ADM8211C/CR Bulls PCI/Cardbus/Mini-PCI WLAN MAC/BBP controller Data Sheet Infineon-ADMtek Co Ltd Information in this document is provided in connection with Infineon-ADMtek products. Infineon-ADMtek may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Infineon-ADMtek reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The products may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. To obtain latest documentation please contact you local Infineon-ADMtek sales office or visit Infineon-ADMtek's website at http://www.ADMtek.com.tw *Third-party brands and names are the property of their respective owners. Copyright 2004 by Infineon-ADMtek Co Ltd All Rights Reserved. Infineon-ADMtek V1.0 About this Manual General Release Intended Audience ADMtek's Customers Structure This Data sheet contains 5 chapters Chapter 1 Product Overview Chapter 2 Interface Description Chapter 3. Register Description Chapter 4. Electrical Specification Chapter 5 Packaging Revision History Date 03 October 2003 Version 1.0 Customer Support ADMtek Incorporated, 2F, No.2, Li-Hsin Rd., Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Sales Information Tel + 886-3-5788879 Fax + 886-3-5788871 Change First release of ADM8211C Infineon-ADMtek V1.0 Table of Contents Chapter 1 Product Overview ........................................................................................ 1-1 1.1 Overview.......................................................................................................... 1-1 1.2 Application....................................................................................................... 1-1 1.3 Features ............................................................................................................ 1-1 1.3.1 Host PCI interface ................................................................................... 1-1 1.3.2 Industry standard ..................................................................................... 1-1 1.3.3 802.11 MAC ............................................................................................. 1-1 1.3.4 WEP ......................................................................................................... 1-2 1.3.5 WLAN TX/RX FIFO ................................................................................. 1-2 1.3.6 WLAN Base Band Processor, BBP .......................................................... 1-2 1.3.7 WLAN Synthesizer Interface .................................................................... 1-2 1.3.8 EEPROM.................................................................................................. 1-2 1.3.9 LED Display............................................................................................. 1-3 1.3.10 Miscellaneous .......................................................................................... 1-3 1.4 ADM8211C Block Diagram ............................................................................ 1-3 1.5 Application Diagram........................................................................................ 1-4 1.5.1 ADM8211CR............................................................................................ 1-4 1.5.2 ADM8211C .............................................................................................. 1-4 1.6 Abbreviations................................................................................................... 1-5 1.7 Conventions ..................................................................................................... 1-7 1.7.1 Data Lengths............................................................................................ 1-7 1.7.2 Register Descriptions............................................................................... 1-7 Chapter 2 Interface Description ................................................................................... 2-1 2.1 Pin Diagram ........................................................................................................... 2-1 2.1.1 ADM8211CR............................................................................................ 2-1 2.1.2 ADM8211C .............................................................................................. 2-2 2.2.1 PHY interface, Pin, 1~22/QFP128, RFMD ............................................. 2-3 2.2.2 PHY interface, Pin, 1~22/QFP128, Maxim/Philips................................. 2-3 2.2.3 PCI interface............................................................................................ 2-4 2.2.4 EEPROM Interface .................................................................................. 2-6 2.2.5 LED display, GPIO, Test ......................................................................... 2-6 2.2.6 Serial Interface to Synthesizer, clock pins ............................................... 2-7 2.2.7 On chip regulator Pins............................................................................. 2-7 Chapter 3 Register Description .................................................................................... 3-1 3.1 PCI Configuration Registers, CR..................................................................... 3-1 3.1.1 WLAN PCI Configuration Registers Map (Needs Work) ........................ 3-1 3.1.2 LID, CR0 offset = 00h.............................................................................. 3-2 3.1.3 CSC, CR1 offset = 04h............................................................................. 3-2 3.1.4 CC, CR2 offset = 08h............................................................................... 3-3 3.1.5 LT, CR3 offset = 0ch................................................................................ 3-3 3.1.6 IOBA, CR4 offset = 10h ........................................................................... 3-4 3.1.7 MBA, CR5 offset = 14h............................................................................ 3-4 3.1.8 CIS, CR6 offset = 28h .............................................................................. 3-4 3.1.9 SID, CR11 offset = 2ch ............................................................................ 3-4 3.1.10 BRBA, CR12 offset = 30h ........................................................................ 3-5 ADM8211C i Infineon-ADMtek V1.0 3.1.11 CP, CR13 offset = 34h............................................................................. 3-5 3.1.12 CI, CR15 offset = 3ch .............................................................................. 3-5 3.1.13 DS, CR16 offset = 40h ............................................................................. 3-6 3.1.14 SIG, CR32 offset = 80h............................................................................ 3-6 3.1.15 PMT0, CR48 offset = c0h ........................................................................ 3-6 3.1.16 PMR1, CR49 offset = c4h ........................................................................ 3-7 3.2 Host Control and Status Register, CSR ........................................................... 3-8 3.2.1 PAR, CSR0 offset = 00h........................................................................... 3-9 3.2.2 FRCTL, CSR0A offset= 04h................................................................... 3-10 3.2.3 TDR, CSR1 offset = 08h ........................................................................ 3-11 3.2.4 WTDP, CSR1A offset=0ch ..................................................................... 3-11 3.2.5 RDR, CSR2 offset =10h ......................................................................... 3-11 3.2.6 WRDP, CSR2A offset =14h ................................................................... 3-12 3.2.7 RDB, CSR3 offset =18h ......................................................................... 3-12 3.2.8 TDBH, CSR3A offset =1Ch ................................................................... 3-12 3.2.9 TDBD, CSR4 offset =20h....................................................................... 3-12 3.2.10 TDBP, CSR4A offset =24h..................................................................... 3-12 3.2.11 STSR, CSR5 offset =28h ........................................................................ 3-12 3.2.12 TDBB, CSR5A offset =2Ch .................................................................... 3-14 3.2.13 NAR, CSR6 offset = 30h ........................................................................ 3-14 3.2.14 IER, CSR7 offset = 38h.......................................................................... 3-16 3.2.15 TKIPSCEP, CSR7A offset = 3Ch........................................................... 3-17 3.2.16 LPC, CSR8 offset = 40h......................................................................... 3-17 3.2.17 CSR_TEST1, CSR8A offset = 44h.......................................................... 3-17 3.2.18 SPR, CSR9 offset = 48h ......................................................................... 3-18 3.2.19 CSR_TEST0, CSR9A offset = 4Ch......................................................... 3-18 3.2.20 WCSR, CSR10 offset = 50h.................................................................... 3-19 3.2.21 SRAM BIST , CSR10A offset = 54h ....................................................... 3-20 3.2.22 GPTMR, CSR11 offset = 58h................................................................. 3-20 3.2.23 GRIO, CSR11A offset = 5Ch ................................................................. 3-21 3.2.24 BBPCTL, CSR12 offset = 60h................................................................ 3-21 3.2.25 SYNCTL, CSR12A offset = 64h.............................................................. 3-22 3.2.26 PLCPHD, CSR13 offset = 68h .............................................................. 3-22 3.2.27 MMIWA, CSR13A offset = 6Ch ............................................................. 3-23 3.2.28 MMIRD0, CSR14 offset = 70h............................................................... 3-23 3.2.29 MMIRD1, CSR14A offset = 74h ............................................................ 3-23 3.2.30 TXBR, CSR15 offset = 78h .................................................................... 3-23 3.2.31 SYNDATA, CSR15A offset = 7Ch .......................................................... 3-24 3.2.32 ALC Statistics, CSR16 offset = 80h ....................................................... 3-24 3.2.33 TOFS2, CSR17 offset = 84h .................................................................. 3-24 3.2.34 CMDR, CSR18 offset = 88h................................................................... 3-24 3.2.35 PCIC, CSR19 offset = 8Ch .................................................................... 3-25 3.2.36 PMCSR, CSR20 offset = 90h ................................................................. 3-25 3.2.37 PAR0, CSR21 offset = 94h..................................................................... 3-26 3.2.38 PAR1, CSR22 offset = 98h..................................................................... 3-27 3.2.39 MAR0, CSR23 offset = 9Ch ................................................................... 3-27 ADM8211C ii Infineon-ADMtek V1.0 3.2.40 MAR1, CSR24 offset = A0h ................................................................... 3-27 3.2.41 ATIMD A0, CSR25 offset = A4h ............................................................ 3-27 3.2.42 ABDA1, CSR26 offset = A8h ................................................................. 3-28 3.2.43 CSR27, BSSID0, BSSID address register 0 ........................................... 3-28 3.2.44 TXLMT, CSR28 ...................................................................................... 3-28 3.2.45 CSR29, MIBCNT, RTS/ACK/FCS MIB Count ....................................... 3-28 3.2.46 CSR30, BCNT, Beacon Transmission Time........................................... 3-28 3.2.47 CSR31, TSFTH, TSFT Value High ........................................................ 3-29 3.2.48 CSR32, TSC, Count down value for TSFT[39:28] ................................ 3-29 3.2.49 CSR33, SYNRF direct control................................................................ 3-29 3.2.50 CSR34, BPLI, Beacon Interval and STA Listen Interval ....................... 3-30 3.2.51 CSR35, CAP0, Capability Parameter 0................................................. 3-30 3.2.52 CSR36, CAP1, Capability Parameter 1................................................. 3-31 3.2.53 CSR37, RMD, RX MAX Duration .......................................................... 3-31 3.2.54 CSR38, CFPP, CFP Parameter............................................................. 3-31 3.2.55 CSR39, TOFS0, Timing Offset Parameter 0.......................................... 3-31 3.2.56 CSR40, TOFS1, Timing Offset Parameter 1.......................................... 3-32 3.2.57 CSR41, IFST, IFS Timing Parameter .................................................... 3-32 3.2.58 CSR42, RSPT, Response Time Register................................................. 3-32 3.2.59 CSR43, TSFTL, TSFT Value Low .......................................................... 3-32 3.2.60 CSR44, WEPCTL, WEP Control ........................................................... 3-33 3.2.61 CSR45, WESK, Data Entry for Share/Individual Key ........................... 3-33 3.2.62 CSR46, WEPCNT, WEP Count.............................................................. 3-33 3.2.63 CSR47, Reserved.................................................................................... 3-34 3.2.64 Function Event Register (Memory base offset 100h)............................. 3-34 3.2.65 Function Event Mask Register (Memory base offset 104h) ................... 3-34 3.2.66 Function Present State Register (Memory base offset 108h)................. 3-35 3.2.67 Function Force Event Register (Memory base offset 10Ch) ................. 3-35 Chapter 4 Electrical Specification................................................................................ 4-1 4.1 Absolute Maximum Ratings ............................................................................ 4-1 4.2 Operating Condition......................................................................................... 4-1 4.3 DC Specifications ............................................................................................ 4-1 4.3.1 Interface DC specification ....................................................................... 4-1 4.3.2 EEPROM Interface DC specification ...................................................... 4-1 4.3.3 GPIO Interface DC Specification ............................................................ 4-1 4.4 Timing Specifications ...................................................................................... 4-2 4.4.1 Reset Timing............................................................................................. 4-2 4.4.2 EEPROM Interface Timing Specification................................................ 4-2 Chapter 5 Packaging...................................................................................................... 5-1 4.1 128-pin Low Profile Quad Flat Package (LQFP) ............................................ 5-1 ADM8211C iii Infineon-ADMtek V1.0 List of Figures Figure 4-1 EEPROM Interface Timings .......................................................................... 4-2 ADM8211C iv ADM8211C Product Review Chapter 1 Product Overview 1.1 Overview The ADM8211C is a WLAN MAC/BBP controller. A high performance PCI, Cardbus, Mini-PCI device integrates: * WLAN MAC controller integrated BBP. * AP/STA controller * IEEE 802.11, 802.11b, 802.11d, 802.11i 1.2 Application * Wireless LAN Network Interface Card, AP or STA * AP repeater * STA converter 1.3 Features 1.3.1 Host PCI interface * Provides 32-bit PCI bus master data transfer * Supports network operation with PCI system clock from 22 MHz to 33MHz * Provides performance meter, PCI bus master latency timer, for tuning the threshold to enhance the performance * Provides burst transmit packet interrupt to reduce host CPU utilization. * Supports memory-read, memory-write, command while being bus master * Supports big or little endian byte ordering * Arbitration between DMA channel to minimize underflow or overflow 1.3.2 Industry standard * PCI 2.2 /Cardbus interface * ACPI and PCI power management 1.1 standard compliant * IEEE802.11, b/d/i 1.3.3 802.11 MAC * Support AP/STA/STA converter/AP repeater operation * Support Infrastructure, Ad-hoc under DCF * Implementation of the Point Coordination Function (PCF) operation * RTS/CTS generation, fragmentation, beacon monitor/loss detection/generation. * Probe response/Beacon generation by H/W or S/W * Auto 2, high or low, rate switching * RX DA address filtering (multicast) with 64 entries. Infineon-ADMtek 1-1 ADM8211C Product Review * * * * * * TIM field decoding at Beacon frame reception Support DSSS PHY. Front end chip power sequence control Power save mode support MAC implements with State Machine No External SRAM needed 1.3.4 WEP * Hardwired WEP function, RC-4, 40/104 bits key. * Hardwired TKIP 128 bits key. * Support WPA. * Randomly generated IV for TX. * ICV generation and check. * 4 default shared key supported. * TA/RA individual key management with 32 entries table. * Enable individual key table extension by S/W 1.3.5 WLAN TX/RX FIFO * Provides two independent FIFO with TXFIFO 2.5K(640*32) bytes, RXFIFO 2K(512*34) bytes for transmitting and receiving. * Bus master descriptor based host memory access. * Pre-fetch up to two transmit packets to guarantee standard inter frame space (IFS). * Re-transmits no-acked packet without reloading from host memory. * Support 4 TX descriptors pointers for DCF, PCF, high priority, buffered mc/bc applications. 1.3.6 WLAN Base Band Processor, BBP * ADMtek 1.3.7 WLAN Synthesizer Interface * RFMD RF2958 * Philips SA-2400A * Maxim MAX2820 1.3.8 EEPROM * Provides serial interface for read/write 93C46/93C66 EEPROM. * Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and Minimum-Grand from the 64 byte contents of 93C46/93C66 after PCI reset de-asserted in PCI environment. * CIS data is recalled from 93C66 through ADM8211C in CARDBUS environment. Infineon-ADMtek 1-2 ADM8211C 1.3.9 Product Review LED Display * Link: Keep On while link, S/W or H/W control. * Activity: 10Hz Blinking. 1.3.10 Miscellaneous * Low power application * Power save mode * Wake up function (Magic packet only) * Supports 4 GPIO pins * CMOS .18um 1P5M Process * 128/LQFP (ADM8211B compatible) * On chip 3.3V ~ 1.8V regulator controller * 3.3V power supply with 5V/3.3V I/O tolerance 1.4 ADM8211C Block Diagram Infineon-ADMtek 1-3 ADM8211C 1.5 Product Review Application Diagram 1.5.1 ADM8211CR PCI / miniPCI / Cardbus Interface EEPROM ADM8211CR MAC+BBP PA SAW 44M Hz Crystal 1.5.2 RFMD/RF LEDs ADM8211C PCI / miniPCI / Cardbus Interface EEPROM ADM8211C MAC+BBP PA SAW 44M Hz Crystal Infineon-ADMtek Maxim/Philips/others RF LEDs 1-4 ADM8211C 1.6 Product Review Abbreviations ACK ACPI ADDA AES AESSC AGC AID AIE ALC AP APM ASIC ATIM BBP BSSID CAL CAM CCA CFP CIS CP CR CRC CSR CSTSCHG CTS DCF DMA DS DSSS DTIM DW dxfer FBE FCS FIFO GPIO ICV IFS LNA LNAGS MAC MCLK MDI Infineon-ADMtek Acknowledge Advanced Computer Peripheral Interface A/D converter and D/A converter Advanced Encryption Standard AES Sequence Count Automatic Gain Control Association Identifier Abnormal Interrupt Enable Amplify Level Control Access Point Advanced Power Management Application Specific Integrated Circuit Announcement Traffic Indication Message Base Band Processor Basic Service Set Identification Cache Alignment Content Access Memory Clear Channel Assessment Contention - free Period Card Info Structure Contention Period Command Register Cyclic Redundancy Code Control and Status Register Card Status Changed Clear to Send Distributed Coordination Function Dynamic Memory Access Distribution System Direct Sequence Spread Spectrum Delivery Traffic Indication Message Double Word DMA transfer Fatal Bus Error Frame Check Sequence First-in First-out General Purpose Input Output Integrity Check Value Inter Frame Space Low Noise Amplifier Low noise Amplifier Gain Selection Media Access Controller MAC Clock Modem Data Interface 1-5 ADM8211C Product Review MIB MMI mc / bc MPDU MSDU NIE PA PCF PCIC PHY PLCP PLCPHD PMEP PMES PMR PME PMES PS PSP RA RCVDTIM rfifo RSSI RTS Rx rxpe SAW SCB SPI STA SYN TA TBTT TDBB TDBH tfifo TIM TKIP TKIPSC TMAC TRSW trdy TSFT TU Tx txpe Infineon-ADMtek Management Information Base Modem Management Interface Multicast / Broadcast MAC Protocol Data Unit MAC Service Data Unit Normal Interrupt Enable Power Amplify Point Coordination Function PCI Bus Performance Counter Physical Layer Physical Layer Convergence Protocol PLCP Header PME Pulse PME Status Power Management Register Power Management Event PME Status Power Save Power Save Procedure Receiver Address Receive Delivery Traffic Indication Message RXFIFO Received Signal Strength Indication Request to Send Receive RX Power Enable Surface Acoustic Wave System Control Block Serial Pin Information Station Synchronization Transmitter Address Target Beacon Transmission Time TX Descriptor Base Address for Buffered bc / mc packet TX Descriptor Base Address for TX High Priority queue TX FIFO Traffic Indication Map Temporal Key Integrity Protocol TKIP Sequence Count Transmit MAC Transceiver Switch TX ready Timing Synchronization Function Timer Time Unit Transmit TX Power Enable 1-6 ADM8211C Product Review WEP WEP ICV WPA Wired Equivalent Privacy WEP Initial Checksum Value WiFi Protected Access 1.7 Conventions 1.7.1 Data Lengths qword dword word byte nibble 1.7.2 64-bits 32-bits 16-bits 8 bits 4 bits Register Descriptions Register Type RO WO RW Infineon-ADMtek Description Read-only Write-only Read/Write 1-7 ADM8211C Interface Description Chapter 2 Interface Description 2.1 Pin Diagram 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 VDDAH REGCTL VSSAH VSENSE VSSIO CLKOUT CLKIN CLKBOUT VDDIO LEIF# SYNDATA SYNCLK NC NC NC NC VDDR VDDIO PWDN NC NC NC VSSR GPIO0 GPIO1 GPIO2 GPIO3 VSSIO EECS EECK EEDI EEDO 2.1.1 ADM8211CR RXPE NC NC NC TXPE NC VDD_ANALOG ADM8211CR 128 LQFP 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 LEDACT LEDLINK MON0 TEST# PCI/CB VDD-DETECT Vaux3.3 AD0 AD1 CLKRUN VDDR AD2 AD3 AD4 VSSIO AD5 AD6 AD7 C-BEB0 VDDIO AD8 VSSR AD9 AD10 AD11 AD12 VSSIO AD13 AD14 VDDIO AD15 C-BEB1 AD30 AD29 AD28 VDDIO AD27 AD26 AD25 AD24 VSSIO C-BEB3 IDSEL VSSR AD23 AD22 AD21 AD20 AD19 AD18 VSSIO AD17 AD16 VDDR C-BEB2 FRAME# VDDIO IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VSSIO PA_PE NC NC RxVGC RXI_P RXQ_P VDDA GNDA TXI_P TXQ_P TxVGC VREF ANTSEL LNA_GS VSSR INTA# RST# VSSIO PCI-CLK VDDIO GNT# REQ# CSTSCHG AD31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Infineon-ADMtek. 2-1 ADM8211C ADM8211C 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 VDDAH REGCTL VSSAH VSENSE VSSIO CLKOUT CLKIN CLKBOUT VDDIO LEIF# SYNDATA SYNCLK NC NC NC NC VDDR VDDIO PWDN NC NC NC VSSR GPIO0 GPIO1 GPIO2 GPIO3 VSSIO EECS EECK EEDI EEDO 2.1.2 Interface Description RXPE TX_DATA_Q TXPE VDD_ANALOG ADM8211C 128 LQFP 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 LEDACT LEDLINK MON0 TEST# PCI/CB VDD-DETECT Vaux3.3 AD0 AD1 CLKRUN VDDR AD2 AD3 AD4 VSSIO AD5 AD6 AD7 C-BEB0 VDDIO AD8 VSSR AD9 AD10 AD11 AD12 VSSIO AD13 AD14 VDDIO AD15 C-BEB1 AD30 AD29 AD28 VDDIO AD27 AD26 AD25 AD24 VSSIO C-BEB3 IDSEL VSSR AD23 AD22 AD21 AD20 AD19 AD18 VSSIO AD17 AD16 VDDR C-BEB2 FRAME# VDDIO IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VSSIO PAPE AGCRESET AGCSET RXVGC RXI_P RXI_M RXQ_P RXQ_M VDDA GNDA TXI_P TXI_M TXQ_P TXQ_M TXVGC ANTSEL LNA_GS VSSR INTA# RST# VSSIO PCI-CLK VDDIO GNT# REQ# CSTSCHG AD31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Infineon-ADMtek. 2-2 ADM8211C Interface Description 2.2 Pin Description by Function ADM8211C/CR pins are categorized into one of the following groups: Section 2.2.1 PHY interface, Pin, 1~22/QFP128, RFMD Section 2.2.2 PHY interface, Pin, 1~22/QFP128, Maxim/Philips Section 2.2.3 PCI interface Section 2.2.4 EEPROM Interface Section 2.2.5 LED display, GPIO, Test Section 2.2.6 Serial Interface to Synthesizer, clock pins Section 2.2.7 On chip regulator Pins 2.2.1 PHY interface, Pin, 1~22/QFP128, RFMD Pin Name RXPE NC NC NC TXPE NC VDD_ANA LOG VSSIO PAPE NC NC RXVGC RXI_P RXQ_P VDDA GNDA TXI_P TXQ_P TXVGC VREF ANTSEL LNAGS/TR SW 2.2.2 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Type O I/O Description PHY Receive Enable, operational or standby mode, 4mA, pull-down Test pin Test Pin Test pin PHY Transmit Power Enable Configure the transmitter in operational or standby mode, 4mA, pull-down Test pin P Analog Power for ADDA, 1.8V P O O Ground for IO Transmit PA Power Enable, 4mA, internal pull-down. Test Pin Test Pin Analog receive variable gain control output: 1.2V to 2.0V. Analog I input. Analog Q input. Analog Power 3.3V Analog Ground Analog I output: 1.6V to 1.8V. Analog Q output: 1.6V to 1.8V. Analog voltage for transmitter variable gain control: 1.2V to 2.0V. Reference voltage for internal data converters. Connect to RF2938 VREF or set to 1.7VDC. Antenna selection signal for diversity receiver. O LNA gain select. "1" indicates "high gain". AO AI AI P P AO AO AO I PHY interface, Pin, 1~22/QFP128, Maxim/Philips Pin Name RXPE TX_DATA_ Q TXPE VDD_ANA LOG Infineon-ADMtek. Pin# 1 2 3 4 Type O Description PHY Receive Enable, operational or standby mode, 4mA pull-down O Transmit data Q for SA2400A O PHY Transmit Power Enable Configure the transmitter in operational or standby mode, 4mA pull-down P Analog Power for ADDA, 1.8V 2-3 ADM8211C Interface Description Pin Name VSSIO PAPE AGCRESE T AGCSET RXVGC RXI_P RXI_M RXQ_P RXQ_M VDDA GNDA TXI_P TXI_M TXQ_P TXQ_M TXVGC ANTSEL LNAGS/TR SW 2.2.3 Pin# 5 6 7 Type P O 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 I AO AI AI AI AI P P AO AO AO AO AO O O O Description Ground for IO Transmit PA Power Enable, 4mA AGC start to SA2400A AGC settled from SA2400A Analog receive variable gain control output: 1.2V to 2.0V. Analog I input, differential +. Analog I input, differential-. Analog Q input, differential +. Analog Q input, differential -. Analog Power 3.3V Analog Ground Analog I output, differential + Analog I output, differential Analog Q output, differential + Analog Q output, differential Analog voltage for transmitter variable gain control: 1.2V to 2.0V. Antenna selection signal for diversity receiver. MAXIM=LNAGS: LNA gain select. "1" indicates "high gain". PHILIPS=TRSW: TR switch control. PCI interface Pin Name VSSR INTA# RST# Pin# 23 24 25 Type P O/D I VSSIO PCICLK 26 27 P I VDDIO GNT# 28 29 P I REQ# PME# / CSTSCHG AD31 AD30 AD29 AD28 VDDIO AD27 AD26 AD25 AD24 VSSIO CBEBZ3 IDSEL 30 31 O I/O 32 33 34 35 36 37 38 39 40 41 42 43 I/O I/O I/O I/O P I/O I/O I/O I/O P I/O I Infineon-ADMtek. Description Ground for core PCI interrupt acknowledge. PCI reset signal, at least 100s. During the reset period, all the output pins of ADM8211C will be set to tri-state and all the O/D pins are floated. Ground for IO This PCI clock inputs to ADM8211C. The bus signals are recognized on rising edge of PCI-CLK. The frequency range of PCI-CLK is limited between 20MHz and 33MHz. Power for IO, 3.3V This signal indicates that the bus request of ADM8211C have been accepted. Bus master device request. The Power Management Event signal is an open drain, active low signal for PCI (PME#). Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Power for IO, 3.3V Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Ground for IO Bus command and byte enable Initialization Device Select. This signal is asserted when host issues the configuration cycles to the ADM8211C. 2-4 ADM8211C Pin Name VSSR AD23 AD22 AD21 AD20 AD19 AD18 VSSIO AD17 AD16 VDDR CBEBZ2 FRAME# VDDIO IRDY# TRDY# Interface Description STOP# PERR# SERR# PAR Pin# 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Type P I/O I/O I/O I/O I/O I/O P I/O I/O P I/O I/O P I/O I/O I/O I/O I/O O/D I/O CBEBZ1 AD15 VDDIO AD14 AD13 VSSIO AD12 AD11 AD10 AD9 VSSR AD8 VDDIO CBEBZ0 65 66 67 68 69 70 71 72 73 74 75 76 77 78 I/O I/O P I/O I/O P I/O I/O I/O I/O P I/O P I/O AD7 AD6 AD5 VSSIO AD4 AD3 AD2 VDDR CLKRUN 79 80 81 82 83 84 85 86 87 I/O I/O I/O P I/O I/O I/O P I/O O/D DEVSEL# Infineon-ADMtek. Description Digital ground for core Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Ground for IO Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Digital power, 1.8V Bus command and byte enable Begin and duration of bus access, driven by master device Power for IO, 3.3V Master device is ready to data transaction Slave device for ready to data transaction Device select, target is driving to indicate the address is decoded Target device requests the master device to stop the current transaction Data parity error is detected, driven by the agent receiving data Address parity error Parity, even parity (AD[31:0] + C/BE[3:0]), master drives par for address and write data phase, target drives par for read data phase Bus command and byte enable Multiplexed address data pin of PCI Bus Power for IO, 3.3V Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Ground for IO Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Digital ground for core Multiplexed address data pin of PCI Bus Power for IO, 3.3V Bus command and byte enable Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Ground for IO Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus Digital power, 1.8V Clock Run for PCI system. In the normal operation situation, Host should assert this signal to indicate ADM8211C about the normal situation. On the other hand, when Host will de-assert this signal when the clock is going down to a no operating frequency. When ADM8211C recognizes the de-asserted status of clk-run, then it will assert clk-run to request host to maintain the normal clock operation. When clk-run function is disabled then the ADM8211C will set clk-run in tri-state. 2-5 ADM8211C Interface Description Pin Name AD1 AD0 Vaux3.3 Pin# 88 89 90 Type I/O I/O I VDDdetect 91 I PCI/CB# 92 93 I 94 I/O I/O TEST# MON0 95 LEDLINK MON1 96 LEDACT 2.2.4 I I/O LED Drive, on when link MON1 For test, 8mA LED Drive Flash on TX/RX pkt, 8mA EEPROM Interface Pin Name Pin# EDO 97 Type I/O EDI ECK 98 99 I/O I/O EECS 100 I/O VSSIO 101 P 2.2.5 Description Multiplexed address data pin of PCI Bus Multiplexed address data pin of PCI Bus When this pin is asserted, it indicates an auxiliary power source is supported. ACPI purpose , for detecting the auxiliary power source . Schmmit trigger 5V tolerant When this pin is asserted, it indicates PCI power source is supported. ACPI purpose , for detecting if the main power still remains, this pin should be connected to PCI bus power source +3.3V. Schmmit trigger 5V tolerant Select CARD bus mode. Internal pull up. 5V-tolerant Chip test pin, active low. For test only. Schmitt Trigger Input with Pull-up. For test, 4mA Description EDO: Data input from serial EEPROM pull-up, 5V tolerant, 4mA EDI: Data output to serial EEPROM., 5V tolerant, 4mA ECK: Clock output to serial EEPROM, 5V tolerant, 4mA Chip Select of serial EEPROM, active high Pull-down, 5V tolerant, 4mA Ground for IO LED display, GPIO, Test Pin Name GPIO[3] GPIO[2] GPIO[1] GPIO[0] VSSR NC NC Pin# 102 103 104 Type I/O I/O I/O 105 I/O 106 107 P I/O 108 I/O 109 NC Infineon-ADMtek. I/O Description General purpose IO, Pull-up, 5V tolerant, 12mA General purpose IO, Pull-up, 5V tolerant, 12mA General purpose IO Pull-up, 5V tolerant, 12mA General purpose IO (BW_SEL output in ADM8211A) Pull-up, 5V tolerant, 12mA Digital ground for core Test pin, RXD: Receive Data In, 4mA, pull-down Test pin, RXC: Receive Clock In, 4mA pull-down Test pin, RXRDY, PHY Receive Ready, Header data and data packet are ready to be transferred from BBP on RXD. 4mA pull-down 2-6 ADM8211C Interface Description Pin Name PWDN VDDIO VDDR NC NC NC NC 2.2.6 Pin# 110 111 112 113 Type O P P I/O 114 I/O 115 I/O 116 I/O Serial Interface to Synthesizer, clock pins Pin Name SYNCLK SYNDATA LEIF# VDDIO ClkBOUT Pin# 117 118 119 120 121 Type O I/O O P O Clk44IN Clk44O VSSIO 122 123 124 I O P 2.2.7 Description Power down Signal output, active low, 4mA Power for IO, 3.3V Power for Core, 1.8V Test Pin, SPIDout Data Out pin. 4mA pull-down Test Pin, SPIClk, SPI clock output, 4mA pull-down Test Pin, SPIDin, Data Input pin with pull low. 4mA pull-down Test pin, SPICS# SPI Chip select, 4mA pull-up Description Synthesizer interface Clock, 4mA Synthesizer Data in/out, 4mA Synthesizer interface Select, 4mA. Power for IO, 3.3V Buffered 44Mhz clock output This signal will be stopped, forced low, during MAC enter into power saving mode. 4mA, 44 Mhz OSC input 44 Mhz OSC output Ground for IO On chip regulator Pins Pin Name VSENSE VSSAH REGCTL VDDAH Infineon-ADMtek. Pin# 125 126 127 128 Type I P I/O P Description 1.8V sense input Gnd for regulaor Regulator control pin 3.3V for regulator 2-7 ADM8211C Electrical Specification Chapter 3 Register Description There are 2 kinds of registers: CR =PCI configuration registers CSR=Control and Status registers 3.1 PCI Configuration Registers, CR 3.1.1 WLAN PCI Configuration Registers Map (Needs Work) Offset CR# 00h 04h CR0 CR1 08h CR2 0ch CR3 10h CR4 14h CR5 b31 ----------- b16 b15 ---------- b0 LDID*, Device ID(RO) Status Base Class Subclass Code LVID*, Vendor ID(RO) Command Revision Step # Reserved # LT, Latency CLS,Cache Line Reserved HT, Header Type Timer Size I O IOBA, I/O Base address Reserved S I M MBA, Memory Base address Reserved S I 18h 24h Reserved 28h CR10 2ch CR11 30h CR12 34h 38h 3ch 40h 80h CR13 CR14 CR15 CR16 CR32 c0h CR48 c4h CR49 RI*, ASO*, ASI*, ROMAddress space offset Add-indi im SID*, Subsystem ID(RO) SVID*, Subsystem vendor ID(RO) BRBA, Boot ROM base address[31:17] R Reserved B R E * Reserved Cap_Ptr Reserved ML*, Max_Lat MG*, Min_Gnt IP, Interrupt pin IL, Interrupt line Reserved Driver Space Reserved Signature of WLAN PMES, D2S, D1S, AUXC, DSI, --, NIP, CAPID, Cap_ID PMEC, VER Next_Item_Ptr Data register* Reserved PMCSR Table 1 Function 2: WLAN PCI configuration registers table Note: automatically recalled from EEPROM when PCI reset is deserted Infineon-ADMtek 3-1 ADM8211C Electrical Specification CIS(28h) is a read-only register DS(40h), bit15-8, is read/write able register SIG(80h) is hard wired register, read only. Data register(C7h) is provided from EEPROM, CSR-CMDR. See Section PCI Configuration Registers Description. 3.1.2 LID, CR0 offset = 00h Note: LID: Loaded Identification number of Device and Vendor Bits 31:16 Type Name R/O LDID 15:0 R/O 3.1.3 LVID Type Name R/W SPE W1C 30 R/W SES W1C R/W SMA W1C 28 27 26:25 Initial value 8211h 1317h CSC, CR1 offset = 04h Note: CSC: Configuration command and status Bits 31 29 Description Loaded Device ID, the device ID number loaded from serial EEPROM. Loaded Vendor ID, the vendor ID number loaded from serial EEPROM. R/W STA W1C R/O Reserved SDST 24 R/W SDPR W1C 23 R/O SFBB 22:21 20 RO Reserved NC 19:9 8 Reserved R/W CSE Infineon-ADMtek Description Initial value Status of Parity Error. 0 1: means that WLAN detected a parity error. This bit will be set in this condition, even if the parity error response(bit 6 of CR1) is disabled. Status of System Error. 0 1: means that WLAN asserted the system error pin. Status of Master Abort. 0 1: means that WLAN received a master abort and terminated a master transaction. Status of Target Abort. 0 1: means that WLAN received a target abort and terminated a master transaction. Not Applicable Status of Device Select Timing. The timing of the assertion of device 01 select. 01: means a medium assertion of DEVSEL# Status of Data Parity Report. 0 1: when three conditions are met: WLAN asserted parity error - PERR# or it detected parity error asserted by other device. WLAN is operating as a bus master. WLAN's parity error response bit (bit 6 of CR1) is enabled. Status of Fast Back-to-Back 1 Always 1, since WLAN has the ability to accept fast back to back transactions. Not Applicable New Capabilities. This bit indicates that whether the WLAN provides Same as bit a list of extended capabilities, such as PCI power management. 19 of CSR18 1: the WLAN provides the PCI management function 0: the WLAN doesn't provide New Capabilities. Not Applicable Command of System Error Response 0 1: enable system error response. WLAN will assert SERR# When it find a parity error on the address phase. 3-2 ADM8211C Electrical Specification Bits 7 6 Type Name Reserved R/W CPE 5:3 2 Reserved R/W CMO 1 R/W CMSA 0 R/W CIOSA 3.1.4 Bits 31:24 23:16 15:8 7:4 3:0 3.1.5 Bits 31:24 23:16 15:8 7:0 Description Not Applicable Command of Parity Error Response 0: disable parity error response. WLAN will ignore any detected parity error and keep on its operating. Default value is 0. 1: enable parity error response. WLAN will assert system error (bit 13 of CSR5) when a parity error is detected. Not Applicable Command of Master Operation Ability 0: disable the bus master ability. 1: enable the PCI bus master ability. Default value is 1 for normal operation. Command of Memory Space Access 0: disable the memory space access ability. 1: enable the memory space access ability. Command of I/O Space Access 0: enable the I/O space access ability. 1: disable the I/O space access ability. Initial value 0 0 0 0 CC, CR2 offset = 08h Note: CC: Class Code and Revision Number Type RO RO RO RO RO Name BCC SC Reserved RN SN Description Base Class Code. It means WLAN is network controller. Subclass Code. It means WLAN is an other network controller. Not Applicable Revision Number identifies the revision number of WLAN. Step Number, identifies the WLAN steps within the current revision. Initial value 02h 80h 00h 3h 0h LT, CR3 offset = 0ch Note: LT: Latency Timer Type Name Reserved RO HT R/W LT R/W CLS Infineon-ADMtek Description Initial value Not Applicable Single function device 00h Latency Timer. This value specifies the latency timer of the WLAN 0 in units of PCI bus clock. Once the WLAN asserts FRAME#, the latency timer starts to count. If the latency timer expires and the WLAN still asserted FRAME#, then the WLAN will terminate the data transaction as soon as its GNT# is removed. Cache Line Size. This value specifies the system cache line size in 0 units of 32-bit double words(DW). The WLAN supports 8, 16, and 32 DW of cache line size. This value is used by the WLAN driver to program the cache alignment bits(bit 14 and 15 of CSR0). The cache alignment bits are used for cache oriented PCI commands, say memory-read-line, memory-read-multiple, and memory-writeand-invalidate. 3-3 ADM8211C Electrical Specification 3.1.6 IOBA, CR4 offset = 10h Note: IOBA: I/O Base Address Bits 31:8 7:1 0 3.1.7 Bits 31:10 9:1 0 3.1.8 Bits 31:28 Type Name R/W IOBA RO Reserved IOSI Type Name R/W MBA RO Reserved MSI Type Name RO RI ASO 2:0 RO ASI 15:0 1 Description Memory Base Address. This value indicates the base address of PCI control and status register (CSR0~28) Not Applicable Memory Space Indicator. 1: means that the configuration registers map into the memory space. Initial value 0 0 CIS, CR6 offset = 28h Note: CIS: Card Information Structure. This register is used to point one of the possible address spaces where the CIS begins. This register is designed for PCI environment. Its data is auto-loaded from the serial EEPROM after power on or hardware reset. RO Bits 31:16 Initial value 0 MBA, CR5 offset = 14h Note: MBA - Memory Base Address 27:3 3.1.9 Description I/O Base Address. This value indicates the base address of PCI control and status register (CSR0~28) Not Applicable I/O Space Indicator. 1: means that the configuration registers map into the I/O space. Description Initial value ROM Image. This ROM image value is applied when the CIS is From stored in a boot ROM. This value is loaded from serial EEPROM. EEPROM Address Space Offset. This value indicates the offset within the From address space. The address space is specified by address space EEPROM indicator(bit 2~0 of CR10). Address Space Indicator. This value indicates the location where the From CIS address space begins. EEPROM 7: means that the CIS begins in the boot ROM space. Other than 7: makes all the bits of CIS reset to 0. SID, CR11 offset = 2ch Note: SID: Subsystem ID Type Name RO SID RO Infineon-ADMtek SVID Description Subsystem ID. This value is loaded from EEPROM after power on or hardware reset. Subsystem Vendor ID. This value is loaded from EEPROM after power on or hardware reset. Initial value From EEPROM From EEPROM 3-4 ADM8211C 3.1.10 Bits 31:17 Electrical Specification BRBA, CR12 offset = 30h Note: BRBA: Boot ROM Base Address. This register should be initialized before accessing the boot ROM space. (write 32'hffffffff return 32'h fffe0001) Type Name R/W BRBA RO 16: 1 0 RO Reserved R/W R/W R/W BRE Description Initial value Boot ROM Base Address. This value indicates the address mapping X: b31~b18 of boot ROM field. Besides, it also defines the boot ROM size. The 0: b17~b10 value of bit 17~10 is set to 0 for WLAN supports up to 128kB of boot ROM. Not Applicable 0 Boot ROM Enable. The WLAN really enables its boot ROM access only if both the memory space access bit (bit 1 of CR04h) and this bit are set to 1. 1: enable Boot ROM. (Combines with bit 1 of CR1) 0 0: after Boot Rom is accessed completely, this bit will be set to 0 to enable MDMCS#. 3.1.11 CP, CR13 offset = 34h Note: CP: Capabilities Pointer Bits 31:8 7:0 Type Name Reserved RO CP Description Not Applicable Capabilities Pointer. Initial value C0h 3.1.12 CI, CR15 offset = 3ch Note: CI: Configuration Interrupt Bits 31:24 Type Name RO ML 23:16 RO MG 15:8 RO IP 7:0 R/W IL Infineon-ADMtek Description Initial value Max_Lat From This value indicates "how often" the WLAN needs to access the PCI EEPROM bus; units 250ns. This value is loaded from serial EEPROM after power on or hardware reset. Min_Gnt From This value indicates how long the WLAN needs to retain the PCI bus EEPROM ownership whenever it initiates a transaction; units 250ns. This value is loaded from serial EEPROM after power on or hardware reset. Interrupt Pin. This value indicates which of the four interrupt request 01h pins the WLAN is connected to. Always 01h: means the WLAN connects to INTA# Interrupt Line. X This value indicates which of the system interrupt request lines the INTA# of WLAN is routed to. The BIOS will fill this field when it initializes and configures the system. The WLAN driver can use this value to determine priority and vector information. 3-5 ADM8211C Electrical Specification 3.1.13 DS, CR16 offset = 40h Note: DS: Driver Space for special purpose. Bits 31:16 15:8 Type Name Reserved R/W DS 7:0 Reserved Description Initial value Not Applicable Driver Space for special purpose. Since this area won't be cleared in X the software reset. The WLAN driver can use this R/W area for special purposes. Not Applicable 3.1.14 SIG, CR32 offset = 80h Note: SIG: Signature of WLAN Bits 31:16 15:0 Type Name RO DID RO VID Description Device ID, the device ID number of WLAN. Vendor ID, the vendor ID number of ADM Technology Corp. Initial value 8211h 1317h 3.1.15 PMT0, CR48 offset = c0h Note: PMR0: Power Management Register0. Bits 31:27 Type Name RO PMES 26 RO D2S 25 RO D1S 24:22 RO AUXC 21 RO DSI 20 19 RO RO Reserved PMEC 18:16 RO VER Infineon-ADMtek Description Initial value X1111b PME_Support. The WLAN will assert PME#/CSTSCHG signal while in the D0, D1, D2, D3hot, D3cold power state. The WLAN supports Wake-up from the above four states. XXXX1 - PME# can be asserted from D0 XXX1X - PME# can be asserted from D1 XX1XX - PME# can be asserted from D2 X1XXX - PME# can be asserted from D3hot 1XXXX - PME# can be asserted from D3cold (**bit 31 load from EEPROM= CSR18.PM & CSR18.D3CS) D2_Support. 1 The WLAN supports D2 Power Management State. D1_Support. 1 The WLAN supports D1 Power Management State. Aux Current. 111b The three bits report the maximum 3.3V aux current requirements (**from for ADM8211C. If bit 31 of PMR0 is `1', the default value is 010b, EEPROM.C this means ADM8211C needs 100 mA to support remote wake-up in MDR) D3cold power state. The Device Specific Initialization bit 0 indicates whether special initialization of this function is required before the generic class device driver is able to use it. 0: indicates that the function does not require a device specific initialization sequence following transition to the D0 un-initialized state. Not Applicable 0 PME Clock. 0 When "1" indicates that the WLAN relies on the presence of the PCI clock for PME#/CSTSCHG operation. While "0" indicates the no PCI clock is required for the WLAN to generate PME#/CSTSCHG. Version. 010b The value of 010b indicates that the WLAN complies with Revision 3-6 ADM8211C Bits Electrical Specification Type Name 15:8 RO NIP 7:0 RO CAPID Description 1.1 of the PCI Power Management Interface Specification. Next Item Pointer. This value is always 00h, indicates that there is no additional items in the Capabilities List. Capability Identifier. This value is always 01h, indicates the link list item as being a PCI Power Management Register. Initial value 00h 01h 3.1.16 PMR1, CR49 offset = c4h Note: PMR1: Power Management Register 1 R/W*: Read and Write clear Bits 31:24 Type Name RO DR 23:16 RO Reserved 15 R/W1C PMES 14:13 RO DSCAL 12:9 R/W DSEL 8 R/W PME_En 7:2 1:0 RO Reserved R/W PWRS Infineon-ADMtek Description Initial value Data register 0 This register is used to report the state dependent data requested (EEPROM) by the data_select field . The value of this register is scaled by the value reported by the data_scale field Not Applicable 8'b0 PME_Status 0 This bit is set when the WLAN would normally assert the PME#/CSTSCHG signal for wake-up event, independent of the state of the PME-En bit. Writing a "1" to this bit will clear it and cause the WLAN to stop asserting a PME#/CSTSCHG (if enabled). Writing a "0" has no effect. Data_Scale 2'b10 indicates the scaling factor to be used when interpreting the value of (EEPROM) the Data register. Data_Select 4'b0000 This four bit field is used to select which data is to be reported through the Data register and Data_Scale field. PME_En 0 "1", enables the WLAN to assert PME#/CSTSCHG. "0", disables the PME#/CSTSCHG assertion. Not Applicable 6'b000000 PowerState 2'b00 This two bit field is used both to determine the current power state of the WLAN and to set the WLAN into a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot This field is auto cleared to D0 when power resumed . 3-7 ADM8211C 3.2 Electrical Specification Host Control and Status Register, CSR Note: Number of CSR = 256B Offset 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9ch A0h A4h A8h Ach B0h Index CSR0 CSR0A CSR1 CSR1A CSR2 CSR2A CSR3 CSR3A CSR4 CSR4A CSR5 CSR5A CSR6 CSR6A CSR7 CSR7A CSR8 CSR8A CSR9 CSR9A CSR10 CSR10A CSR11 CSR11A CSR12 CSR12A CSR13 CSR13A CSR14 CSR14A CSR15 CSR15A CSR16 CSR17 CSR18 CSR19 CSR20 CSR21 CSR22 CSR23 CSR24 CSR25 CSR26 CSR27 CSR28 B4h B8h CSR29 CSR30 Infineon-ADMtek Name PAR FRCTL TDR WTDP RDR WRDP RDB TDBH TDBD TDBP STSR TDBB NAR Reserved IER TKIPSCEP LPC CSR_TEST1 SPR CSR_TEST0 WCSR SBIST GPTMR GPIO BBPCTL SYNCTL PLCPHD MMIWA MMIRD0 MMIRD1 TXBR SYNDATA ALCS TOFS2 CMDR PCIC PMCSR PAR0 PAR1 MAR0 MAR1 ATIMDA0 ABDA1 BSSID0 TXLMT MIBCNT BCNT Descriptions PCI access register Frame Control register Transmit demand register Current transmit descriptor pointer Receive demand register Current receive descriptor pointer Receive descriptor base address TX descriptor base address for TX High prioirity queue Transmit descriptor base address, DCF Transmit descriptor base address, PCF Status register TX descriptor base address for buffered bc/mc packet Network register Interrupt enable register TKIPSC counter expired status pending bit. Lost packet counter Test register 1 Serial port register Test register 0 Wake-up Control/Status Register SRAM BIST Register General Purpose Timer GPIO[5:0] Configuration and Control register BBP Control Port SYNTHESIZER Control port PLCP Header Setting MMI write sequence address, for tx vector MMI read sequence address[3:0], for rx vector MMI read sequence address[4], 8b. RXPECNT, 8b Transmit burst counter Synthesizer Data register ALC Statistics Timing Offset Parameter 2, 16b Command register PCI bus performance counter Power Management Command and Status Local MAC address register 0, 32b Local MAC address register 1, 16b Multicast address hash table register 0 Multicast address hash table register 1 ATIM frame DA , byte[3:0] {BSSID address byte[5:4], ATIM frame DA byte[5:4]} BSSID address byte[3:0] WLAN retry limit, 8b Max TX MSDU Life Time, 16b RTS/ACK/FCS MIB Count, 32b Beacon Transmission Time, 32b. 3-8 ADM8211C Electrical Specification BCh C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h Ech F0h F4h F8h FCh 100h 104h 108h 10Ch CSR31 TSFTH CSR32 TSC CSR33 SYNRF CSR34 BPLI CSR35 CAP0 CSR36 CAP1 CSR37 RMD CSR38 CFPP CSR39 TOFS0 CSR40 TOFS1 CSR41 IFST CSR42 RSPT CSR43 TSFTL CSR44 WEPCTL CSR45 WESK CSR46 WEPCNT CSR47 MACTEST FER FEMR FPSR FFER TSFT[63:32], 32b TSFT[39:32] down count value SYN RF IF Direct Control Beacon Interval, 16b. STA Listen Interval, 16b. Current Channel, 4b. RCVDTIM, 1b. Capability Information, 16b. ATIM Window, 16b. RX max reception duration, 16b CFP Parameter, 32b Timing Offset Parameter 0, 28b Timing Offset Parameter 1, 24b IFS Timing Parameter 1, 32b Response time Register, 24b TSFT[31:0], 32b WEP Control Write Entry for Shared/ Indival Key WEP Count, 32b Function Event Register (memory based) Function Event Mask Register Function Present State Register Function Force Event Register Note: All reserved bits are RO with value 0. R/W: read/write access RO: read only RC: read to clear the bit to zero W1C: write one to clear the bit to zero 3.2.1 PAR, CSR0 offset = 00h Note: PAR: PCI Access Register R/W* = before writing, the transmit and receive operations should be stopped. Bits 31:25 24 Type Name RO Reserved R/W* MWIE 23 R/W* MRLE 22 21 RO Reserved R/W* MRME 20:19 18:17 RO Reserved R/W* RAP Infineon-ADMtek Description Initial value Not Applicable 0 Memory Write and Invalidate Enable. 0 1: enable WLAN to generate memory write invalidate command. WLAN will generate this command while writing full cache lines. 0: disable WLAN to generate memory write invalidate command and use memory write commands instead. Memory Read Line Enable. 0 1: enable WLAN to generate memory read line command, while read access instruction reach the cache line boundary. If the read access instruction doesn't reach the cache line boundary then WLAN uses the memory read command instead. Not Applicable 0 Memory Read Multiple Enable. 0 1: enable WLAN to generate memory read multiple command while reading full cache line. If the memory is not cache aligned, the WLAN uses memory read command instead. Not Applicable 0 Receive auto-polling in receive suspended state. 00 00: disable auto-polling (default) 01: polling own-bit every 200 us 3-9 ADM8211C Bits Electrical Specification Type Name 16 15:14 RO Reserved R/W* CAL 13:8 R/W* PBL 7 R/W* BLE 6:2 R/W* DSL 1 R/W* BAR 0 R/W* SWR Description Initial value 10: polling own-bit every 800 us 11: polling own-bit every 1600 us Not Applicable 0 Cache alignment, address boundary for data burst, set after reset 00 00: = PBL 01: min ( 8 DW , PBL) 10: min (16 DW, PBL) 11: min (32 DW , PBL) Programmable Burst Length. This value defines the maximum 001000 number of DW to be transferred in one DMA transaction. Value: 0 (unlimited), 1, 2, 4, 8(default), 16, 32 DW Big or Little Endian selection. 0 0: little endian (e.g. INTEL, 3-2-1-0) 1: big endian (only for data buffer, 0-1-2-3) Descriptor Skip Length. Defines the gap between two descriptions in 0 the units of DW. Bus arbitration 0 0: receive higher priority 1: transmit higher priority Software reset 0 1: reset all internal hardware, except configuration registers. This signal will be cleared by WLAN itself after it completed the reset process. 3.2.2 FRCTL, CSR0A offset= 04h Note: FRCTL: Frame Control register Bits 31 30:29 28 Type Name R/W PWRMGT R/W Ver R/W Order 27 R/W MAXPSP 26 R/W DRVPRSP 25 R/W DRVBCON 24 R/W DrvLinkCtrl 23 R/W DrvLinkOn 22 R/W CTX_DATA Infineon-ADMtek Description Power Management. Set this bit to enable MAC to enter PS mode, Fast_PSP mode. If clear, MAC will always on, CAM power mode.. Protocal ver Order bit. Used when frame generated by ADM8211C. To power down the MAC and RF front end chip into max power saving, except PCI, CSR and CR. This bit is logically Ored with power down function. The deault mode is enable after reset. 1: enable 0: disable Probe response handling. 1: Driver handle probe response 0: ASIC handle probe response 1: Driver handle beacon frame 0: ASIC handle beacon frame 1: Driver control Link led 0: ASIC control Link led 1: Driver turn Link led on 0: Driver turn Link led off 0: fixed by CSR28 1: random Initial value 0 00 0 1 0 0 0 0 0 3-10 ADM8211C Electrical Specification Bits 21 Type Name R/W RSVFRM 20 19 Reserved W1C CFEND 18 RW 17 16 15:0 DozeFrm RO PSAWAKE RO PSMODE R/W AID Description 0: disable 0: enable receiving of reserved frame type. Not Applicable CF_END, write 1 clear. Set this bit, MAC will send CF_END frame. Packet TXed before sleep 0: Null Pkt 1: zero length data Pkt 1: MAC AWAKE during PS MODE, indicate MAC status to host 1: MAC PS MODE, indicates MAC status to host STA Association ID assigned by AP [15:14]=11 [13:0] = 1-2007, ID assigned by an AP during association. For TIM decoding. Initial value 0 0 0 0 0 0000 3.2.3 TDR, CSR1 offset = 08h Note: TDR: Transmit demand register W* = Before writing, the transmit process should be in the suspended state. Bits 31:0 Type Name W* TPDM Description Transmit poll demand When written any value in suspended state, trigger read-txdescriptor process and check the own-bit, if own-bit = 1, then start transmit process Initial value ffffffffh 3.2.4 WTDP, CSR1A offset=0ch Note: WTDP: The current working transmit descriptor pointer Bits 31:0 Type Name RO WTDP Description The current working transmit descriptor pointer for driver's doublechecking or other special purpose. Initial value XXXX 3.2.5 RDR, CSR2 offset =10h Note: RDR: Receive demand register W* = Before writing, the receive process should be in the suspended state. Bits 31:0 Type Name W* RPDM Infineon-ADMtek Description Initial value Receive poll demand ffffffffh When written any value in suspended state, trigger the read-rxdescriptor process and check own-bit, if own-bit = 1, then start move data to buffer from FIFO, if data available 3-11 ADM8211C Electrical Specification 3.2.6 WRDP, CSR2A offset =14h Note: WRDP: The current working receive descriptor pointer Bits 31:0 Type Name RO WRDP Description The current working receive descriptor pointer for driver's doublechecking or other special purpose. Initial value XXXX 3.2.7 RDB, CSR3 offset =18h Note: RDB: Receive descriptor base address R/W* = before writing, the receive process should be stopped. Bits 31:2 1:0 Type Name R/W* SAR RO RBND Description Start address of receive descriptor Must be 00, DW boundary Initial value xxxxxxx 00 3.2.8 TDBH, CSR3A offset =1Ch Note: TDBH: Transmit descriptor base address, High Priority R/W* = before writing, the receive process should be stopped Bits 31:2 1:0 Type Name R/W* SAT RO RBND Description Start address of descriptor Must be 00, DW boundary Initial value xxxxxxx 00 3.2.9 TDBD, CSR4 offset =20h Note: TDBD: Transmit descriptor base address, DCF R/W* = before writing, the receive process should be stopped Bits 31:2 1:0 Type Name R/W* SAT RO TBND Description Start address of transmit descriptor Must be 00, DW boundary Initial value xxxxxxx 00 3.2.10 TDBP, CSR4A offset =24h Note: TDBP: Transmit descriptor base address, PCF R/W* = before writing, the receive process should be stopped Bits 31:2 1:0 Type Name R/W* SAT RO TBND Description Start address of transmit descriptor Must be 00, DW boundary Initial value xxxxxxx 00 3.2.11 STSR, CSR5 offset =28h Note: STSR: Status register W1C = High Latching and cleared by writing 1. Bits Type Name 31 RO/W1 PCF C 30 RO/W1 BCNTC C Infineon-ADMtek Description STA enters into or leave from PCF period, ref CSR37.30 see if CFP or CP. BEACON Frame Transmit completed, Adhoc Initial value 0 0 3-12 ADM8211C Electrical Specification Bits Type Name 29 RO/W1 GPINT C 28 RO/W1 LinkOff C 27 RO/W1 ATIMTC C 26 RO/W1 TSFTF C 25 RO/W1 TSCZ C 24 RO/W1 LinkOn C 23 RO/W1 SQL C 22 RO/W1 WEPTD C 21 RO/W1 ATIME C 20 RO/W1 TBTT C 19 RO/W1 TKIPSCE C 18:17 RO Reserved 16 RO//W NISS 1C 15 RO//W AISS 1C 14 RO/W1 TEIS C 13 RO/W1 FBE C 12 RO/W1 REIS C 11 RO/W1 GPTT C 10:9 Reserved 8 RO/W1 RPS C 7 RO/W1 RDU C Infineon-ADMtek Description GPIO Interrupt Initial value 0 Beacon Lost count equal to CSR10.BLN, set this bit 0 ATIM Frame Transmit completed. Set TX status, either ok or fail, to CSR37. Adhoc. TSFT out of range, lost TBTT during 2 beacon interval. 0 0 TSC down count value zero. For key table dynamic switch 0 Matched Beacon reception. (SSID, BSSID) 0 Signal Quality Level (from Marvel status reg) WEP table switch done. For key table dynamic switch ATIM window end. 0 0 TBTT happened 0 One of entry in TKIPSC expired. See CSR7A for pending bit 0 Not Applicable Normal Interrupt Status Summary. It's set if any of below bits of CSR5 asserted. Bit 31,30, 27,24,14,12,6,2,0 Abnormal Interrupt Status Summary. It's set if any of below bits of CSR5 asserted. Bit 29,28,26,25,23,22,13,11,8,7,5,4,3,1 Transmit Early Interrupt status Transmit early interrupt status is set to 1 when Transmit early interrupt function is enabled and the transmitted packet is moved completed from descriptors to TX-FIFO buffer. This bit is cleared by writing 1. Fatal Bus Error. 1: while any of either parity error, master abort, or target abort is occurring. WLAN will disable all bus access. The way to recover parity error is by setting a software reset. Receive Early Interrupt Status. Receive early interrupt status is set to 1 when Receive early interrupt function is enabled and the received packet is filled with it's first receive descriptor. This bit is cleared by writing a 1. General Purpose Timer Time-out, base on CSR11 0 0 0 Not Applicable Receive Process Stopped, receive state = stop 0 Receive Descriptor Unavailable 1: while the next receive descriptor can't be applied by WLAN. The receive process is suspended in this situation. To restart the receive process, the ownership bit of next receive descriptor should be set to WLAN and a receive poll demand command should be issued(or a new recognized frame is received, if the receive poll demand is not issued). 0 0 0 0 0 0 3-13 ADM8211C Electrical Specification Bits Type Name 6 RO/W1 RCI C 5 RO/W1 TUF C 4 3 2 1 0 RO/W1 TRT C RO/W1 TLT C RO/W1 TDU C RO/W1 TPS C RO/W1 TCI C Description Receive Completed Interrupt 1: while a frame reception is completed. Transmit Under-Flow 1: while the transmit FIFO had an under-flow condition happening during transmission. Transmit Retry Count Expired, report TRT error on TDES0. Initial value 0 0 0 Transmit Life Time Out, report TLT error on TDES0 0 Transmit Descriptor Unavailable 1: while the next transmit descriptor can't be applied by WLAN. The transmission process is suspended in this situation. To restart the transmission process, the ownership bit of next transmit descriptor should be set to WLAN and then a transmit poll demand command should be issued. Transmit Process Stopped. 1: while transmit state = stop Transmit Completed Interrupt. 1: means a frame transmission is completed while bit 31 of TDES1 is asserted in the LAST transmit descriptor of the frame. 0 0 0 3.2.12 TDBB, CSR5A offset =2Ch Note: TDBB: Transmit descriptor base address, Buffered mc/bc packet R/W* = Before writing, the transmit process should be stopped. Bits 31:2 1:0 Type Name R/W* SAT RO TBND Description Start address of descriptor Must be 00, DW boundary Initial value xxxxxx 00 3.2.13 NAR, CSR6 offset = 30h Note: NAR: Network Access register W* = only write when the transmit processor stops. W** = only write when the transmit and receive processor both stops. W*** = only write when the receive processor stops. Bits 31 Type Name R/W TXCF 30 R/W HF 29 R/W UTR 28 R/W SQ 27 R/W1C CFP 26 R/W APSTA 25 R/W TDBBE Infineon-ADMtek Description TX condition after pkt1 fail 0: Go to pkt2 as normal case 1: Hold, stop TX, to wait Host. Fetching continue, Host Flush TX FIFO Packet, at TP STOP. Write 1 to this bit, click once. Self clear. 0: Use retry count from MSDU Header 1: Use retry count from CSR28 0: Disable TDBP 1: Enable TDBP 1: Tell TMAC that host have TX data in the next CFP. ADM8211C will set "more data" bit at 1st CF-Poll 0: STA mode 1: AP mode 0: disable TDBB 1: enable TDBB Initial value 0 0 0 0 0 0 0 3-14 ADM8211C Bits 24 23 22 21 20:16 15:14 13 Electrical Specification Type Name R/W TDBHE W1C TDBHT Reserved R/W* Reserved RO Reserved R/W* Reserved R/W ST 12 RO Reserved 11:10 R/W** OM 9:8 7 RO Reserved R/W*** MM 6 R/W*** PR 5 R/W** EA 4 R/W** DISPCF 3 R/W*** PB 2 1 R/W STPDMA R/W SR 0 R/W CTX Infineon-ADMtek Description Initial value 0: disable TDBH 0 1: enable TDBH Write one to trigger TDBH polling once 0 Not Applicable Not Applicable 0 Not Applicable 0 Not Applicable 00 Stop transmit 0 0: stop (default) 1: start Not Applicable 0 Operating Mode 00 00: normal 01: MAC loop-back 10 : BBP loop back 11: reserved Not Applicable 0 Multicast Mode 0 1: receive all multicast packets Promiscuous Mode 0 1: receive any good packet, including control frame, plus FCS, WEP disabled. 0: receive only the right destination address packets, w/o FCS. Enable uni-cast/multicast packet received, if BSSID, matched, at Ad 1 hoc mode. (asic as a bc matched happened) 1: The chip does not support PCF 0 0: The chip supports PCF Pass Bad packet 0 1: receives any packets, if pass address filter, including CRC error, WEP ICV error, RX time out, alignment error. For receiving all bad packets, the PR bit should be set to 1. 0: filters all bad packets Stop DMA operation, current pkt will be aborted 0 Start/Stop Receive 0 0: receive processor will enter stop state after the current reception frame completed. This value is effective only when the receive processor is in the running or suspending state. Notice: In "Stop Receive" state, the PAUSE packet and Remote Wake Up packet won't be affected and can be received if the corresponding function is enabled. 1: receive processor will enter running state. Continuous TX mode, either using data pattern at CSR22 or random 0 data by CSR0A[22], for production test. 0: disable 1: enable 3-15 ADM8211C Electrical Specification 3.2.14 IER, CSR7 offset = 38h Note: IER: Interrupt Enable Register Bits 31 Type Name R/W PCFIE 30 R/W BCNTCIE 29 R/W GPIE 28 R/W LinkOffIE 27 R/W ATIMTCIE 26 R/W TSFTFIE 25 R/W TSCZE 24 R/W LinkOnIE 23 R/W SQLIE 22 R/W WEPIE 21 R/W ATIMEIE 20 R/W TBTTIE 19 R/W TKIPSCIE 18:17 16 RO Reserved R/W NIE 15 R/W AIE 14 R/W TEIE 13 R/W FBEIE 12 R/W REIE 11 R/W GPTIE 10:9 8 RO Reserved R/W RSIE 7 R/W RUIE 6 R/W RCIE 5 R/W TUIE Infineon-ADMtek Description Initial value STA enters into PCF period interrupt enable 0 1: combine this bit and NIE to enable interrupt STA Beacon transmit completed interrupt enable 0 1: combine this bit and NIE to enable interrupt GPIO interrupt enable 0 1: combine this bit and AIE to enable interrupt Beacon Lost interrupt enable 0 1: combine this bit and AIE to enable interrupt ATIM Frame Transmit completed interrupt enable 0 1: combine this bit and NIE to enable interrupt TSFT out of range interrupt enable 0 1: combine this bit and AIE to enable interrupt TSC count down zero interrupt enable 0 1: combine this bit and AIE to enable interrupt Matched Beacon reception interrupt enable 0 1: combine this bit and NIE to enable interrupt Signal Quality Level 0 1: combine this bit and AIE to enable interrupt WEP Table Switch done enable 0 1: combine this bit and AIE to enable interrupt ATIM Window end enable 0 1: combine this bit and NIE to enable interrupt TBTT enable 0 1: combine this bit and NIE to enable interrupt TKIPSC enable 0 1: combine this bit and NIE to enable interrupt Not Applicable 0 Normal Interrupt Enable 0 1: enable all the normal interrupt bits( see bit16 of CSR5) Abnormal Interrupt Enable 0 1: enable all the abnormal interrupt bits(see bit 15 of CSR5) Transmit Early Interrupt Enable 0 1: combine this bit and NIE to enable interrupt. Fatal Bus Error Interrupt Enable 0 1: combine this bit and bit AIE to enable fatal bus error interrupt Receive Early Interrupt Enable 0 1: combine this bit and NIE to enable interrupt. General Purpose Timer Interrupt Enable 0 1: combine this bit and bit AIE to enable general purpose timer expired interrupt. Not Applicable 0 Receive Stopped Interrupt Enable 0 1: combine this bit and bit AIE to enable receive stopped interrupt. Receive Descriptor Unavailable Interrupt Enable 0 1: combine this bit and AIE to enable receive descriptor unavailable interrupt. Receive Completed Interrupt Enable 0 1: combine this bit and bit NIE to enable receive completed interrupt. Transmit Under-flow Interrupt Enable 0 1: combine this bit and AIE to enable transmit under-flow interrupt. 3-16 ADM8211C Electrical Specification Bits 4 Type Name R/W TRTIE 3 R/W TLTTIE 2 R/W TDUIE 1 R/W TPSIE 0 R/W TCIE Description Transmit Retry Count Expired Interrupt enable 1: combine this bit and AIE to enable transmit under-flow interrupt. Transmit Life Time Out Interrupt Enable 1: combine this bit and bit AIE to enable transmit life time out interrupt. Transmit Descriptor Unavailable Interrupt Enable 1: combine this bit and bit NIE to enable transmit descriptor unavailable interrupt. Transmit Processor Stopped Interrupt Enable 1: combine this bit and AIE to enable transmit processor stop interrupt. Transmit Completed Interrupt Enable 1: combine this bit and NIE to enable transmit completed interrupt. Initial value 0 0 0 0 0 3.2.15 TKIPSCEP, CSR7A offset = 3Ch Note: TKIPSCEP: TKIPSC counter expired status pending bit. Bits 31:0 Type Name W1C Description TKIPSC counter expired status pending bit. For 32 entries in WEP key table. Initial value 0000 3.2.16 LPC, CSR8 offset = 40h Note: LPC - Lost packet counter Bits Type Name 31:17 RO Reserved 16 RO/LH LPCO 15:0 RC LPC Description Not Applicable Lost Packet Counter Overflow 1: while lost packet counter overflowed. Cleared after read Lost Packet Counter Increment the counter while packet discarded since there was no host receive descriptors available. Cleared after read Initial value Ffff 0 0 3.2.17 CSR_TEST1, CSR8A offset = 44h Note: CSR_TEST1: Test register 1, write to dxfer_control, read from dxfer_state Bits 31 Type Name Control 30:28 27:25 R/W R/W TXWP 24:6 5:4 Reserved R/W Test mode 3:0 R/W Dump Infineon-ADMtek Description 0: read from dxfer_control 1: read from dxfer_state Control of read data, debug only Index to select read of current TX pointer : 000: TDBD 001: TDBH 010: TDBB 011: TDBP Not Applicable 00: Whole chip, normal operation 01: MAC only mode 10: Whole chip, normal operation 11: Whole chip, monitor mode Select dump signal from dxfer Initial value 0 000 00 0000 3-17 ADM8211C Electrical Specification 3.2.18 SPR, CSR9 offset = 48h Note: SPR: Serial port register Bits 31:12 11 10:4 3 Type RO R/W RO RO Name Reserved SRS Reserved SDO 2 R/W SDI 1 R/W SCLK 0 R/W SCS Description Not Applicable Serial EEPROM Select Not Applicable Serial EEPROM data out This bit serially shifts data from the EEPROM to the WLAN. Serial EEPROM data in This bit serially shifts data from the WLAN to the EEPROM. Serial EEPROM clock High/Low this bit to provide the clock signal for EEPROM. Serial EEPROM chip select 1: selects the serial EEPROM chip. Initial value F 0 F 0 0 0 0 3.2.19 CSR_TEST0, CSR9A offset = 4Ch Note: CSR_TEST0: TEST Register 0 Bits 31:29 Type Name RO BET[2:0] 28:26 RO TS [2:0] 25:23 RO RS[2:0] 22 21 20 19 18 17 RO RO RO RO RO RO ClkSave[1] ClkSave[0] EPABRT EPNE EPSNM Infineon-ADMtek Description Bus Error Type. This field is valid only when bit FBE of this reg is set. There is no interrupt generated by this field. 000: parity error, 001: master abort, 010: target abort 011, 1xx: reserved Transmit State. Report the current transmission state only, no interrupt will be generated. 000: stop 001: read descriptor 010: transmitting 011: FIFO fill 100:suspend 101:descriptor write 110: last descriptor write 111: is fifo full Receive State. Report current receive state only, no interrupt will be generated. 000: stop 001: read descriptor 010: check this packet and pre-fetch next descriptor 011: wait for receiving data 100: suspended 101: write descriptor 110: flush the current FIFO 111: FIFO drain, move data from receiving FIFO into memory PCI Clock Save state 1 or 0 Enable clock save state 1: H/W force Bypass EEPROM boot 1: EEPROM not detected 1: EEPROM signature not matched Initial value 000 000 000 0 EEPROM EEPROM X X X 3-18 ADM8211C Electrical Specification Bits 16 Type Name RO EPTYP 15 14 13 12 11 10 9 8:7 6:3 2:0 R/W R/W R/W R/W R/W R/W R/W R/W Description EEPROM type 1: 93C66, 0: 93C46 EEPROM Recall, write 1 recall EPRLD Cdisreq Cengnt CdisREQenz CkeepCAL Conlyrdw Blckallen Delay all target processes Dlytrdyocnt Delay PCI cycle count for trdy assertion. Testdxfer R/W Chipmode 0: Normal 1: dxfer dump 2: mac dump 3: ---4. tfifo test 5: rfifo test Initial value X 0 0 0 0 0 0 0 10 0 0 3.2.20 WCSR, CSR10 offset = 50h Note: WCSR: Wake-up Control/Status Register R/W1C*, Read only and Write one cleared. Bit 6~0 is cleared by write 1 or power on reset. Will set CR49.PMES. Bits 31 30 Type Name Reserved R/W CRCT 29 28:21 Reserved R/W BLN 20 R/W TSFTWE 19 R/W TIMWE 18 R/W ATIMWE 17 R/W KEYWE 16:11 10 9 8 Reserved Reserved R/W MPRE R/W LSOE Infineon-ADMtek Description Initial value Not Applicable CRC-16 Type 0 0: Initial contents = 0000h 1: Initial contents = FFFFh Not Applicable Define Link Off Status in number of lost beacon reception. 255 0 ~ 255 Wake up enable for TSFT out of range. 0 The WLAN will include this event into wake-up events. If this bit is set, WLAN will assert PMES bit of PMR1 after WLAN has detected TSFT out range. "TIM" event into wake-up events. 0 If this bit is set, WLAN will assert PMES bit of PMR1 after WLAN has detected my AID in TIM field of Beacon Frame. "ATIM" event into wake-up events. 0 If this bit is set, WLAN will assert PMES bit of PMR1 after WLAN has received a my ATIM frame. Key Update Event Wakeup enable. 0 The WLAN will include the this event into wake-up events. If this bit is set, WLAN will assert PMES bit of PMR1 after Key Update Event.. Not Applicable 00001 Not Applicable Magic Packet Received Enable. 0 The WLAN will include the "Magic Packet Received" event into wake-up events. If this bit is set, WLAN will assert PMES bit of PMR1 after WLAN has received a Magic packet. Link Status Off Enable. 0 3-19 ADM8211C Bits 7 6 5 4 3 2 1 0 Electrical Specification Type Name R/W1C * R/W1C * R/W1C * R/W1C * Reserved KEYUP Description The WLAN will include the "Link Status Off" event into wake-up events. If this bit is set, WLAN will assert PMES bit of PMR1 after WLAN has detected a link status off event. Not Applicable 1:Event of Key Update TSFTW 1:TSFT out of range event 0 TIMW 1:Received a Beacon frame with my AID set in TIM field 0 ATIMW 1:ATIM Frame Received. 0 Not Applicable 1:Magic Packet Received 0 1:Link Status Off 0 Reserved R/W1C MPR * R/W1C LSO * Initial value 0 3.2.21 SRAM BIST , CSR10A offset = 54h Bits 31 30 29 28 27 26 25 24:0 Type R/W RO RO RO RO RO RO RO Name Enable Done TFIFO RFIFO WEPTable WEPBuffer TKIPSC Reserved Description 1= enable 1=done 1=fail 1=fail 1=fail 1=fail 1=fail Not Applicable Initial value 0 0 0 0 0 0 0 0 3.2.22 GPTMR, CSR11 offset = 58h Note: GPTMR: General-purpose Timer Bits 31:17 16 Type Name Reserved R/W COM 15:0 R/W GTV Infineon-ADMtek Description Not Applicable Continuous Operation Mode 1: sets the general-purpose timer in continuous operating mode. General-purpose Timer Value Sets the counter value. This is a count-down counter with the cycle time of 204us. Initial value 0 0 3-20 ADM8211C Electrical Specification 3.2.23 GRIO, CSR11A offset = 5Ch Note: GPIO-GPIO configuration and control register Bits 31:26 25:24 23:22 21:20 19:18 17:12 11:6 5:0 Type Name Description RO Reserved Not Applicable R/W GpioEC1[1:0] GPIO Event Configuration for GPIO1: 00: rising edge 01: falling edge 10: toggle 11:disable R/W GpioEC0[1:0] GPIO Event Configuration for GPIO0: 00: rising edge 01: falling edge 10: toggle 11:disable RC Gpioilat[1:0] GPIO[1:0] pin latched input, set if Event defined in GpioEC Captured. Read cleared. R/W GpintEn[1:0] Gpio[1:0] input interrupt enable. If GPIE.CSR7 set, generate interrupt if event happened once R/W GpioEn[5:0] Gpio[5:0] output enable, active high R/W GpioO[5:0] Gpio[5:0] output value RO GpioI[5:0] Gpio[5:0] pin static input Initial value f 00 00 0 0 0 0 0 3.2.24 BBPCTL, CSR12 offset = 60h Note: BBPCTL: BBP Control port Bits 31 Type Name R/W MMISEL 30:24 R/W 23 R/W 22 R/W 21 R/W 20:18 R/W Description 0: Intersil 4 wire interface 1: Intersil 3 wire interface SPICADD SPI Chip Address For RF3000 only, Driver needs to restore this field to BBP's chip address after programming other device. MAC will use this field as BBP's chip address. TXCE MDI Data 0: positive edge to drive data out 1: negative edge to drive data out RXCE MDI Data 0: positive edge to latch data in 1: negative edge to latch data in CCAP CCA Polarity, 0: High Busy(intersil), 1: Low Busy(RFMD) BBPtype[2:0] 101 = ADMtek 17 16 15:8 7:0 R/W R/W R/W R/W Wr Rd Add[7:0] Data[7:0] Infineon-ADMtek Host set Wr(Rd) to start. ASIC reset to indicate done Host set Rd to start. ASIC reset to indicate done BBP reg Address Port BBP Data Port Initial value 0 0100000 0 0 0 000 EEPROM 0 0 0 0 3-21 ADM8211C Electrical Specification 3.2.25 SYNCTL, CSR12A offset = 64h Note: SYNCTL: SYNTHESIZER Control port See CSR15A for related information Bits 31 30 29 28 27 Name Wr Rd CS0 Reserved R/W1C CAL * 26 R/W SELCAL 25 R/W MMICE 24:22 Type R/W R/W R/W RW RFtype[2:0] Description Host set Wr to start. ASIC reset to indicate done Host set Rd to start. ASIC reset to indicate done Chip sel 0 Not Applicable 1: Generate CAL pulse for RF. Write one to generate CAL pulse once after the end of packet receiving. RF CAL control source 0: CAL bit. 1: MAC control. MMI read data clock edge 0: 8211B use MMICLK negative edge to latch data in 1: 8211B use MMICLK positive edge to latch data in 001=RFMD, 011=Maxim, 100=Philips, 111=General Initial value 0 0 0 0 0 0 000 EEPROM For RFtype[2:0] 111 Bits 21:20 19:0 Type Name R/W Data[21:20] R/W Data[19:0] Description Data for RFMD only Data for Intersil, RFMD Initial value 0 0 For RFtype[2:0] = 111 Bits 21:17 16 Type Name RO Reserved R/W SYNCE 15:13 12:8 7:6 5:0 RO R/W RO R/W Reserved AddrLen Reserved TotalLen Description Not Applicable Synthesizer read data clock edge 0: 8211B use SYNCLK negative edge to latch data in 1: 8211B use SYNCLK positive edge to latch data in Not Applicable (RW_mode + Addr) bit length Not Applicable (RW_mode + Addr + Data) bit length Initial value 0 0 0 0 0 0 3.2.26 PLCPHD, CSR13 offset = 68h Note: PLCPHD: PLCP Header * ACK, RTS, CTS, PROBE RSP, Beacon, ATIM, Null(Doze FRM) Others frame from TX MSDU header. * @Marvel's BBP, the service field will be content of reg "TX control 5", 8200. * @RFMD's BBP, the service field will be content of reg "0x11 TX variable gain and TX length field extension ", RF3000. * Asic will use SPI Burst at SPI, but driver's operation is one byte. Bits 31:24 Type Name R/W Signal 23:16 15 R/W Service R/W PMBL Infineon-ADMtek Description Signal field in PLCP header when this mac transmit beacon and atim frame. Only for Beacon, ATIM and RTS. Service field in PLCP Header Preamble, 0: Long, 1:Short Initial value 0 0 0 3-22 ADM8211C Bits 14:8 7:0 Electrical Specification Type Name Reserved R/W MMIWA4 Description Not Applicable MMI write sequence address 4, ALC control, 8b Initial value 0 3.2.27 MMIWA, CSR13A offset = 6Ch Note: MMIWA: MMI write sequence address, for tx vector For RFMD, only MMIWA1, MMIWA0 is used. Bit 7, AI, of MMIWA1 must be "1" for SPI's burst mode. Bits 31:24 23:16 15:8 7:0 Type R/W R/W R/W R/W Name MMIWA3 MMIWA2 MMIWA1 MMIWA0 Description MMI write sequence address 3, len low, 8b MMI write sequence address 2, len high, 8b MMI write sequence address 1, service, 8b MMI write sequence address 0, signal, 8b Initial value 0 0 0 0 3.2.28 MMIRD0, CSR14 offset = 70h Note: MMIRD0: MMI read sequence address, for rx vector INTERSIL 3861=0x6c6e6a68 RSSI is not return at control frame reception. Bits 31:24 23:16 15:8 7:0 Type R/O R/W R/W R/W Name Reserved MMIRA2 MMIRA1 MMIRA0 Description Not Applicable MMI read sequence address 2, power level, 8b, ALC MMI read sequence address 5, RSSI MMI read sequence address 4, status Initial value 0 0 0 0 3.2.29 MMIRD1, CSR14A offset = 74h Note: MMIRD1, MMI read sequence address 1, for rx vector Bits 31:24 23:16 Type Name R/W ID R/W RXPECNT 15 14:0 R/W PROREXT R/W PRORLEN Description 1st element ID in WEP table for Probe Response This counter is used to control the min duration in units of system clock, 22Mhz, after that the rx_pe can asserts again Probe Response length extension bit for 11M Probe Response length in us Initial value 0 0 0 0 3.2.30 TXBR, CSR15 offset = 78h Note: TXBR, transmit burst count Bits 31 Type Name W/O ALCupdate 30:21 20:16 Reserved R/W TBCNT 15:8 7:0 R/W ALC Set R/W ALC Ref Infineon-ADMtek Description 1: Enable update ALC set to BBP 0: write done clear Not Applicable Transmit Burst Count After this number of consecutive successful transmit, transmit completed interrupt will be generated. Continuously do this function if no reset. Tx Power Level control Value Reference point for measured ALC power. Unsigned fixed point 6.2 Initial value 0 0 0 0 3-23 ADM8211C Electrical Specification 3.2.31 SYNDATA, CSR15A offset = 7Ch Note: SYNDATA: Synthesizer data register For write operation, bit 31 is the first bit transmitted, and the number of bits transmitted equals CSR12A.TotalLen For read operation, bit 0 is the last bit received, and the number of bits received equals (CSR12A.TotalLen - CSR12A.AddrLen) Bits 31:0 Type Name R/W Data Description Synthesizer read/write data port Initial value 0 3.2.32 ALC Statistics, CSR16 offset = 80h Bits 31 30:28 27 26 25:16 15:0 Type Name R/W Reserved Reserved RO MCOV RO ESOV RC MCNT RC ERSUM Description Not Applicable Not Applicable MPDU count overflow Error Sum Over Flow MPDU Count, unsigned integer Power error sum, 2's complement signed integer Initial value 0 0 0 0 0 3.2.33 TOFS2, CSR17 offset = 84h Note: TOFS2: Timing Offset Parameter 2 Bits 31:28 Type Name R/W PWR1UP 27:24 23:20 19:16 15:12 11:8 7:4 3:0 R/W R/W R/W R/W R/W R/W R/W PWR0PAPE PWR1PAPE PWR0TRSW PWR1TRSW PWR0PE2 PWR1PE2 PWR0TXPE Description Initial value Delay of TX or RX from PE1, Radio, PhyRst, asserted/ de-asserted/ 0 de-asserted/ after return from power down(unit 2*ms) (0 ~ Eh) Delay of pape going low after internal data transmit end (in use) 0 Delay of pape going high after txpe asserted (in use) 0 Delay of trsw going low after internal data transmit end (in use) 0 Delay of trsw going high after txpe asserted (in use) 0 Delay of pe2 going low after internal data transmit end (in use) 0 Delay of pe2 going high after txpe asserted (in use) 0 Delay of txpe going low after internal data transmit end (in use) 0 3.2.34 CMDR, CSR18 offset = 88h Note: CMDR: Command Register, bit31 to bit16 automatically recall from EEPROM Bits 31 30:28 27 27 26:25 24 Type Name R/W D3CS Description D3cold support , mapped to CR48<31> R/W AUXCL Aux Current @D3Cold Initial value 0 (EEPROM) 111b (EEPROM) Reserved Not Applicable R/W RF2958PSn 1: disable ; 0 : enable RF2958 PS function in WLAN sleep mode 0 TXPE=RXPE=1, also enable function of CSR33[18]. (EEPROM) Reserved Not Applicable R/W pmes_sticky 1: pmez sticky 0 0: pmez will be de-sasserted by power up after wakeup event trigger (EEPROM) Infineon-ADMtek 3-24 ADM8211C Bits 23:21 20 19 Electrical Specification Type Name Reserved R/W CRD R/W PM Description Initial value Not Applicable Clock Run(clk-run pin) disable 0 1: disables the function of clock run supports to PCI. (EEPROM) Power Management, enables the WLAN to activate the Power 0 Management abilities. When this bit is set into "0" the WLAN will set (EEPROM) the Cap_Ptr register to zero, indicating no PCI compliant power management capabilities. The value of this bit will be mapped to NC-bit 20 of CR04. 18 R/W APM In PCI Power Management mode, the Wake-up events include "Beacon(TIM)", "ATIM". APM mode , this bit is effective when CMDR.PM = 1 17 R/W MAbtRcry Master Abort Auto Recovery 16:9 8 Reserved R/W Pmepshort Not Applicable PMEP pulse length select 0:long pulse 50ms 1:short pulse 100us for test purpose D3_cold APM_mode_en for PC99 certification PMEZ can be asserted without the impact of PME_EN. Reset wake up pattern data Pointer 0: Normal 1: Reset Not Applicable Not Applicable Software interrupt. Not Applicable 7 R/W D3_APM 6 R/W RWP 4 3:2 1 0 R/W R/W R/W R/O Reserved Reserved SINT Reserved 0 from EEPROM 0 from EEPROM 0 0 0 0 01 0 0 3.2.35 PCIC, CSR19 offset = 8Ch Note: PCIC: PCI bus performance counter RO* = Read only and cleared by reading. Bits 31:16 Type Name RO* CLKCNT 15:8 7:0 R/O Reserved RO* DWCNT Description The accumulated number from the PCI clock from read request asserted to access completed. This PCI clock number is the accumulated read command cycles from last PCIC read to current PCIC read. Not Applicable The number of double words accessed by the last bus master. This double word number is accumulated from all the bus master data transactions from last PCIC read to current PCIC read. Initial value 0 FF 0 3.2.36 PMCSR, CSR20 offset = 90h Note: PMCSR: Power Management Command and Status. The same register value mapping to CR49-PMCSR Bits 31:16 Type Name Reserved Infineon-ADMtek Description Not Applicable Initial value 3-25 ADM8211C Bits 15 Electrical Specification Type Name RO PMES 14:13 RO DSCAL 12:9 RO DSEL 8 RO PME_En 7:2 1:0 RO RO Reserved PWRS Description Initial value PME_Status, This bit is set when the WLAN would normally assert 0 the PME# signal for wakeup event, this bit is independent of the state of the PME-En bit. Writing a "1" to this bit will clear it and cause the WLAN to stop asserting a PME#(if enabled). Writing a "0" has no effect. CR49 PMES is R/W1C. Data_Scale, indicates the scaling factor to be used when 10b interpreting the value of the Data register. This field is required for =0.01x, any function that implements the Data register. unit Watts Data_Select, This four bit field is used to select which data is to be 0000b reported through the Data register and Data_Scale field. This field is required for any function that implements the Data register. PME_En, "1" enables the WLAN to assert PME#. When "0" disables 0 the PME# assertion. This bit defaults to "0" if the function does not support PME# generation from D3cold. Not Applicable 000000b PowerState, This two bit field is used both to determine the current 00b power state of the WLAN and to set the WLAN into a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported, optional state to this field, the write operation must complete normally on the bus, however the data is discarded and no state change occurs. 3.2.37 PAR0, CSR21 offset = 94h Note: PAR0: physical address register 0, automatically recall from EEPROM Bits 31:24 23:16 15:8 7:0 Type R/W R/W R/W R/W Infineon-ADMtek Name PAB3 PAB2 PAB1 PAB0 Description Physical address byte 3 Physical address byte 2 Physical address byte 1 Physical address byte 0 Initial value 00 00 00 00 3-26 ADM8211C Electrical Specification 3.2.38 PAR1, CSR22 offset = 98h Note: PAR1: physical address register 1, automatically recall from EEPROM For example: physical address = 00-00-e8-11-22-33 PAR0= 11 e8 00 00 PAR1= xx xx 33 22 PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped. Bits 31:16 15:8 7:0 Type R/W R/W R/W Name CTD PAB5 PAB4 Description Continuous TX data pattern physical address byte 5 physical address byte 4 Initial value 0 00 00 3.2.39 MAR0, CSR23 offset = 9Ch Note: MAR0: multicast address register 0 Bits 31:24 23:16 15:8 7:0 Type R/W R/W R/W R/W Name MAB3 MAB2 MAB1 MAB0 Description multicast address byte 3 (hash table 31:24) multicast address byte 2 (hash table 23:16) multicast address byte 1 (hash table 15:8) multicast address byte 0 (hash table 7:0) Initial value 00 00 00 00 3.2.40 MAR1, CSR24 offset = A0h Note: MAR1, multicast address register 1 MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped(CSR5 bit19-17=000). Bits 31:24 23:16 15:8 7:0 Type R/W R/W R/W R/W Name MAB7 MAB6 MAB5 MAB4 Description multicast address byte 7 (hash table 63:56) multicast address byte 6 (hash table 55:48) multicast address byte 5 (hash table 47:40) multicast address byte 4 (hash table 39:32) Initial value 00 00 00 00 3.2.41 ATIMD A0, CSR25 offset = A4h Note: ATIMDA0, ATIM frame address register 0 Bits 31:24 23:16 15:8 7:0 Type R/W R/W R/W R/W Infineon-ADMtek Name ATIMB3 ATIMB2 ATIMB1 ATIMB0 Description ATIM frame destination address byte 3 ATIM frame destination address byte 2 ATIM frame destination address byte 1 ATIM frame destination address byte 0 Initial value 00 00 00 00 3-27 ADM8211C Electrical Specification 3.2.42 ABDA1, CSR26 offset = A8h Note: ABDA1, ATIM frame address register 1, BSSID address 1 Bits 31:24 23:16 15:8 7:0 Type R/W R/W R/W R/W Name BSSIDB5 BSSIDB4 ATIMB5 ATIMB4 Description BSSID address byte 5 BSSID address byte 4 ATIM frame destination address byte 5 ATIM frame destination address byte 4 Initial value ff ff 00 00 3.2.43 CSR27, BSSID0, BSSID address register 0 Bits 31:24 23:16 15:8 7:0 Type R/W R/W R/W R/W Name BSSIDB3 BSSIDB2 BSSIDB1 BSSIDB0 Description BSSID address byte 3 BSSID address byte 2 BSSID address byte 1 BSSID address byte 0 Initial value ff ff ff ff 3.2.44 TXLMT, CSR28 Note: TXLMT: WLAN MAX TX MSDU Life Time and retry limit Control Bits 31:16 15:8 7:0 Type R/W R/W R/W Name MTMLT BCNTSIG SRTYLIM Description Max TX MSDU Life Time, TU Beacon, probe response, ATIM frame TX data rate. Retry Limit, 0-255. This is short retry count. Initial value 512 0x0A 4 3.2.45 CSR29, MIBCNT, RTS/ACK/FCS MIB Count Bits 31:24 23:16 15:8 7:0 Type RC RC RC RC Name FFCNT AFCNT RSCNT RFCNT Description FCS Failure Count ACK Failure Count RTS Success Count RTS Failure Count Initial value 0 0 0 0 3.2.46 CSR30, BCNT, Beacon Transmission Time Note: Bit 31 and bit 15 are extension bit for 11M Bits 31 30:16 15 14:0 Type R/W R/W R/W R/W Infineon-ADMtek Name EXTEN1 BEANLEN1 EXTEN0 BEANLEN0 Description Beacon length extension bit for 11M when using TIMTab 1 Beacon length in us when using TIMTab 1 Beacon length extension bit for 11M when using TIMTab 0 Beacon length in us when using TIMTab 0 Initial value 0 0 0 0 3-28 ADM8211C Electrical Specification 3.2.47 CSR31, TSFTH, TSFT Value High Bits 31:0 Type Name R/O TSFTH Description TSFT counter high DW Value, TSFT[63:32] Initial value 0 3.2.48 CSR32, TSC, Count down value for TSFT[39:28] Bits 31:24 23:22 21:12 11:5 4 3:0 Type R/W R/O R/W R/O R/W R/W Name 1st ID Reserved Length Reserved TIMTabSel TSC Description 1st element ID for data in TIM table Not Applicable Total Length in byte for data in TIM table Not Applicable TIM table selection (0: select table 0, 1: select table 1) 0: disable. Down count value for TSFT[42:28] to generate interrupt If the corresponding bit , 1 ~ 15, as index of TSFT[42:28], bit toggle once. Initial value 0 0 0 0 0 000h 3.2.49 CSR33, SYNRF direct control Bits 31 Type Name R/W SELSYN 30 R/W SELRF 29 28 27 26 25 24 23 22 21 20 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 19 18 R/W Cal_en R/W RF2958PD 17:0 R/O LERF LEIF SYNCLK SYNDATA PE1 PE2 PA_PE TR_SW TR_SWn Radio Reserved Description Control Source of SYN control IF pin 0: MAC control 1: CSR control, see bit 29:26 as below Control Source of RF Power control IF pin 0: MAC control 1: CSR control, see bit 25:19 as below Direct control of LERF# pin, if bit 31 = 1 Direct control of LEIF# pin, if bit 31 = 1 Direct control of SYNCLK pin, if bit 31 = 1 Direct control of SYNDATA pin, if bit 31 = 1 Direct control of PE1 pin, if bit 30 = 1 Direct control of PE2 pin, if bit 30 = 1 Direct control of PA_PE pin, if bit 30 = 1 Direct control of TR_SW pin, if bit 30 = 1 Direct control of TR_SWn pin, if bit 30 = 1 Direct control of Radio pin w/o related to bit30(ADM8211A compatible) Direct control of Cal_en pin, if bit 30 = 1 0: disable. 1: directly force TXPE=RXPE=1 if CSR18[27]=0. Not Applicable Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: RF2958 RESET Mode(TXPE=1, RXPE=1): "RF2958, MCLK must stay on until entered RESET mode. The RF2958 state machine needs MCLK in order to get into the RESET state. Once RESET has been entered, MCLK is no longer needed. So you need to set MODE0 and MODE1 high first, then you can turn off MCLK, if desired. But you must turn MCLK back on before any mode change from RESET takes effect." Infineon-ADMtek 3-29 ADM8211C Electrical Specification *1. This function is enabled by CSR18[27] = 0. *2. For RF2958, CSR33[18] = "1" will let TXPE, RXPE=1, CLK44BOUT still is running, before entering into power down mode. *3. For WLAN PS, the CLK44BOUT will always run at WLAN PS mode, if CSR18[27] =0 . When CSR18[27]=0, RF2958 RESET TXPE, RXPE Awake at PS mode CSR33[18]=1 Chip power down RF2958 IDLE Sleep at PS mode RF2958 RESET > 5 cycle of 44M CLK44BOUT ON PWDN 3.2.50 CSR34, BPLI, Beacon Interval and STA Listen Interval Bits 31:16 15:0 Type Name R/W BP R/W LI Description Beacon Interval, in unit of TU the STA Listen Interval, in unit of Beacon Interval Initial value 0 0 3.2.51 CSR35, CAP0, Capability Parameter 0 Note: 1. TIM table selection is controlled by CSR32[4] 2. TIM length includes one byte for TIM ID Bits 31:24 23:16 15:11 11:8 7:5 4 3:0 Type R/W R/W R/O R/W Name TIMLEN1 TIMLEN0 Reserved CWmax Reserved R/W RCVDTIM R/W CHN Infineon-ADMtek Description TIM length in byte when using TIM table 1* TIM length in byte when using TIM table 0* Not Applicable Option for CWmax adjusting. CWmax= 5 ~ 9 Others=10 1~5: CW always equal to CWmax. Not Applicable Receive every DTIM frame when device in ps-mode Current DSS Channel(DS parameter set element) Initial value 00 00 0 0000 0 0 3-30 ADM8211C Electrical Specification 3.2.52 CSR36, CAP1, Capability Parameter 1 Bits 31:16 15:0 Type Name R/W CAPI R/W ATIMW Description Capability Information. ATIM Window, IBSS parameter set element, TU Initial value 0 0 3.2.53 CSR37, RMD, RX MAX Duration Bits 31 30 Type Name R/O ATIMST R/O CFP 29:28 27:16 R/O Reserved R/W PCNT 15:0 R/W RMRD Description ATIM Frame TX Status 0: Successful, 1: Failure CFP indicator 0:DCF , 1: PCF. Not Applicable MAC Idle time between awake state and power-save mode. (unit S) RX max reception duration in unit us, ex 18768 us, @1Mbps(2346Byte). When receiving a pkt, if > RMRD, time out abort reception. Set RDES0 status bit RTO. Initial value 0 0 0 fff ffff 3.2.54 CSR38, CFPP, CFP Parameter Bits 31:24 23:8 7:0 Type R/W R/W R/W Name CFPP CFPMD DTIMP Description Contention Free Period, unit DTIM CFP Max Duration, unit TU DTIM Period, unit Beacon Initial value 0 0 0 3.2.55 CSR39, TOFS0, Timing Offset Parameter 0 Bits 31:30 29:24 23:10 14:10 9:0 Type RO R/W RO RW R/W Infineon-ADMtek Name Reserved USCNT Reserved PIFS TUCNT Description Not Applicable number of system clocks, 22Mhz, in a period of 1us Not Applicable PIFS, Time in us TU(Time Unit) counter in unit of us, range 1 ~ 1024 Initial value 0 16H 0 00H 3ffH 3-31 ADM8211C Electrical Specification 3.2.56 CSR40, TOFS1, Timing Offset Parameter 1 Bits 31:24 Type Name R/W TSFTOFSR Description RX TSFT Offset, unit us RF+BBP Latency 23:8 R/W TBTTPRE The prediction time, (next Nth TBTT - TBTTOFS), unit TU To match TSFT[25:10]. 7:0 R/W TBTTOFS Wake up time offset before TBTT, unit TU Note: -----+--------------------+-------------o-----+-------------------+ Initial value 0 0 0 + == TBTT [o,+]==TBTTOFS 3.2.57 CSR41, IFST, IFS Timing Parameter Bits 31:28 27:23 22:15 14:9 8:0 Type RO R/W R/W R/W R/W Name Reserved SLOT SIFS DIFS EIFS Description Not Applicable SLOT Time in us SIFS Time in cycle of 22Mhz DISF Time in us EIFS Time in us Initial value 0 0 0 0 0 3.2.58 CSR42, RSPT, Response Time Register Bits 31:16 15:8 7:0 Type R/W R/W R/W Name MART MIRT TSFTOFST Description Max Response Time, us Min Response Time, us TX TSFT Offset, unit us RF+BBP Latency Note: * { TX }, SIFS, {Rsp Frm} sequence that require response. Initial value 0 0 0 ----TX------+----IFS----+--- m----M----- 3.2.59 CSR43, TSFTL, TSFT Value Low Bits 31:0 Type Name R/O TSFTL Infineon-ADMtek Description TSFT counter low DW Value, TSFT[31:0] Initial value 0 3-32 ADM8211C Electrical Specification 3.2.60 CSR44, WEPCTL, WEP Control Bits 31 30 29 28 Type R/W R/W R/O R/W 27 R/W 26 25 24 R/W R/W R/W 23 R/W 22 R/W 21 R/W 20:10 9:0 RO R/W Name WEPEnble WPA En Current Table WEPTableW R WEPTableR D TBLCMD WEPRXByp SHKEY Description Enable WEP engine 1=Enable, 0=Disable. Current Key Table in use 1: write 1: read Write 1 to start, 0: done 1= WEP RX always bypass, no table loop up 1=pass the received packet to host without de-encrypt if individual key table search fails. 0=using shared key to de-encrypt the received packet if individual key table search fails. SelWEPTabl 1: select WEPTable buffer e 0: Done SelTKIPSC 1: select TKIPSC Buffer 0: Done SelTKIPROM 1: select TKIP ROM 0: Done Reserved Not Applicable Table Add Read or write Address Initial value 0 0 0 0 0 0 0 0 0 0 0 3.2.61 CSR45, WESK, Data Entry for Share/Individual Key Bits 31:0 Type Name R/W Data Description Data Initial value 0 3.2.62 CSR46, WEPCNT, WEP Count Bits 31:28 27:23 Type Name Description RW TKIPSCTHD TKIPSC counter threshold value 0000: 2^16 0001: 2^17 0010: 2^18 .............. 1101: 2^29 1110: 2^30 1111: 2^31 RW AESSCTHD AESSC counter threshold value 00000: 2^1 Initial value 1111 1111 11000: 2^25 11001: 2^26 11010: 2^27 11011: 2^28 .............. 11111: 2^28 Infineon-ADMtek 3-33 ADM8211C Electrical Specification Bits 22 Type Name R/W AESSCINC 21 R/W AESSCEV 21:16 15:0 RO RC Reserved WIEC Description 1: SC increment 1 once 0: SC increment 2 once 0: SC count from EVEN 1: SC count from ODD Not Applicable WEP ICV error count, inc if ICV check fails Initial value 0 0 0 0 3.2.63 CSR47, Reserved Bits 31:0 Type Description Reserved, Not Applicable Initial value 3.2.64 Function Event Register (Memory base offset 100h) Bits Type 31:16 15 RLH*/ W1C Name Reserved INTR_EVEN T Description Initial value Bits [31:16] are reserved in the PCI Specification This bit os used for as the interrupt bit. It is set when the interrupt 0 source is set, regardless of the mask value. It is cleared when the OS writes 1b to this field and the interrupt source has been serviced. Writing 0b to this field has no effect. 14:5 Reserved Bits [14:5] are reserved in the PCI Specification 4 R/W1C GWAKE_EV This bit is used for general wake-up. It is set when the wake-up 0 ENT source is set, regardless of the mask value. Writing 1b to this field clears this bit and the PME Status bit in the PMCSR. Writing 0b to this field has no effect. Note that writing 1b to the PME Status bit in the PMCSR has the same effect. 3:0 Reserved Bits [3:0] are reserved in the PCI Specification 3.2.65 Function Event Mask Register (Memory base offset 104h) Bits 31:16 15 14 13:5 4 3:0 Type Name Reserved R/W INTR_EN Description Bits [31:16] are reserved in the PCI Specification The bit is the interrupt mask. When this bit equals 0b, it masks the INTA# line but has no effect on the Function Event register. The interrupt mask bit affects the INTA# masking. R/W WKUP_EN This bit is the wake-up mask. When this bit equals 0b, it masks the CSTSCHG signal but has no effect on the Function Event register. This bit is dependent on bit 4 of this register. Reserved Bits [13:5] are reserved in the PCI Specification R/W GWAKE_EN This bit is the general wake-up mask. When this bit equals 0b, it masks the wake-up events towards the CSTSCHG signal. It has no effect on the Function Event register. The WLAN can assert the CSTSCHG signal in the following configuration of masked bits: wake-up bit AND general wake-up bit, or PME Enable bit in the PMCSR register only. Reserved Bits [3:0] are reserved in the PCI Specification Infineon-ADMtek Initial value 1 0 0 3-34 ADM8211C Electrical Specification 3.2.66 Function Present State Register (Memory base offset 108h) Bits 31:16 15 14:5 4 3:0 Type Name Description Initial value Reserved Bits [31:16] are reserved in the PCI Specification RO INTR_STATU This bit is used for interrupts. It reflects the current state of the 0 S source of the interrupt regardless of the mask value. It is set when the function has a pending interrupt and cleared when the software driver acknowledges all active interrupts through the SCB Command Word. Reserved Bits [14:5] are reserved in the PCI Specification RO WAKEUP_S This bit is used for general wake-up. It reflects the current state of 0 TATUS the source of CSTSCHG. It is a logical OR result of the gated three most significant bits in the PMDR: Link Status change bit is gated by the Link Status Change Wake Enable bit in the Configuration command. The Magic Packet bit is gated by the Magic Packet Wake-up disable bit in the Configuration command. The Interesting Packet bit is gated by the programmable filter command. Reserved Bits [3:0] are reserved in the PCI Specification 3.2.67 Function Force Event Register (Memory base offset 10Ch) Bits 31:16 15 14:5 4 Type Name Reserved W INTA_FORC E W 3:0 Infineon-ADMtek Description Bits [31:16] are reserved in the PCI Specification This bit is used for interrupts. Writing 1b in this field will set the interrupt bit in the Function Event register. If the INTA# pin is not masked, then it will also be activate. Writing 0b has no effect. Reserved Bits [14:5] are reserved in the PCI Specification GWAKE_FO This bit is used for general wake-up. Writing 1b in this field will set RCE the CSTSCHG bit in the Function Event register. If the CSTSCHG pin is not masked, then it will also be activated. Writing 0b has no effect. Reserved Bits [3:0] are reserved in the PCI Specification Initial value 0 0 3-35 ADM8211C Electrical Specification Chapter 4 Electrical Specification 4.1 Absolute Maximum Ratings Supply Voltage (VDD) DC Input Voltage (VIN) DC Output Voltage (VOUT) Storage Temperature Ambient Temperature ESD Rating 4.2 Operating Condition Symbol VDD Idd Parameter Supply Voltage Supply Current 4.3 DC Specifications 4.3.1 Interface DC specification Symbol Vih Vil Iih Voh Vol Vcrs 4.3.2 -0.3 V to 3.6 V -0.5 V to VDD+0.5V -0.5 V to VDD+0.5V -65 C to 150 C 0 C to 70 C 2000V Parameter Input High Voltage Input Low Voltage Differential Input Sensitivity Output High Voltage Output Low Voltage Output Signal Crossover Voltage Condition Min 3.0 Condition Min 2.0 Max 3.6 150 Units V mA Max 0.8 0.1 0.0 2.8 0.8 0.3 3.6 2.5 Units V V V V V V EEPROM Interface DC specification Standard Vcc (4.5V to 5.5V) DC Specification Symbol Vih Vil Iih Iil Voh Vol Cin Parameter Input High Voltage Input Low Voltage Input High Leakage Current Input High Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance Condition 0<Vin < Vcc 0<Vin < Vcc IoH = -10 A IoL = 10 A Min 2.0 -0.1 Max Vcc +1 0.8 1 -1 Vcc -0.2 0.2 5 Units V V A A V V pF 4.3.3 GPIO Interface DC Specification Symbol Vih Vil Iih Infineon-ADMtek Parameter Condition Input High Voltage Input Low Voltage Input High Leakage Current 0<Vin < Vcc Min 2.0 Max 0.8 10 Units V V A 4-1 ADM8211C Electrical Specification Symbol Iil Voh Vol Parameter Input High Leakage Current Output High Voltage Output Low Voltage Condition 0<Vin < Vcc IoH = -4 mA IoL = 4 mA Min Max -10 2.4 0.4 4.4 Timing Specifications 4.4.1 Reset Timing ADM8211C can be reset either by hardware, software. Units A V V 1. A hardware reset is accomplished by asserting the RST# pin after power up the device. All registers will be reset to default values. 2. 4.4.2 A software reset is accomplished by setting the reset bit. This software reset will reset all registers to default values. EEPROM Interface Timing Specification Symbol tEESK TEECSS TEECSH TEEDOH TEEDOP tEEDIS tEEDIH Parameter EESK Clock Frequency EECS Setup Time to EESK EECS Hold Time from EESK EEDO Hold Time from EESK EEDO Output Delay to "1" or "0" EEDI Setup Time to EESK EEDI Hold Time from EESK Min 0 0.2 0 70 Max 1 2 0.4 0.4 Units MHz s ns ns s s s EECS tEECSS tEECSH tEESKS EESK tEEDIS tEEDIH EEDI tEEDOH tEEDOP EEDO tEEDOP tEEDOH Figure 4-1 EEPROM Interface Timings Infineon-ADMtek 4-2 ADM8211C Packaging Chapter 5 Packaging 4.1 128-pin Low Profile Quad Flat Package (LQFP) Dimension: 14mm*14mm*1.4mm Infineon-ADMtek 5-1