MC74HC4066ADR2G - ON Semiconductor - Datasheet.Technology

May, 2011 − Rev. 9

1Publication Order Number:

MC74HC4066A/D

MC74HC4066A

Quad Analog Switch/

Multiplexer/Demultiplexer

High−Performance Silicon−Gate CMOS

The MC74HC4066A utilizes silicon−gate CMOS technology to

achieve fast propagation delays, low ON resistances, and low

OFF−channel leakage current. This bilateral switch/

multiplexer/demultiplexer controls analog and digital voltages that

may vary across the full power−supply range (from VCC to GND).

The HC4066A is identical in pinout to the metal−gate CMOS

MC14016 and MC14066. Each device has four independent switches.

The device has been designed so the ON resistances (RON) are more

linear over input voltage than RON of metal−gate CMOS analog

switches.

The ON/OFF control inputs are compatible with standard CMOS

outputs; with pullup resistors, they are compatible with LSTTL outputs.

For analog switches with voltage−level translators, see the HC4316A.

Features

•Fast Switching and Propagation Speeds

•High ON/OFF Output Voltage Ratio

•Low Crosstalk Between Switches

•Diode Protection on All Inputs/Outputs

•Wide Power−Supply Voltage Range (VCC − GND) = 2.0 to 12.0 V

•Analog Input Voltage Range (VCC − GND) = 2.0 to 12.0 V

•Improved Linearity and Lower ON Resistance over Input Voltage

than the MC14016 or MC14066

•Low Noise

•Chip Complexity: 44 FETs or 11 Equivalent Gates

•These Devices are Pb−Free, Halogen Free and are RoHS Compliant

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See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

TSSOP−14

DT SUFFIX

CASE 948G

14

1

SOEIAJ−14

F SUFFIX

CASE 965

SOIC−14

D SUFFIX

CASE 751A

14

1

14

74HC4066A

ALYWG

HC4066AG

AWLYWW

14

1

14

HC

4066A

ALYWG

G

1

14

1

PDIP−14

N SUFFIX

CASE 646

MC74HC4066AN

AWLYYWWG

1

14

(Note: Microdot may be in either location)

MC74HC4066A

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2

LOGIC DIAGRAM

XAYA

12

A ON/OFF CONTROL 13

XBYB

43

B ON/OFF CONTROL 5

XCYC

89

C ON/OFF CONTROL 6

XDYD

11 10

D ON/OFF CONTROL 12

ANALOG

OUTPUTS/INPUTS

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD

PIN 14 = VCC

PIN 7 = GND

FUNCTION TABLE

On/Off Control State of

Input Analog Switch

LOff

HOn

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

YD

XD

VCC

XC

YC

XB

YB

YA

XA

GND

D ON/OFF CONTROL

A ON/OFF CONTROL

C ON/OFF CONTROL

B ON/OFF CONTROL

ORDERING INFORMATION

Device Package Shipping†

MC74HC4066ANG PDIP−14

(Pb−Free) 25 Units / Rail

MC74HC4066ADG SOIC−14

(Pb−Free) 55 Units / Rail

MC74HC4066ADR2G SOIC−14

(Pb−Free) 2500 / Tape & Reel

MC74HC4066ADTR2G TSSOP−14* 2500 / Tape & Reel

MC74HC4066AFELG SOEIAJ−14

(Pb−Free) 2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC74HC4066A

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 14.0

ÎÎÎ

V

ÎÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

I

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current Into or Out of Any Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic DIP†

EIAJ/SOIC Package†

TSSOP Package†

ÎÎÎÎÎÎ

750

500

450

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

°C

ÎÎÎÎ

TL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎÎÎÎ

260

ÎÎÎ

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device

reliability.

†Derating −Plastic DIP: – 10 mW/°C from 65° to 125°C

EIAJ/SOIC Package: – 7 mW/°C from 65° to 125°C

TSSOP Package: − 6.1 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎ

Min

ÎÎÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎÎ

2.0

ÎÎÎÎÎÎ

12.0

ÎÎÎ

V

ÎÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage (Referenced to GND)

ÎÎÎÎÎÎÎ

GND

ÎÎÎÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND)

ÎÎÎÎÎÎÎ

GND

ÎÎÎÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

VIO*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Static or Dynamic Voltage Across Switch

ÎÎÎÎÎÎÎ

−

ÎÎÎÎÎÎ

1.2

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎÎÎÎÎ

–55

ÎÎÎÎÎÎ

+ 125

ÎÎÎ

°C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time, ON/OFF Control

Inputs (Figure 10) VCC = 2.0 V

VCC = 3.0 V

VCC = 4.5 V

VCC = 9.0 V

VCC = 12.0 V

ÎÎÎÎÎÎÎ

0

ÎÎÎÎÎÎ

1000

600

500

400

250

ÎÎÎ

ns

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may

contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

– 55 to

25°C

ÎÎÎ

v 85°C

ÎÎÎÎ

v 125°C

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎÎ

Minimum High−Level Voltage

ON/OFF Control Inputs

ÎÎÎÎÎÎÎÎ

Ron = Per Spec

ÎÎÎÎ

2.0

3.0

4.5

9.0

12.0

ÎÎÎÎ

1.5

2.1

3.15

6.3

8.4

ÎÎÎ

1.5

2.1

3.15

6.3

8.4

ÎÎÎÎ

1.5

2.1

3.15

6.3

8.4

ÎÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Voltage

ON/OFF Control Inputs

ÎÎÎÎÎÎÎÎ

Ron = Per Spec

ÎÎÎÎ

2.0

3.0

4.5

9.0

12.0

ÎÎÎÎ

0.5

0.9

1.35

2.7

3.6

ÎÎÎ

0.5

0.9

1.35

2.7

3.6

ÎÎÎÎ

0.5

0.9

1.35

2.7

3.6

ÎÎÎ

V

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ON/OFF Control Inputs

ÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

12.0

ÎÎÎÎ

± 0.1

ÎÎÎ

± 1.0

ÎÎÎÎ

± 1.0

ÎÎÎ

A

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply Current

(per Package)

ÎÎÎÎÎÎÎÎ

Vin = VCC or GND

VIO = 0 V

ÎÎÎÎ

6.0

12.0

ÎÎÎÎ

2

4

ÎÎÎ

20

40

ÎÎÎÎ

40

160

ÎÎÎ

A

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

I/O pins must be connected to a

properly terminated line or bus.

MC74HC4066A

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4

DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

– 55 to

25°C

ÎÎÎ

v 85°C

ÎÎÎÎ

v 125°C

ÎÎÎÎ

Ron

ÎÎÎÎÎÎÎÎÎÎ

Maximum “ON” Resistance

ÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC to GND

IS v 2.0 mA (Figures 1, 2)

ÎÎÎÎ

2.0†

3.0†

4.5

9.0

12.0

ÎÎÎÎ

−

120

70

ÎÎÎ

−

160

85

ÎÎÎÎ

−

200

100

ÎÎÎ



ÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC or GND

(Endpoints)

IS v 2.0 mA (Figures 1, 2)

ÎÎÎÎ

2.0

3.0

4.5

9.0

12.0

ÎÎÎÎ

−

70

50

ÎÎÎ

−

85

60

ÎÎÎÎ

−

120

80

ÎÎÎÎ

Ron

ÎÎÎÎÎÎÎÎÎÎ

Maximum Difference in “ON”

Resistance Between Any Two

Channels in the Same Package

ÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = 1/2 (VCC − GND)

IS v 2.0 mA

ÎÎÎÎ

2.0

4.5

9.0

12.0

ÎÎÎÎ

−

20

15

ÎÎÎ

−

25

20

ÎÎÎÎ

−

30

25

ÎÎÎ



ÎÎÎÎ

Ioff

ÎÎÎÎÎÎÎÎÎÎ

Maximum Off−Channel Leakage

Current, Any One Channel

ÎÎÎÎÎÎÎÎ

Vin = VIL

VIO = VCC or GND

Switch Off (Figure 3)

ÎÎÎÎ

12.0

ÎÎÎÎ

0.1

ÎÎÎ

0.5

ÎÎÎÎ

1.0

ÎÎÎ

A

ÎÎÎÎ

Ion

ÎÎÎÎÎÎÎÎÎÎ

Maximum On−Channel Leakage

Current, Any One Channel

ÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC or GND

(Figure 4)

ÎÎÎÎ

12.0

ÎÎÎÎ

0.1

ÎÎÎ

0.5

ÎÎÎÎ

1.0

ÎÎÎ

A

†At supply voltage (VCC) approaching 3 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage

operation, it is recommended that these devices only be used to control digital signals.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

– 55 to

25°C

ÎÎÎ

v 85°C

ÎÎÎÎ

v 125°C

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Analog Input to Analog Output

(Figures 8 and 9)

ÎÎÎÎ

2.0

3.0

4.5

9.0

12.0

ÎÎÎÎ

40

30

10

ÎÎÎ

50

40

13

ÎÎÎÎ

60

50

15

ÎÎÎ

ns

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 11)

ÎÎÎÎ

2.0

3.0

4.5

9.0

12.0

ÎÎÎÎ

80

60

30

25

ÎÎÎ

90

70

38

28

ÎÎÎÎ

110

80

45

30

ÎÎÎ

ns

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 1 1)

ÎÎÎÎ

2.0

3.0

4.5

9.0

12.0

ÎÎÎÎ

80

45

25

ÎÎÎ

90

50

32

ÎÎÎÎ

100

60

37

ÎÎÎ

ns

ÎÎÎÎ

C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Capacitance ON/OFF Control Input

ÎÎÎÎ

−

ÎÎÎÎ

10

ÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Control Input = GND

Analog I/O

Feedthrough

ÎÎÎÎ

−

ÎÎÎÎ

35

1.0

ÎÎÎ

35

1.0

ÎÎÎÎ

35

1.0

CPD Power Dissipation Capacitance (Per Switch) (Figure 13)*

Typical @ 25°C, VCC = 5.0 V

pF

15

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

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5

ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

V

ÎÎÎÎ

Limit*

25°C

54/74HC

ÎÎÎ

Unit

ÎÎÎÎ

BW

ÎÎÎÎÎÎÎÎÎÎ

Maximum On−Channel Bandwidth or

Minimum Frequency Response

(Figure 5)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 MHz Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VOS

Increase fin Frequency Until dB Meter Reads – 3 dB

RL = 50 , CL = 10 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

150

160

ÎÎÎ

MHz

ÎÎÎÎ

−

ÎÎÎÎÎÎÎÎÎÎ

Off−Channel Feedthrough Isolation

(Figure 6)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin  Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 , CL = 50 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

− 50

ÎÎÎ

dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1.0 MHz, RL = 50 , CL = 10 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

− 40

ÎÎÎÎ

−

ÎÎÎÎÎÎÎÎÎÎ

Feedthrough Noise, Control to

Switch

(Figure 7)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin v 1 MHz Square Wave (tr = tf = 6 ns)

Adjust RL at Setup so that IS = 0 A

RL = 600 , CL = 50 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

60

130

200

ÎÎÎ

mVPP

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

RL = 10 k, CL = 10 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

30

65

100

ÎÎÎÎ

−

ÎÎÎÎÎÎÎÎÎÎ

Crosstalk Between Any Two

Switches

(Figure 12)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin  Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 , CL = 50 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

– 70

ÎÎÎ

dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1.0 MHz, RL = 50 , CL = 10 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

– 80

ÎÎÎÎ

THD

ÎÎÎÎÎÎÎÎÎÎ

Total Harmonic Distortion

(Figure 14)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 kHz, RL = 10 k, CL = 50 pF

THD = THDMeasured − THDSource

VIS = 4.0 VPP sine wave

VIS = 8.0 VPP sine wave

VIS = 11.0 VPP sine wave

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

0.10

0.06

0.04

ÎÎÎ

%

*Guaranteed limits not tested. Determined by design and verified by qualification.

MC74HC4066A

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6

0

50

100

150

200

250

300

350

400

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00

+25 °C

+125°C

−55°C

Figure 1a. Typical On Resistance, VCC = 2.0 V

Figure 1b. Typical On Resistance, VCC = 3.0 V

Figure 1c. Typical On Resistance, VCC = 4.5 V

Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND

RON @ 2 V

Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND

RON @ 3 V

0

20

40

60

80

100

120

140

160

180

200

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50

Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND

RON @ 4.5 V

0

20

40

60

80

100

120

140

160

180

200

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00

+25 °C

+125°C

−55°C

+25 °C

+125°C

−55°C

MC74HC4066A

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7

0

10

20

30

40

50

60

70

80

90

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00

+25 °C

+125°C

−55°C

Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND

RON @ 6 V

Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND

RON @ 9V

0

10

20

30

40

50

60

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00

Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND

RON @ 12 V

0

10

20

30

40

50

60

70

80

90

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00

+25 °C

+125°C

−55°C

Figure 1d. Typical On Resistance, VCC = 6.0 V

Figure 1e. Typical On Resistance, VCC = 9.0 V

Figure 1f. Typical On Resistance, VCC = 12.0 V

+25 °C

+125°C

−55°C

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8

Figure 2. On Resistance Test Set−Up

PLOTTER

MINI COMPUTER

PROGRAMMABLE

POWER

SUPPLY

DC ANALYZER

VCC

+-

ANALOG IN COMMON OUT

GND

DEVICE

UNDER TEST

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set−Up

OFF

7

14

VCC

A

VCC

GND

VCC

SELECTED

CONTROL

INPUT

VIL

Figure 4. Maximum On Channel Leakage Current,

Test Set−Up

ON

14

VCC

N/C

A

GND

VCC

7

SELECTED

CONTROL

INPUT

VIH

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9

Figure 5. Maximum On−Channel Bandwidth

Test Set−Up

ON

14

VCC

0.1FCL*

fin dB

METER

*Includes all probe and jig capacitance.

VOS

7

SELECTED

CONTROL

INPUT

VCC

Figure 6. Off−Channel Feedthrough Isolation,

Test Set−Up

OFF

7

14

VCC

0.1FCL*

fin dB

METER

*Includes all probe and jig capacitance.

VOS

RL

VIS

SELECTED

CONTROL

INPUT

Figure 7. Feedthrough Noise, ON/OFF Control to

Analog Out, Test Set−Up

14

VCC

CL*

*Includes all probe and jig capacitance.

OFF/ON

VCC

GND

Vin ≤1 MHz

tr = tf = 6 ns

CONTROL

VCC/2

RL

IS

RLVOS

7

SELECTED

CONTROL

INPUT

VCC/2

VCC

GND

ANALOG IN

ANALOG OUT 50%

tPLH tPHL

50%

Figure 8. Propagation Delays, Analog In to

Analog Out

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10

POSITIONWHEN TESTING tPLZ AND tPZL

Figure 9. Propagation Delay Test Set−Up

ON

14

VCC

*Includes all probe and jig capacitance.

TEST

POINT

ANALOG OUTANALOG IN

CL*

7

SELECTED

CONTROL

INPUT

VCC

trtf

VCC

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

CONTROL

ANALOG

OUT

90%

50%

10%

50%

10%

90%

tPZH tPHZ

tPZL tPLZ

Figure 10. Propagation Delay, ON/OFF Control

to Analog Out

ON/OFF

VCC

TEST

POINT

14

VCC

1 k

POSITIONWHEN TESTING tPHZ AND tPZH

CL*

1

2

1

2

Figure 11. Propagation Delay Test Set−Up

1

2

7

SELECTED

CONTROL

INPUT

Figure 12. Crosstalk Between Any Two Switches,

Test Set−Up

RL

ON

14

VCC OR GND CL*

*Includes all probe and jig capacitance.

OFF

RL

VIS

RLCL*

VOS

fin

0.1 F

VCC/2 VCC/2

7

SELECTED

CONTROL

INPUT

VCC/2

Figure 13. Power Dissipation Capacitance

Test Set−Up

14

VCC

N/C

OFF/ON

A

N/C

7

SELECTED

CONTROL

INPUT

ON/OFF CONTROL

ON

VCC

0.1 F

CL*

fin

RL

TO

DISTORTION

METER

*Includes all probe and jig capacitance.

VOS

VIS

7

SELECTED

CONTROL

INPUT

VCC

Figure 14. Total Harmonic Distortion, Test Set−Up

*Includes all probe and jig capacitance.

VCC

VCC/2

MC74HC4066A

http://onsemi.com

11

0

-10

-20

-30

-40

-50

1.0 2.0

FREQUENCY (kHz)

dBm

-60

-70

-80

-90

FUNDAMENTAL FREQUENCY

DEVICE

SOURCE

Figure 15. Plot, Harmonic Distortion

3.0

APPLICATION INFORMATION

The ON/OFF Control pins should be at VCC or GND logic

levels, VCC being recognized as logic high and GND being

recognized as a logic low. Unused analog inputs/outputs

may be left floating (not connected). However, it is

advisable to tie unused analog inputs and outputs to VCC or

GND through a low value resistor. This minimizes crosstalk

and feedthrough noise that may be picked−up by the unused

I/O pins.

The maximum analog voltage swings are determined by

the supply voltages VCC and GND. The positive peak analog

voltage should not exceed VCC. Similarly, the negative peak

analog voltage should not go below GND. In the example

below, the difference between VCC and GND is twelve volts.

Therefore, using the configuration in Figure 16, a maximum

analog signal of twelve volts peak−to−peak can be

controlled.

When voltage transients above VCC and/or below GND

are anticipated on the analog channels, external diodes (Dx)

are recommended as shown in Figure 17. These diodes

should be small signal, fast turn−on types able to absorb the

maximum anticipated current surges during clipping. An

alternate method would be to replace the Dx diodes with

Mosorbs (Mosorb™ is an acronym for high current surge

protectors). Mosorbs are fast turn−on devices ideally suited

for precise DC protection with no inherent wear out

mechanism.

ANALOG O/I

ON

14

VCC = 12 V

ANALOG I/O

+ 12 V

0 V

+ 12 V

0 V

OTHER CONTROL

INPUTS

(VCC OR GND)

ON

16

VCC

Dx

VCC

Dx

Figure 16. 12 V Application Figure 17. Transient Suppressor Application

7

SELECTED

CONTROL

INPUT

Dx

OTHER CONTROL

INPUTS

(VCC OR GND)

7

SELECTED

CONTROL

INPUT

VCC

MC74HC4066A

http://onsemi.com

12

+5 V

14

HC4066A

CONTROL

INPUTS

7

5

6

14

15

LSTTL/

NMOS

ANALOG

SIGNALS

R* R* R* R*

ANALOG

SIGNALS

HCT

BUFFER

R* = 2 TO 10 k

VDD = 5 V VCC = 5 TO 12 V

ANALOG

SIGNALS

ANALOG

SIGNALS

116 14

CONTROL

INPUTS

78

MC14504

13

3

5

7

9

11

14

2

4

6

10

5

6

14

15

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

1 OF 4

SWITCHES

COMMON I/O

1234

CONTROL INPUTS

INPUT

OUTPUT

0.01 F

LF356 OR

EQUIVALENT

a. Using Pull-Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface

Figure 19. TTL/NMOS−to−CMOS Level Converter

Analog Signal Peak−to−Peak Greater than 5 V

(Also see HC4316A)

Figure 20. 4−Input Multiplexer Figure 21. Sample/Hold Amplifier

+

-

1 OF 4

SWITCHES

+5 V

14

CONTROL

INPUTS

7

5

6

14

15

LSTTL/

NMOS

ANALOG

SIGNALS

ANALOG

SIGNALS

1 OF 4

SWITCHES

1 OF 4

SWITCHES

1 OF 4

SWITCHES

HC4066A

MC74HC4066A

http://onsemi.com

13

PACKAGE DIMENSIONS

PDIP−14

N SUFFIX

CASE 646−06

ISSUE P

17

14 8

B

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG D

K

C

SEATING

PLANE

N

−T−

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

MC74HC4066A

http://onsemi.com

14

PACKAGE DIMENSIONS

SOIC−14

D SUFFIX

CASE 751A−03

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

G

P7 PL

14 8

7

1

M

0.25 (0.010) B M

S

B

M

0.25 (0.010) A S

T

−T−

F

RX 45

SEATING

PLANE D14 PL K

C

J

M

_DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

__ __

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

7X

MC74HC4066A

http://onsemi.com

15

PACKAGE DIMENSIONS

TSSOP−14

DT SUFFIX

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V S

T

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

K

K1

ÉÉÉ

DETAIL E

F

M

−W−

0.25 (0.010)

8

14

7

1

PIN 1

IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

−V−

14X REFK

N

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

MC74HC4066A

http://onsemi.com

16

PACKAGE DIMENSIONS

SOEIAJ−14

F SUFFIX

CASE 965−01

ISSUE B

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.004 0.008

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 1.42 --- 0.056

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

D

Z

E

1

14 8

7

eA

b

VIEW P

c

L

DETAIL P

M

A

b

c

D

E

e

L

M

Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

MC74HC4066A/D

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