PowerSSO-16
Features
Max transient supply voltage VCC 40 V
Operating voltage range VCC 4 to 28 V
Typ. on-state resistance (per Ch) RON 10.5 mΩ
Current limitation (typ) ILIMH 88 A
Standby current (max) ISTBY 0.5 µA
Minimum cranking supply voltage (VCC
decreasing) VUSD_cranking 2.85 V
• AEC-Q100 qualified
• Extreme low voltage operation for deep cold cranking applications (compliant
with LV124, revision 2013)
• General
– Single channel smart high-side driver with CurrentSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS outputs
• CurrentSense diagnostic functions
– Analog feedback of load current with high precision proportional current
mirror
– Overload and short to ground (power limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
– Sense enable/disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Configurable latch-off on overtemperature or power limitation
– Loss of ground and loss of VCC
– Reverse battery with external components
– Electrostatic discharge protection
Applications
• Automotive resistive, inductive and capacitive loads
• Protected supply for ADAS systems: radars and sensors
• Automotive headlamp
Product status link
VN7E010AJ
High-side driver with CurrentSense analog feedback for automotive applications
VN7E010AJ
Datasheet
DS11954 - Rev 5 - November 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
Description
The device is a single channel high-side driver manufactured with proprietary ST
VIPower® M0-7 technology, in a PowerSSO-16 package. The device is designed to
drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible
interface, providing protection and diagnostics.
The device integrates advanced protective functions such as load current limitation,
overload active management by power limitation and overtemperature shutdown with
configurable latch-off.
A FaultRST pin unlatches the output in case of fault or disables the latch-off
functionality.
A current sense pin delivers high precision proportional load current sense in addition
to the detection of overload and short circuit to ground, short to VCC and OFF-state
open-load.
A sense enable pin allows OFF-state diagnosis to be disabled during the module low-
power mode as well as external sense resistor sharing among similar devices.
VN7E010AJ
DS11954 - Rev 5 page 2/46
1Block diagram and pin description
Figure 1. Block diagram
Control & Diagnostic
VCC
Current
Limitation
VCC –OUT
Clamp
Internal supply
OUTPUT
MUX
Current
Sense
GND
Undervoltage
shut-down
VCC –GND
Clamp
Fault
Short to VCC
Open-Load in OFF
Overtemperature
Power Limitation
T
VSENSEH
INPUT
SEn
CS
FaultRST
Gate Driver
Table 1. Pin functions
Name Function
VCC Battery connection.
OUTPUT Power output; all the pins must be connected together.
GND Ground connection; must be reverse battery protected by an external diode / resistor network.
INPUT Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs; controls output switch
state.
CS Analog current sense output pin; delivers a current proportional to the selected load current.
SEn Active high compatible with 3 V and 5 V CMOS outputs pin; enables the CS diagnostic pin.
FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault - if kept low, sets
the output to auto-restart mode.
VN7E010AJ
Block diagram and pin description
DS11954 - Rev 5 page 3/46
Figure 2. Configuration diagram (top view)
1
2
3
4
5
6
CS
FaultRST
7
8
SEn
N.C.
16
15
14
13
12
11
10
9
OUTPUT
GND
INPUT
TAB = VCC
PowerSSO-16
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
N.C.
N.C.
Note: Pins 9, 10, 11 and 12 are internally connected; Pins 13, 14, 15 and 16 are internally connected; all output pins
must be connected together on PCB.
Table 2. Suggested connections for unused and not connected pins
Connection / pin CS N.C. Output Input SEn, FaultRST
Floating Not allowed X (1) X X X
To ground Through 1 kΩ resistor X Not allowed Through 15 kΩ resistor Through 15 kΩ resistor
1. X: do not care.
VN7E010AJ
Block diagram and pin description
DS11954 - Rev 5 page 4/46
2Electrical specification
Figure 3. Current and voltage conventions
VIN
OUTPUT
CS
FaultRST
SEn
INPUT
IIN
ISEn
IFR
IGND
VSENSE
VOUT
VCC
VFn
IS
IOUT
ISENSE
VCC
VSEn
VFR
Note: VFn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
Forcing the device to operate above absolute maximum ratings may cause permanent damage.
These are stress ratings only and operation of the device at these or any other conditions outside those indicated
in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 38
V
-VCC Reverse DC supply voltage 0.3
VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 Ω) 40 V
VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V
-IGND DC reverse ground pin current 200 mA
IOUT OUTPUT DC output current Internally limited
A
-IOUT Reverse DC output current 35
IIN INPUT DC input current
-1 to 10 mA
ISEn SEn DC input current
IFR FaultRST DC input current -1 to 1.5 mA
ISENSE
CS pin DC output current (VGND = VCC and VSENSE < 0 V) 10
mA
CS pin DC output current in reverse (VCC < 0 V) -20
EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 °C) 118 mJ
VN7E010AJ
Electrical specification
DS11954 - Rev 5 page 5/46
Symbol Parameter Value Unit
VESD
Electrostatic discharge (JEDEC 22A-114F)
INPUT 4000
V
CS, SEn 2000
FaultRST 4000
OUTPUT 4000
VCC 4000
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature -40 to 150
°C
Tstg Storage temperature -55 to 150
2.2 Thermal data
Table 4. Thermal data
Symbol Parameter Typ. value Unit
Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) (1) 4.2
°C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(2) 55
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7)(1) 21.4
Rthj-top Thermal resistance junction-top (JEDEC JESD 51-7)(1) 12.1
1. Device mounted on four-layer 2s2p PCB
2. Device mounted on two-layer 2s0p PCB with 2 cm² heatsink copper trace
2.3 Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5. Electrical characteristics during cranking
Symbol Parameter Test conditions Min. Typ. Max. Unit
VUSD_Cranking
Minimum cranking supply
voltage (VCC decreasing) 2.85 V
RON On-state resistance IOUT = 1 A; VCC = 2.85 V;
VCC decreasing 31.5 mΩ
TTSD (1) Shutdown temperature (VCC
decreasing) VCC = 2.85 V 140 °C
1. Parameter guaranteed by design and characterization; not subject to production test
Table 6. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 4 13 28 V
VUSD Undervoltage shutdown 2.85 V
VUSDReset Undervoltage shutdown reset 5 V
VN7E010AJ
Thermal data
DS11954 - Rev 5 page 6/46
Symbol Parameter Test conditions Min. Typ. Max. Unit
VUSDhyst Undervoltage shutdown
hysteresis 0.3 V
RON On-state resistance
IOUT = 5 A; Tj = 25°C 10.5
mΩ
IOUT = 5 A; Tj = 150°C 22.5
IOUT = 5 A; VCC = 4 V; Tj = 25°C(1) 17
Vclamp Clamp voltage
IS = 20 mA; 25°C < Tj < 150°C 41 46 52 V
IS = 20 mA; Tj = -40°C 38 V
ISTBY
Supply current in standby at
VCC = 13 V (2)
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
Tj = 25°C
0.5
µA
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
Tj = 85°C (3)
0.5
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
Tj = 125°C
3
tD_STBY Standby mode blanking time VCC = 13 V;
VIN = 5; VSEn = VFR = 0 V; IOUT = 0 A 60 300 550 µs
IS(ON) Supply current VCC = 13 V; VSEn = VFR = 0 V;
VIN = 5 V; IOUT = 0 A 3 5 mA
IGND(ON)
Control stage current
consumption in ON state. All
channels active.
VCC = 13 V; VSEn = 5 V; VFR = 0 V;
VIN = 5 V; IOUT = 5 A 6 mA
IL(off) (2) Off-state output current at
VCC = 13 V
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C 0 0.01 0.5
µA
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C 0 3
VF
Output - VCC diode voltage at
Tj = 150°C IOUT = -5 A; Tj = 150°C 0.7 V
1. Parameter guaranteed only at VCC = 4 V and Tj = 25 °C
2. PowerMOS leakage included
3. Parameter specified by design; not subject to production test.
Table 7. Switching
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) (1) Turn-on delay time at
Tj = 25 °C
RL = 2.6 Ω
10 50 120
µs
td(off) (1) Turn-off delay time at
Tj = 25 °C 10 50 100
(dVOUT/dt)on (1) Turn-on voltage slope at
Tj = 25 °C
RL = 2.6 Ω
0.1 0.25 0.7
V/µs
(dVOUT/dt)off (1) Turn-off voltage slope at
Tj = 25 °C 0.1 0.3 0.7
WON
Switching energy losses at
turn-on (twon)RL = 2.6 Ω — 0.8 1.2 (2) mJ
VN7E010AJ
Main electrical characteristics
DS11954 - Rev 5 page 7/46
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol Parameter Test conditions Min. Typ. Max. Unit
WOFF
Switching energy losses at
turn-off (twoff)RL = 2.6 Ω — 0.7 1.1(2) mJ
tSKEW
Differential pulse skew (tPHL -
tPLH)RL = 2.6 Ω -50 0 +50 µs
1. See Figure 6. Switching time and pulse skew
2. Parameter guaranteed by design and characterization; not subject to production test.
Table 8. Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
INPUT characteristics
VIL Input low level voltage 0.9 V
IIL Low level input current VIN = 0.9 V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN = 2.1 V 10 µA
VI(hyst) Input hysteresis voltage 0.2 V
VICL Input clamp voltage
IIN = 1 mA 5.3 7.2
V
IIN = -1 mA -0.7
FaultRST characteristics
VFRL Input low level voltage 0.9 V
IFRL Low level input current VIN = 0.9 V 1 µA
VFRH Input high level voltage 2.1 V
IFRH High level input current VIN = 2.1 V 10 µA
VFR(hyst) Input hysteresis voltage 0.2 V
VFRCL Input clamp voltage
IIN = 1 mA 5.3 7.5
V
IIN = -1 mA -0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL Input low level voltage 0.9 V
ISEnL Low level input current VIN = 0.9 V 1 µA
VSEnH Input high level voltage 2.1 V
ISEnH High level input current VIN = 2.1 V 10 µA
VSEn(hyst) Input hysteresis voltage 0.2 V
VSEnCL Input clamp voltage
IIN = 1 mA 5.3 7.2
V
IIN = -1 mA -0.7
VN7E010AJ
Main electrical characteristics
DS11954 - Rev 5 page 8/46
Table 9. Protections
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
ILIMH DC short circuit current
VCC = 13 V 63 88
126
A
4 V < VCC < 18 V (1)
ILIML Short circuit current during
thermal cycling
VCC = 13 V;
TR < Tj < TTSD
29
TTSD Shutdown temperature 150 175 200
°C
TRReset temperature(1) TRS + 1 TRS + 7
TRS Thermal reset of fault
diagnostic indication VFR = 0 V; VSEn = 5 V 135
THYST
Thermal hysteresis (TTSD -
TR)(1) 7
ΔTJ_SD Dynamic temperature Tj = -40°C; VCC = 13 V 60 K
tLATCH_RST Fault reset time for output
unlatch(1)
VFR = 5 V to 0 V; VSEn = 5 V;
- E.g. Ch0
VIN = 5 V
3 10 20 µs
VDEMAG Turn-off output voltage clamp
IOUT = 2 A; L = 6 mH; Tj = -40°C VCC - 38 V
IOUT = 2 A; L = 6 mH; Tj = 25°C to
150°C VCC - 41 VCC - 46 VCC - 52 V
1. Parameter guaranteed by design and characterization; not subject to production test.
Table 10. CurrentSense
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSENSE_CL CurrentSense clamp voltage
VSEn = 0 V; ISENSE = 1 mA -17 -12
V
VSEn = 0 V; ISENSE = -1 mA 7
CurrentSense characteristics
K0IOUT/ISENSE IOUT = 0.1 A; VSENSE = 0.5 V;
VSEn = 5 V
-40% 5000 +40%
dK0/K0 (1) (2) CurrentSense ratio drift -20 20 %
K1IOUT/ISENSE IOUT = 0.25 A; VSENSE = 0.5 V;
VSEn = 5 V
-25% 5000 25%
dK1/K1 (1) (2) CurrentSense ratio drift -15 15 %
K2IOUT/ISENSE IOUT = 6 A; VSENSE = 4 V; VSEn = 5 V
-7% 5000 7%
dK2/K2 (1) (2) CurrentSense ratio drift -6 6 %
K3IOUT/ISENSE IOUT = 18 A; VSENSE = 4 V;
VSEn = 5 V
-7% 5000 7%
dK3/K3 (1) (2) CurrentSense ratio drift -6 6 %
ISENSE_OL CS current for OL detection IOUT = 0.01 A; VSENSE = 0.5 V;
VSEn = 5 V 11.5 µA
VN7E010AJ
Main electrical characteristics
DS11954 - Rev 5 page 9/46
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISENSE0 CurrentSense leakage current
CS disabled: VSEn = 0 V 0 0.5
µA
CS disabled:
-1 V < VSENSE < 5 V(1) -0.5 0.5
CS enabled: VSEn = 5 V; all channel
ON; IOUT = 0 A; diagnostic selected;
VIN = 5 V; IOUT = 0 A
0 10
CS enabled: VSEn = 5 V; channel
OFF; diagnostic selected; VIN = 0 V 0 2
VOUT_MSD (1) Output voltage for
CurrentSense shutdown
VIN = 5 V; VSEn = 5 V;
RSENSE = 2.7 kΩ; IOUT = 5 A 5 V
VSENSE_SAT CurrentSense saturation
voltage
VCC = 7 V; RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN = 5 V; IOUT = 18 A;
Tj = -40°C
4.8 V
ISENSE_SAT (1) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V;
VSEn = 5 V; Tj = 150°C 4 mA
IOUT_SAT (1) Output saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V;
VSEn = 5 V; Tj = 150°C 22 A
OFF-state diagnostic
VOL OFF-state open-load voltage
detection threshold
VIN = 0 V;
VSEn = 0 V 2 3 4 V
IL(off2) (3) OFF-state output sink current VIN = 0 V; VOUT = VOL; Tj = -40°C to
125°C -100 -15 µA
tDSTKON
OFF-state diagnostic delay
time from falling edge of
INPUT (see
Figure 8. TDSTKON )
VIN = 5 V to 0 V; VSEn = 5 V;
IOUT = 0 A;
VOUT = 4 V
100 350 700 µs
tD_OL_V
Settling time for valid OFF-
state open load diagnostic
indication from rising edge of
SEn
VIN = 0 V; VFR = 0 V; VOUT = 4 V;
VSEn = 0 V to 5 V 60 µs
tD_VOL
OFF-state diagnostic delay
time from rising edge of VOUT
VIN = 0 V;
VSEn = 5 V;
VOUT = 0 V to 4 V
5 30 µs
Fault diagnostic feedback (see Table 11. Truth table)
VSENSEH CurrentSense output voltage
in fault condition
VCC = 13 V;
VIN = 0 V; VSEn = 5 V;
IOUT = 0 A; VOUT = 4 V;
RSENSE = 1 kΩ
5 6.6 V
ISENSEH CurrentSense output current
in fault condition VCC = 13 V; VSENSE = 5 V 7 20 30 mA
CurrentSense timings (current sense mode - see Figure 7. CurrentSense timings (current sense mode))(4)
tDSENSE1H Current sense settling time
from rising edge of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 2.6 Ω 60 µs
VN7E010AJ
Main electrical characteristics
DS11954 - Rev 5 page 10/46
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
tDSENSE1L Current sense disable delay
time from falling edge of SEn
VIN = 5 V; VSEn = 5 V to 0 V;
RSENSE = 1 kΩ; RL = 2.6 Ω 5 20 µs
tDSENSE2H Current sense settling time
from rising edge of INPUT
VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 2.6 Ω 100 250 µs
ΔtDSENSE2H
Current sense settling time
from rising edge of IOUT
(dynamic response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ;
ISENSE = 90 % of ISENSEMAX;
RL = 2.6 Ω
100 µs
tDSENSE2L
Current sense turn-off delay
time from falling edge of
INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 2.6 Ω 50 250 µs
1. Parameter specified by design; not subject to production test.
2. All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
3. Parameter granted at -40 °C < Tj< 125 °C
4. Transition delay are measured up to +/- 10% of final conditions.
Figure 4. IOUT/ISENSE versus IOUT
2500
3500
4500
5500
6500
7500
0 2 4 6 8 10 12 14 16 18 20
K-factor
IOUT [A]
Max
Min
Typ
VN7E010AJ
Main electrical characteristics
DS11954 - Rev 5 page 11/46
Figure 5. Current sense accuracy versus IOUT
0
5
10
15
20
25
30
35
40
45
50
0 2 4 6 8 10 12 14 16 18 20
%
IOUT [A]
Current sense uncalibrated precision
Current sense calibrated precision
Figure 6. Switching time and pulse skew
VOUT
t
Vcc
twon
80% Vcc
20% Vcc
twoff
INPUT
td(on)
tpLH tpHL
td(off)
t
dVOUT/dt
ON OFF
dVOUT/dt
VN7E010AJ
Main electrical characteristics
DS11954 - Rev 5 page 12/46
Figure 7. CurrentSense timings (current sense mode)
IN
SEn
I
t t tt
GAPG1003141014CFT
CURRENT SENSE
OUT
High
Low
DSENSE2H DSENSE1L DSENSE1H DSENSE2L
Figure 8. TDSTKON
TDSTKON
VINPUT
VOUT
MultiSense
VOUT > VOL
GAPG2609141140CFT
Table 11. Truth table
Mode Conditions INXFR SEn OUTXCurrentSense Comments
Standby All logic inputs low L L L L Hi-Z Low quiescent current
consumption
Normal Nominal load connected;
Tj < 150 °C
L X
See (1)
L
See (1)
H L H Outputs configured for
auto-restart
H H H Outputs configured for
Latch-off
Overload
Overload or short to GND
causing:
Tj > TTSD or ΔTj > ΔTj _SD
L X
See (1)
L
See (1)
H L H Output cycles with
temperature hysteresis
H H L Output latches-off
VN7E010AJ
Main electrical characteristics
DS11954 - Rev 5 page 13/46
Mode Conditions INXFR SEn OUTXCurrentSense Comments
Undervoltage VCC < VUSD (falling) X X X L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
OFF-state
diagnostics
Short to VCC L X
See (1) H
See (1)
Open-load L X H External pull-up
Negative output
voltage Inductive loads turn-off L X See (1) < 0 V See (1)
1. Refer to Table 12. CurrentSense multiplexer addressing
Table 12. CurrentSense multiplexer addressing
SEn MUX channel
CurrentSense output
Normal mode Overload OFF-state diag. Negative output
L Hi-Z
H output diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z
Note: If the output channel for the selected MUX channel is latched off while the relevant input is low, the CS pin
delivers feedback according to OFF-State diagnostic.
Example 1: FR = 1; IN = 0; OUT = L (latched); MUX channel = channel 0 diagnostic; CS = 0.
Example 2: FR = 1; IN = 0; OUT = latched, VOUT > VOL; MUX channel = channel 0 diagnostic; CS = VSENSEH
2.4 Waveforms
Figure 9. Latch functionality: behavior in hard short-circuit condition (TAMB << TTSD)
VN7E010AJ
Waveforms
DS11954 - Rev 5 page 14/46
Figure 10. Latch functionality: behavior in hard short-circuit condition
Figure 11. Latch functionality: behavior in hard short-circuit condition (autorestart mode + latch off)
VN7E010AJ
Waveforms
DS11954 - Rev 5 page 15/46
Figure 12. Standby mode activation
Figure 13. Standby state diagram
Normal Operation
Stand-by Mode
INx = Low
AND
FaultRST = Low
AND
SEn = Low
INx = High
OR
FaultRST = High
OR
SEn = High
{
t > t D_STBY
GAPG1003141053CFT
VN7E010AJ
Waveforms
DS11954 - Rev 5 page 16/46
2.5 Electrical characteristics curves
Figure 14. OFF-state output current
GADG111020180937OSOC
1600
1400
1200
1000
800
600
400
200
0
-50 -25 0 25 50 75 100 125 150
Iloff
T [°C]
VCC = 13 V
Vin = Vout = 0
Off State
[nA]
1800
175
Figure 15. Standby current
GADG111020180943STBC
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150
ISTBY
T [°C]
VCC = 13 V
2
[µA]
175
Figure 16. IGND(ON) vs. Iout
GADG111020180950IGIO
4
3.5
3
[mA]
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150
IGND[on]
T [°C]
VCC = 13 V
IOUT = 5 A
2.5
175
Figure 17. Logic input high level voltage
GADG111020180953LILV
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150
T [°C]
ViH , VFRH , VSELH , VSEnH [V]
175
Figure 18. Logic input low level voltage
GADG111020180959LILLV
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150
[V]
T [°C]
VilL ,VFRL ,VSELL ,VSEnL
2
175
Figure 19. High level logic input current
GADG111020181002HLLIC
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150
[µA]
T [°C]
IiH ,IFRH ,ISELH ,ISEnH
4
175
VN7E010AJ
Electrical characteristics curves
DS11954 - Rev 5 page 17/46
Figure 20. Low level logic input current
GADG111020181015LLLIC
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150
[µA]
T [°C]
IiL ,IFRL ,ISELL ,ISEnL
4
175
Figure 21. Logic input hysteresis voltage
GADG111020181017LIHV
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
[V]
T [°C]
Vi(hyst) ,VFR(hyst) ,VSEL(hyst), V SEn(hyst)
1
175
Figure 22. FaultRST Input clamp voltage
GADG111020181021FICV
7
6
5
4
3
2
1
0
-1
-50 -25 0 25 50 75 100 125 150
T [°C]
IIN = 1 mA
IIN = -1 mA
VFRCL [V]
8
175
Figure 23. Undervoltage shutdown
GADG111020181024UNSH
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150
T [°C]
VUSD [V]
8
175
Figure 24. On-state resistance vs. Tcase
GADG111020181028OSRT
45
40
35
30
25
20
15
10
5
0
-50 -25 0 25 50 75 100 125 150
T [°C]
IOUT = 5 A
VCC = 13 V
RDS[on] [mΩ]
175
50
Figure 25. On-state resistance vs. VCC
GADG111020181032ONRV
20
15
10
5
00 5 10 15 20 25 30 35
RDS[on] [mΩ]
VCC [V]
T= 125 °C
T= 25 °C
T= -40 °C
T= 150 °C
25
40
VN7E010AJ
Electrical characteristics curves
DS11954 - Rev 5 page 18/46
Figure 26. Turn-on voltage slope
GADG111020181043TONVS
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
[dVout/dt ]On
T [°C]
VCC = 13 V
RI = 2.6 Ω
[V/µs]
1
175
Figure 27. Turn-off voltage slope
GADG111020181047TOFVS
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
[V/µs]
T [°C]
VCC = 13 V
RI = 2.6 Ω
[dVout/dt ]Off
1
175
Figure 28. Won vs. Tcase
GADG111020181053WONT
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
Won [mJ]
T [°C]
175
1.4
Figure 29. Woff vs. Tcase
GADG111020181054WOFFT
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
Woff [mJ]
T [°C]
1
175
Figure 30. ILIMH vs. Tcase
GADG111020181058ILT
105
100
95
90
85
80
75
70
-50 -25 0 25 50 75 100 125 150
Ilimh [A]
T [°C]
VCC = 13 V
110
Figure 31. OFF-state open-load voltage detection
threshold
GADG111020181101OFFOL
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150
VOL [V]
T [°C]
4
VN7E010AJ
Electrical characteristics curves
DS11954 - Rev 5 page 19/46
Figure 32. Vsense clamp vs. Tcase
GADG111020181104VCT
5
0
-5
-10
-15
-20
-50 -25 0 25 50 75 100 125 150
T [°C]
IIN = 1 mA
IIN = -1 mA
VSENSE_CL [V]
10
Figure 33. Vsenseh vs. Tcase
GADG111020181105VST
9
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150
T [°C]
VSENSEH [V]
10
VN7E010AJ
Electrical characteristics curves
DS11954 - Rev 5 page 20/46
3Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature
swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to
automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the
voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-
mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it
automatically switches off and the diagnostic indication is triggered. According to the voltage level on the
FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or
remains off (FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other
components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current
flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a
safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative
voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor
energy to be dissipated without damaging the device.
VN7E010AJ
Protections
DS11954 - Rev 5 page 21/46
4Application information
Figure 34. Application diagram
VDD
OUT
OUT
OUT
OUT
ADC in
OUT
GND
GND
GND GND
Logic
OUTPUT
GND
FaultRST
INPUT
SEn
SEL
VCC
CS
Current mirror
Rprot
Rprot
Rprot
Rprot
Rprot
+5V
R
GND
Rsense
D
GND
Cext
GND GND
Dld
VN7E010AJ
Application information
DS11954 - Rev 5 page 22/46
4.1 GND protection network against reverse battery
Figure 35. Simplified internal structure
MCU
INPUT
SEn
CS
FaultRST
Vcc
OUTPUT
GND
Rprot
Rprot
Rprot
Rprot
Dld
Rsense
5V
RGND DGND
GND GAPGCFT00830
4.1.1 Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of
the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the
microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares
the same diode/resistor network.
4.2 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the supply lines and injected
into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010.
The related function performance status classification is shown in Table 13. ISO 7637-2 - electrical transient
conduction along supply line.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO
7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed
through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function
does not perform as designed during the test but returns automatically to normal operation after the test”.
VN7E010AJ
GND protection network against reverse battery
DS11954 - Rev 5 page 23/46
Table 13. ISO 7637-2 - electrical transient conduction along supply line
Test Pulse
2011(E)
Test pulse severity level with
Status II functional
performance status
Minimum number
of pulses or test
time
Burst cycle / pulse
repetition time Pulse duration and
pulse generator internal
impedance
Level US (1) min max
1 III -112 V 500 pulses 0.5 s 2 ms, 10 Ω
2a (3) III +55 V 500 pulses 0.2 s 5 s 50 µs, 2 Ω
3a IV -220 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b IV +150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 (2) IV -7 V 1 pulse 100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B (3) 40 V 5 pulse 1 min 400 ms, 2 Ω
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3. With 40 V external suppressor referred to ground (-40°C < Tj < 150 °C).
4.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be
pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from
latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller and the current
required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4 CS - analog current sense
Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the
following signals:
• Current monitor: current mirror of channel output current
Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and
SEn pins, according to the address map in MultiSense multiplexer addressing Table.
VN7E010AJ
MCU I/Os protection
DS11954 - Rev 5 page 24/46
Figure 36. CurrectSense and diagnostic – block diagram
1
n
R
R
V
MUX
I
I
T
0
VCC
Gate Driver
VCC – OUT
Clamp
Limitation
VON
Limitation
Current
Power Limitation
Overtemperature
Open-Load in OFF
Short to VCC K factor
Sense
Current
Control & Diagnostic
shut-down
Undervoltage
Internal Supply
Clamp
VCC – GND
Diagnostic
Fault
SENSEH
CURRENT
MONITOR
GND
INPUT
SEL
SEL
SE
SENSE
PROT
To µC ADC
SENSE
FaultRST
Fault OUT
OUT
CS
GADG0504171037PS
VN7E010AJ
CS - analog current sense
DS11954 - Rev 5 page 25/46
4.4.1 Principle of CurrentSense signal generation
Figure 37. CurrentSense block diagram
INPUT
Vcc
OUT
To uC ADC
RPROT RSENSE
Main MOSSense MOS
Fault
CS
Current sense Switch Block
Current sense
GAPG2307131200CFT
Current sense
The output is able to provide:
• Current mirror proportional to the load current in normal operation, delivering current proportional to the load
according to a known ratio named K
• Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted into a voltage VSENSE by using
an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using
simple equations
Current provided by CS output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
• VSENSE is the voltage measurable on RSENSE resistor
VN7E010AJ
CS - analog current sense
DS11954 - Rev 5 page 26/46
• ISENSE is the current provided from CS pin in current output mode
• IOUT is the current flowing through output
• K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric
factor spread, current sense amplifier offset and process parameters spread of the overall circuitry,
specifying the ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CS pin which is switched to a “current
limited” voltage source, VSENSEH.
In any case, the current sourced by the CS in this condition is limited to ISENSEH.
Figure 38. Analog HSD – open-load detection in off-state
15k
15k
15k
15k
15k
+5V
R
GN D
4.7k
Vbat
Rsense
15k
V
DD
OUT
OUT
OUT
OUT
ADC in
GND
OUT
100nF
GND
GND GND GND GND GND
100nF/ 50V
CEXT
D
GN D
10 nF /100V
GND
Microcontroller
OUTPUT
Vbat
Rpull-up
External
Pull -Up
switch
Logic
GND
FaultRST
INPUT
SEn
SEL
V
CC
CS
Cu rrent mirro r
OUTPUT
GAPG1201151432CFT
VN7E010AJ
CS - analog current sense
DS11954 - Rev 5 page 27/46
Figure 39. Open-load / short to VCC condition
VSENSEH
VSENSE = 0
VSENSEH
tDSTKON
VSENSE
VSENSE
VIN
Pull-up connected
Pull-up
disconnected
Open-load
Short to VCC
Table 14. CurrentSense pin levels in off-state
Condition Output CS SEn
Open-load
VOUT > VOL
Hi-Z L
VSENSEH H
VOUT < VOL
Hi-Z L
0 H
Short to VCC VOUT > VOL
Hi-Z L
VSENSEH H
Nominal VOUT < VOL
Hi-Z L
0 H
4.4.2 Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the
device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature
of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive
supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby
current consumption to increase in normal conditions, i.e. when load is connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation:
VN7E010AJ
CS - analog current sense
DS11954 - Rev 5 page 28/46
Equation
R
PU < V
PU - 4
IL(off2)min @ 4V
VN7E010AJ
CS - analog current sense
DS11954 - Rev 5 page 29/46
5Maximum demagnetization energy (VCC = 16 V)
Figure 41. Maximum turn off current versus inductance
1
10
100
0.1 1 10 100 1000
I (A)
L (mH)
VN7E010AJ - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
Figure 42. Maximum turn off energy versus inductance
1
10
100
1000
10000
0.1 1 10 100 1000
EI (mJ)
L (mH)
VN7E010AJ - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
Note: Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the
temperature specified above for curves A and B.
VN7E010AJ
Maximum demagnetization energy (VCC = 16 V)
DS11954 - Rev 5 page 30/46
6Package and PCB thermal data
6.1 PowerSSO-16 thermal data
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
VN7E010AJ
Package and PCB thermal data
DS11954 - Rev 5 page 31/46
Table 15. PCB properties
Dimension Value
Board finish thickness 1.6 mm +/- 10%
Board dimension 77 mm x 86 mm
Board material FR4
Copper thickness (top and bottom layers) 0.070 mm
Copper thickness (inner layers) 0.035 mm
Thermal vias separation 1.2 mm
Thermal via diameter 0.3 mm +/- 0.08 mm
Copper thickness on vias 0.025 mm
Footprint dimension (top layer) 2.2 mm x 3.9 mm
Heatsink copper area dimension (bottom layer) Footprint, 2 cm2 or 8 cm2
Figure 45. Rthj-amb vs PCB copper area in open box free air condition (one channel on)
30
40
50
60
70
80
90
0 2 4 6 8 10
RTHjamb
RTHjamb
VN7E010AJ
PowerSSO-16 thermal data
DS11954 - Rev 5 page 32/46
Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000
ZTH (°C/W)
Time (s)
Cu=foot print
Cu=2 cm2
Cu=8 cm2
4 Layer
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
Figure 47. Thermal fitting model of a double-channel HSD in PowerSSO-16
Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
VN7E010AJ
PowerSSO-16 thermal data
DS11954 - Rev 5 page 33/46
Table 16. Thermal parameters
Area/island (cm²) FP 2 8 4L
R1 (°C/W) 0.4
R2 (°C/W) 3
R3 (°C/W) 5.6 5.6 5.6 4
R4 (°C/W) 16 6 6 4
R5 (°C/W) 30 20 10 3
R6 (°C/W) 26 20 18 7
C1 (W·s/°C) 0.0007
C2 (W·s/°C) 0.009
C3 (W·s/°C) 0.13
C4 (W·s/°C) 0.2 0.3 0.3 0.4
C5 (W·s/°C) 0.4 1 1 4
C6 (W·s/°C) 3 5 7 18
VN7E010AJ
PowerSSO-16 thermal data
DS11954 - Rev 5 page 34/46
7Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
7.1 PowerSSO-16 package information
Figure 48. PowerSSO-16 package dimensions
GAPG1605141159CFT
8017965_Rev_9
Bottom view
Top view
Section A-A
Section B-B
θ1
θ3
θ2
h
h
R1
R
L1
L
B
B
GAUGE PLANE
S
θ
b1
cc1
b
BASE METAL
WITH PLATING
E2E3
D2
D3
AA2
A1 b
SEATING PLANE
for dual gauge only
for dual gauge only
ccc C
C
H
eee C
ggg
ggg A-B DC
A-B DC
e
index area
(0.25D x 0.75E1)
2x N/2 TIPS
2x
1.2
aaa C D
N
123
D
EE1
f f f
ddd
C
bbb C
C D
A-B
AD
B
2x
AN/2
A
minimum solderable area
VN7E010AJ
Package information
DS11954 - Rev 5 page 35/46
Table 17. PowerSSO-16 mechanical data
Symbol
Millimeters
Min. Typ. Max.
Θ 0° 8°
Θ1 0°
Θ2 5° 15°
Θ3 5° 15°
A 1.70
A1 0.00 0.10
A2 1.10 1.60
b 0.20 0.30
b1 0.20 0.25 0.28
c 0.19 0.25
c1 0.19 0.20 0.23
D 4.90 BSC
D2 3.31 3.91
D3 2.61
e 0.50 BSC
E 6.00 BSC
E1 3.90 BSC
E2 2.20 2.80
E3 1.49
h 0.25 0.50
L 0.40 0.60 0.85
L1 1.00 REF
N 16
R 0.07
R1 0.07
S 0.20
Tolerance of form and position
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.08
eee 0.10
fff 0.10
ggg 0.15
VN7E010AJ
PowerSSO-16 package information
DS11954 - Rev 5 page 36/46
7.2 PowerSSO-16 packing information
Figure 49. PowerSSO-16 reel 13"
Access Hole at
Slot Location
( 40 mm min.)
If present,
tape slot in core
for tape start:
2.5 mm min. width x
10.0 mm min. depth
C
N
W2
W1
D
A
B
TAPG2004151655CFT
Table 18. Reel dimensions
Description Value(1)
Base quantity 2500
Bulk quantity 2500
A (max) 330
B (min) 1.5
C (+0.5, -0.2) 13
D (min) 20.2
N 100
W1 (+2 /-0) 12.4
W2 (max) 18.4
1. All dimensions are in mm.
VN7E010AJ
PowerSSO-16 packing information
DS11954 - Rev 5 page 37/46
Figure 50. PowerSSO-16 carrier tape
0.30 ±0.05 1.55 ±0.05
1.6 ±0.1
R 0.5
Typical
K1
K0
B0
P2
2.0 ±0.1
P0
4.0 ±0.1
P1A0
F
W
1.75 ±0.1
SECTION X - X
SECTION Y - Y
REF 4.18
REF 0.6
REF 0.5
X
X
Y Y
GAPG2204151242CFT
Table 19. PowerSSO-16 carrier tape dimensions
Description Value(1)
A06.50 ± 0.1
B05.25 ± 0.1
K02.10 ± 0.1
K11.80 ± 0.1
F 5.50 ± 0.1
P18.00 ± 0.1
W 12.00 ± 0.3
1. All dimensions are in mm.
Figure 51. PowerSSO-16 schematic drawing of leader and trailer tape
Embossed carrier
Carrier tape
Round sprocket holes
Elongated sprocket holes
Top cover tape
(32 mm tape and wider)
Top cover tape
Trailer
160 mm minimum
Leader
100 mm min.
400 mm minimumComponents
User direction feed
Punched carrier
8 mm & 12 mm only
END START
GAPG2004151511CFT
VN7E010AJ
PowerSSO-16 packing information
DS11954 - Rev 5 page 38/46
7.3 PowerSSO-16 marking information
Figure 52. PowerSSO-16 marking information
Spe cial function digit
&: Engineering sample
<blank>: Commercial sample
PowerSSO-16 TOP VIEW
(not to scale)
GADG0310161234SMD
Parts marked as ‘&’ are not yet qualified and therefore not approved for use in production. ST is not responsible
for any consequences resulting from such use. In no event will ST be liable for the customer using any of these
engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
VN7E010AJ
PowerSSO-16 marking information
DS11954 - Rev 5 page 39/46
8Ordering information
Table 20. Ordering information
Package
Order codes
Tape and reel
VN7E010AJTR PowerSSO-16
VN7E010AJ
Ordering information
DS11954 - Rev 5 page 40/46
Revision history
Table 21. Document revision history
Date Revision Changes
18-Jan-2017 1 Initial release.
09-Oct-2017 2
Updated Figure 3: "Current and voltage conventions" Updated value for EMAX Table 3: "Absolute
maximum ratings" Updated Table 6: "Power section" Updated Table 7: "Switching". Updated Table
10: "CurrentSense" Updated Table 13: "ISO 7637-2 - electrical transient conduction along supply
line"
19-Jun-2018 3
Updated applications in cover page.
Updated Table 3. Absolute maximum ratings, Section 2.2 Thermal data and Section 8 Ordering
information.
Inserted Section 5 Maximum demagnetization energy (VCC = 16 V) and Section 6 Package and
PCB thermal data.
11-Oct-2018 4 Updated Table 5. Electrical characteristics during cranking and Table 7. Switching.
Added Section 2.5 Electrical characteristics curves .
08-Nov-2018 5 Updated features in cover page, Table 4. Thermal data and Section 7.1 PowerSSO-16 package
information.
VN7E010AJ
DS11954 - Rev 5 page 41/46
Contents
1Block diagram and pin description .................................................3
2Electrical specification.............................................................5
2.1 Absolute maximum ratings.......................................................5
2.2 Thermal data ..................................................................6
2.3 Main electrical characteristics ....................................................6
2.4 Waveforms ...................................................................14
2.5 Electrical characteristics curves .................................................17
3Protections .......................................................................21
3.1 Power limitation ...............................................................21
3.2 Thermal shutdown.............................................................21
3.3 Current limitation ..............................................................21
3.4 Negative voltage clamp ........................................................21
4Application information...........................................................22
4.1 GND protection network against reverse battery....................................22
4.1.1 Diode (DGND) in the ground line............................................23
4.2 Immunity against transient electrical disturbances ..................................23
4.3 MCU I/Os protection ...........................................................24
4.4 CS - analog current sense ......................................................24
4.4.1 Principle of CurrentSense signal generation ...................................25
4.4.2 Short to VCC and OFF-state open-load detection ...............................28
5Maximum demagnetization energy (VCC = 16 V)...................................30
6Package and PCB thermal data ...................................................31
6.1 PowerSSO-16 thermal data .....................................................31
7Package information..............................................................35
7.1 PowerSSO-16 package information ..............................................35
7.2 PowerSSO-16 packing information ...............................................36
7.3 PowerSSO-16 marking information...............................................38
8Ordering information .............................................................40
Revision history .......................................................................41
VN7E010AJ
Contents
DS11954 - Rev 5 page 42/46
List of tables
Table 1. Pin functions .......................................................................3
Table 2. Suggested connections for unused and not connected pins .......................................4
Table 3. Absolute maximum ratings .............................................................5
Table 4. Thermal data.......................................................................6
Table 5. Electrical characteristics during cranking....................................................6
Table 6. Power section ......................................................................6
Table 7. Switching .........................................................................7
Table 8. Logic inputs........................................................................8
Table 9. Protections ........................................................................9
Table 10. CurrentSense ......................................................................9
Table 11. Truth table ....................................................................... 13
Table 12. CurrentSense multiplexer addressing ..................................................... 14
Table 13. ISO 7637-2 - electrical transient conduction along supply line .................................... 24
Table 14. CurrentSense pin levels in off-state ...................................................... 28
Table 15. PCB properties .................................................................... 32
Table 16. Thermal parameters ................................................................. 34
Table 17. PowerSSO-16 mechanical data ......................................................... 36
Table 18. Reel dimensions ................................................................... 37
Table 19. PowerSSO-16 carrier tape dimensions .................................................... 38
Table 20. Ordering information................................................................. 40
Table 21. Document revision history ............................................................. 41
VN7E010AJ
List of tables
DS11954 - Rev 5 page 43/46
List of figures
Figure 1. Block diagram ....................................................................3
Figure 2. Configuration diagram (top view)........................................................4
Figure 3. Current and voltage conventions........................................................5
Figure 4. IOUT/ISENSE versus IOUT ............................................................ 11
Figure 5. Current sense accuracy versus IOUT .................................................... 12
Figure 6. Switching time and pulse skew ........................................................ 12
Figure 7. CurrentSense timings (current sense mode) ............................................... 13
Figure 8. TDSTKON ....................................................................... 13
Figure 9. Latch functionality: behavior in hard short-circuit condition (TAMB << TTSD).......................... 14
Figure 10. Latch functionality: behavior in hard short-circuit condition ..................................... 15
Figure 11. Latch functionality: behavior in hard short-circuit condition (autorestart mode + latch off) ................ 15
Figure 12. Standby mode activation ............................................................ 16
Figure 13. Standby state diagram.............................................................. 16
Figure 14. OFF-state output current ............................................................ 17
Figure 15. Standby current .................................................................. 17
Figure 16. IGND(ON) vs. Iout .................................................................. 17
Figure 17. Logic input high level voltage ......................................................... 17
Figure 18. Logic input low level voltage .......................................................... 17
Figure 19. High level logic input current.......................................................... 17
Figure 20. Low level logic input current .......................................................... 18
Figure 21. Logic input hysteresis voltage ......................................................... 18
Figure 22. FaultRST Input clamp voltage......................................................... 18
Figure 23. Undervoltage shutdown ............................................................. 18
Figure 24. On-state resistance vs. Tcase ......................................................... 18
Figure 25. On-state resistance vs. VCC ......................................................... 18
Figure 26. Turn-on voltage slope .............................................................. 19
Figure 27. Turn-off voltage slope .............................................................. 19
Figure 28. Won vs. Tcase ................................................................... 19
Figure 29. Woff vs. Tcase ................................................................... 19
Figure 30. ILIMH vs. Tcase ................................................................... 19
Figure 31. OFF-state open-load voltage detection threshold ........................................... 19
Figure 32. Vsense clamp vs. Tcase ............................................................. 20
Figure 33. Vsenseh vs. Tcase ................................................................. 20
Figure 34. Application diagram................................................................ 22
Figure 35. Simplified internal structure .......................................................... 23
Figure 36. CurrectSense and diagnostic – block diagram ............................................. 25
Figure 37. CurrentSense block diagram ......................................................... 26
Figure 38. Analog HSD – open-load detection in off-state ............................................. 27
Figure 39. Open-load / short to VCC condition ..................................................... 28
Figure 41. Maximum turn off current versus inductance............................................... 30
Figure 42. Maximum turn off energy versus inductance ............................................... 30
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ................................. 31
Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ................................. 31
Figure 45. Rthj-amb vs PCB copper area in open box free air condition (one channel on) ........................ 32
Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .................... 33
Figure 47. Thermal fitting model of a double-channel HSD in PowerSSO-16 ................................ 33
Figure 48. PowerSSO-16 package dimensions .................................................... 35
Figure 49. PowerSSO-16 reel 13" ............................................................. 37
Figure 50. PowerSSO-16 carrier tape ........................................................... 38
Figure 51. PowerSSO-16 schematic drawing of leader and trailer tape .................................... 38
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DS11954 - Rev 5 page 46/46
