SN74ACT3631-15PCB - Texas Instruments

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

Clocked FIFO Buffering Data From Port A

to Port B

Synchronous Read-Retransmit Capability

Mailbox Register in Each Direction

Programmable Almost-Full and

Almost-Empty Flags

Microprocessor Interface Control Logic

Input-Ready and Almost-Full Flags

Synchronized by CLKA

Output-Ready and Almost-Empty Flags

Synchronized by CLKB

Low-Power 0.8-µm Advanced CMOS

Technology

Supports Clock Frequencies up to 67 MHz

Fast Access Times of 11 ns

Pin-to-Pin Compatible With the

SN74ACT3641 and SN74ACT3651

Package Options Include 120-Pin Thin

Quad Flat (PCB) and 132-Pin Plastic Quad

Flat (PQ) Packages

description

The SN74ACT3631 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies

up to 67 MHz and has read access times as fast as 1 1 ns. The 512 × 36 dual-port SRAM FIFO buffers data from

port A to port B. The FIFO memory has retransmit capability , which allows previously read data to be accessed

again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and

almost empty) to indicate when a selected number of words is stored in memory . Communication between each

port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail

has been stored. Two or more devices can be used in parallel to create wider datapaths. Expansion also is

possible in word depth.

The SN74ACT3631 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable

signals. The continuous clocks for each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple interface between microprocessors

and/or buses with synchronous control.

The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The

output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset

values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.

The SN74ACT3631 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering

(literature number SCAA007)

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number

SCAA007)

Metastability Performance of Clocked FIFOs (literature number SCZA004).

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCB PACKAGE

(TOP VIEW)

A35

A34

A33

A32

VCC

A31

A30

GND

A29

A28

A27

A26

A25

A24

A23

GND

A22

VCC

A21

A20

A19

A18

GND

A17

A16

A15

A14

A13

VCC

A12

B35

B34

B33

B32

GND

B31

B30

B29

B28

B27

B26

VCC

B25

B24

GND

B23

B22

B21

B20

B19

B18

GND

B17

B16

VCC

B15

B14

B13

B12

GND

CLKA

ENA

GND

A11

A10

CSA

MBA

GND

FS0/SD

FS1/SEN

RTM

MBF1

GND

W/RA

GND

CSB

W/RB

ENB

CLKB

B10

VCC

RST

VCC

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

MBB

VCC

GND

VCC

B11

MBF2

VCC

RFM

NC – No internal connection

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

132131130129128127

126125

124123122121

120119118 117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

5251 83828180797877767574737271706968676665646362616059585756555453

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

B35

B34

B33

B32

GND

B31

B30

B29

B28

B27

B26

VCC

B25

B24

GND

B23

B22

B21

B20

B19

B18

GND

B17

B16

VCC

B15

B14

B13

B12

GND

A35

A34

A33

A32

VCC

A31

A30

GND

A29

A28

A27

A26

A25

A24

A23

GND

A22

VCC

A21

A20

A19

A18

GND

A17

A16

A15

A14

A13

VCC

A12

PQ PACKAGE

†

(TOP VIEW)

CLKB

ENB

W/RB

GND

MBF1

GND

MBB

RTM

FS1/SEN

FS0/SD

GND

RST

MBA

MBF2

CSA

W/RA

ENA

CLKA

GND

B11

B10

GND

A10

A11

GND

VCC

RFM

CSB

VCC

NC – No internal connection

†Uses Y amaichi socket IC51-1324-828

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Port-A

Control

Logic

CLKA

CSA

W/RA

ENA

MBA

Reset

Logic

RST

512 × 36

SRAM

Input Register

Output Register

Mail1

Write

Pointer Read

Pointer

Status-Flag

Logic

Flag-Offset

Mail2

Port-B

Control

Logic

FS0/SD

FS1/SEN

A0–A35

MBF2

MBF1

B0–B35

CLKB

CSB

W/RB

ENB

MBB

Synch

Retransmit

Logic

RTM

RFM

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME I/O DESCRIPTION

A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.

AE O Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less

than or equal to the value in the almost-empty of fset register (X).

AF O Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO

is less than or equal to the value in the almost-full offset register (Y).

B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.

CLKA I Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous

or coincident to CLKB. IR and AF are synchronous to the low-to-high transition of CLKA.

CLKB I Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous

or coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB.

CSA I Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

A0–A35 outputs are in the high-impedance state when CSA is high.

CSB I Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

B0–B35 outputs are in the high-impedance state when CSB is high.

ENA I Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB I Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

FS1/SEN,

FS0/SD I

Flag offset select 1/serial enable, flag of fset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used

for flag offset register programming. During a device reset, FS1/SEN and FS0/SD select the flag of fset programming

method. Three offset register programming methods are available: automatically load one of two preset values, parallel

load from port A, and serial load.

When serial load is selected for flag of fset register programming, FS1/SEN is used as an enable synchronous to the

low-to-high transition of CLKA. When FS1/SEN is low , a rising edge on CLKA loads the bit present on FS0/SD into the

X- and Y -of fset registers. The number of bit writes required to program the offset register is 18. The first bit write stores

the Y-register MSB and the last bit write stores the X-register LSB.

IR O Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes

to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the

point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.

MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.

MBB I Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the

B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects

FIFO data for output.

MBF1 O Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1

is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by

a reset.

MBF2 O Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2

is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by

a reset.

OR O Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and

reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during

the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.

RFM I Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to reset

the read pointer to the beginning retransmit location and output the first selected retransmit data.

RST I Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

while RST is low . The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.

RTM I

Retransmit mode. When R TM is high and valid data is present in the FIFO output register (OR is high), a low-to-high

transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected

word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low , taking the FIFO

out of retransmit mode.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME I/O DESCRIPTION

W/RA I Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a

low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.

W/RB I Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a

low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is low.

detailed description

reset

The SN74ACT3631 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four

port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset

initializes the memory read and write pointers and forces the input-ready (IR) flag low, the output-ready (OR)

flag high, the almost-empty (AE) flag low, and the almost-full (AF) flag high. Resetting the device also forces

the mailbox flags (MBF1, MBF2) high. After a FIFO is reset, its input-ready flag is set high after at least two clock

cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.

almost-empty flag and almost-full flag offset programming

Two registers in the SN74ACT3631 are used to hold the offset values for the almost-empty and almost-full flags.

The almost-empty (AE) flag offset register is labeled X, and the almost-full (AF ) flag offset register is labeled Y.

The offset registers can be loaded with a value in three ways: one of two preset values is loaded into the of fset

registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag

select (FS1, FS0) inputs during a low-to-high transition on the RST input (see Table 1).

Table 1. Flag Programming

FS1 FS0 RST X AND Y REGISTERS†

H H ↑Serial load

H L ↑64

L H ↑8

L L ↑Parallel load from port A

†X register holds the offset for AE; Y register holds the

offset for AF.

preset values

If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of a RST low-to-high transition according to

Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is

necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.

parallel load from port A

To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high

transition of RST. After this reset is complete, the IR flag is set high after two low-to-high transitions on CLKA.

The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X.

Each offset register of the SN74ACT3631 uses port-A inputs (A8–A0). The highest number input is used as

the most-significant bit of the binary number in each case. Each register value can be programmed from 1 to

508. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

serial load

To serially program the X and Y registers, the device is reset with FS0/SD and FS1/SEN high during the

low-to-high transition of RST . After this reset is complete, the X- and Y -register values are loaded bitwise through

FS0/SD on each low-to-high transition of CLKA that FS1/SEN is low. Writes of 18 bits are needed to complete

the programming. The first bit write stores the most-significant bit of the Y register , and the last bit write stores

the least-significant bit of the X register. Each register value can be programmed from 1 to 508.

When the option to program the offset registers serially is chosen, the input-ready (IR) flag remains low until

all register bits are written. The IR flag is set high by the low-to-high transition of CLKA after the last bit is loaded

to allow normal FIFO operation.

FIFO write/read operation

The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-A

write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is

high. The A0–A35 outputs are active when both CSA and W/RA are low.

Data is loaded into the FIFO from the A0–A35 inputs on a low-to-high transition of CLKA when CSA and the

port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the input-ready (IR) flag are high

(see Table 2). Writes to the FIFO are independent of any concurrent FIFO reads.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA A0–A35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None

L H L X X In high-impedance state None

L H H L ↑In high-impedance state FIFO write

L H H H ↑In high-impedance state Mail1 write

L L L L X Active, mail2 register None

L L H L ↑Active, mail2 register None

L L L H X Active, mail2 register None

L L H H ↑Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A, with the exception that the port-B write/read select

(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0–B35) outputs is

controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0–B35 outputs are

in the high-impedance state when either CSB is high or W/RB is low. The B0–B35 outputs are active when CSB

is low and W/RB is high.

Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and the port-B

mailbox select (MBB) are low, W/RB, the port-B enable (ENB), and the output-ready (OR) flag are high

(see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB MBB CLKB B0–B35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None

L L L X X In high-impedance state None

L L H L ↑In high-impedance state None

L L H H ↑In high-impedance state Mail2 write

L H L L X Active, FIFO output register None

L H H L ↑Active, FIFO output register FIFO read

L H L H X Active, mail1 register None

L H H H ↑Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only

for enabling write and read operations and are not related to high-impedance control of the data outputs. If a

port enable is low during a clock cycle, the port-chip select and write/read select can change states during the

setup- and hold-time window of the cycle.

When the output-ready (OR) flag is low , the next data word is sent to the FIFO output register automatically by

the CLKB low-to-high transition that sets the output-ready flag high. When OR is high, an available data word

is clocked to the FIFO output register only when a FIFO read is selected by the port-B chip select (CSB),

write/read select (W/RB), enable (ENB), and mailbox select (MBB).

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the

flags’ reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate

asynchronously to one another.

OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA.

Table 4 shows the relationship of each flag to the number of words stored in memory.

Table 4. FIFO Flag Operation

NUMBER OF WORDS IN

FIFO†‡

SYNCHRONIZED

TO CLKB SYNCHRONIZED

TO CLKA

FIFO†‡

OR AE AF IR

0 L L H H

1 to X H LHH

(X + 1) to [512 – (Y + 1)] H HHH

(512 – Y) to 511 H HLH

512 H H L L

†X is the almost-empty offset for AE. Y is the almost-full offset for AF.

‡When a word is present in the FIFO output register , its previous memory

location is free.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

output-ready flag (OR)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). When

the output-ready flag is high, new data is present in the FIFO output register . When the output-ready flag is low ,

the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to its output register . From the time a word

is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB; therefore,

an output-ready flag is low if a word in memory is the next data to be sent to the FIFO output register and three

CLKB cycles have not elapsed since the time the word was written. The output-ready flag of the FIFO remains

low until the third low-to-high transition of CLKB occurs, simultaneously forcing the output-ready flag high and

shifting the word to the FIFO output register.

A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition

occurs at time tsk(1), or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first

synchronization cycle (see Figure 6).

input-ready flag (IR)

The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). When the

input-ready flag is high, a memory location is free in the SRAM to write new data. No memory locations are free

when the input-ready flag is low and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO,

its previous memory location is ready to be written in a minimum of three cycles of CLKA; therefore, an

input-ready flag is low if less than two cycles of CLKA have elapsed since the next memory write location has

been read. The second low-to-high transition on CLKA after the read sets the input-ready flag high, and data

can be written in the following cycle.

A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition

occurs at time tsk(1), or greater, after the read. Otherwise, the subsequent CLKA cycle can be the first

synchronization cycle (see Figure 7).

almost-empty flag (AE)

The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). The

almost-empty state is defined by the contents of register X. This register is loaded with a preset value during

a FIFO reset, programmed from port A, or programmed serially (see

almost-empty flag and almost-full flag offset

programming

). The almost-empty flag is low when the FIFO contains X or fewer words and is high when the

FIFO contains (X + 1) or more words. A data word present in the FIFO output register has been read from

memory.

T wo low-to-high transitions of CLKB are required after a FIFO write for the almost-empty flag to reflect the new

level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low if two cycles

of CLKB have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set

high by the second low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level.

A low-to-high transition of CLKB begins the first synchronization cycle if it occurs at time tsk(2), or greater , after

the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first

synchronization cycle (see Figure 8).

almost-full flag (AF)

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The almost-full

state is defined by the contents of register Y. This register is loaded with a preset value during a FIFO reset,

programmed from port A, or programmed serially (see

almost-empty flag and almost-full flag offset

programming

). The almost-full flag is low when the number of words in the FIFO is greater than or equal to

(512 – Y). The almost-full flag is high when the number of words in the FIFO is less than or equal to

[512 – (Y + 1)]. A data word present in the FIFO output register has been read from memory.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

T wo low-to-high transitions of CLKA are required after a FIFO read for its almost-full flag to reflect the new level

of fill; therefore, the almost-full flag of a FIFO containing [512 – (Y + 1)] or fewer words remains low if two cycles

of CLKA have not elapsed since the read that reduced the number of words in memory to [512 – (Y + 1)]. An

almost-full flag is set high by the second low-to-high transition of CLKA after the FIFO read that reduces the

number of words in memory to [512 – (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization

cycle if it occurs at time tsk(2), or greater, after the read that reduces the number of words in memory to

[512 – (Y + 1)]. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 9).

synchronous retransmit

The synchronous-retransmit feature of the SN74ACT3631 allows FIFO data to be read repeatedly starting at

a user-selected position. The FIFO is first put into retransmit mode to select a beginning word and prevent

ongoing FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three

words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode

at any time and allow normal device operation.

The FIFO is put in retransmit mode by a low-to-high transition on CLKB when the retransmit-mode (RTM) input

is high and OR is high. This rising CLKB edge marks the data present in the FIFO output register as the first

retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.

When two or more reads occur after the initial retransmit word, a retransmit is initiated by a low-to-high transition

on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the first retransmit word

to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can be done

endlessly while the FIFO is in retransmit mode. RFM must be low during the CLKB rising edge that takes the

FIFO out of retransmit mode.

When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operates

normally , incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE

flags. The shadow read pointer stores the SRAM location at the time the device is put into retransmit mode and

does not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IR

and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that

stores (512 – Y) words after the first retransmit word. The IR flag is set low by the 512th write after the first

retransmit word.

When the FIFO is in retransmit mode and RFM is high, a rising CLKB edge loads the current read pointer with

the shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes

the FIFO status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are

needed to switch AE high (see Figure 11). The rising CLKB edge that takes the FIFO out of retransmit mode

shifts the read pointer used by the IR and AF flags from the shadow to the current read pointer. If the change

of read pointer used by IR and AF should cause one or both flags to transition high, at least two CLKA

synchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after the FIFO is taken

out of retransmit mode is the first synchronizing cycle of IR if it occurs at time tsk(1), or greater, after the rising

CLKB edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of retransmit mode is the first

synchronizing cycle of AF if it occurs at time tsk(2), or greater, after the rising CLKB edge (see Figure 14).

mailbox registers

Two 36-bit bypass registers pass command and control information between port A and port B. The

mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation.

A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port-A write is selected by

CSA, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0–B35 data to the mail2 register

when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail register sets its

corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while its mail flag is

low.

SN74ACT3631

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When the port-B data (B0–B35) outputs are active, the data on the bus comes from the FIFO output register

when the port-B mailbox select (MBB) input is low and from the mail1 register when MBB is high. Mail2 data

is always present on the port-A data (A0–A35) outputs when they are active. The mail1 register flag (MBF1)

is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB with

MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read

is selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read

and changes only when new data is written to the register.

tpd(R-F)

ÎÎÎÎÎÎÎ

ÏÏÏÏÏÏÏÏÏÏÏÏ

CLKA

CLKB

RST

0,1

th(FS)

tsu(FS)

th(RS)

tsu(RS)

FS1, FS0

tpd(C-IR)

ÌÌÌÌÌÌÌÌÌÌÌ

tpd(C-IR)

tpd(C-OR)

ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ

tpd(R-F)

ÌÌÌÌÌÌÌ

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

ÎÎÎÎÎÎÎ

MBF1,

MBF2

tpd(R-F)

Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight

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ÏÏÏÏ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÌÌÌÌ

AE Offset

(X)

CLKA

RST

FS1, FS0

ENA

A0–A35

tsu(FS) th(FS)

tpd(C-IR)

ÌÌÌÌ

ÏÏÏÏ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÏÏÏÏ

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

AF Offset

(Y) First Word Stored in FIFO

th(D)

tsu(D)

tsu(EN) th(EN)

ÏÏÏÏ

NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register bits on consecutive clock cycles.

Figure 2. Programming the AF Flag and AE Flag Offset Values From Port A

ÏÏÏÏÏÏÏÏÏ

ÎÎÎÎÎÎÎÎÎ

ÏÏÏÏÏ

ÏÏÏÏÏÏÏ

ÎÎÎÎ

ÏÏÏ

AE Offset

(X) LSB

CLKA

RST

FS1/SEN

FS0/SD

tsu(FS) th(FS)

tpd(C-IR)

ÏÏÏÏÏ

AF Offset

(Y) MSB

th(SD)

tsu(SD)

ÏÏÏÏÏ

th(SD)

tsu(SD)

th(SEN)

tsu(SEN)

th(SP) th(SEN)

tsu(SEN)

tsu(FS)

NOTE A: It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until I R is set high.

Figure 3. Serially Programming the AF Flag and AE Flag Offset Values

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tsu(EN)

tsu(D)

ÏÏÏÏÏÏÏÏ

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

ÌÌÌÌÌÌ

ÏÏÏÏÏÏÏ

ÌÌÌÌÌÌ

CLKA

CSA

tsu(EN)

tw(CLKL)

ÏÏÏÏÏÏ

tw(CLKH)

th(EN)

tsu(EN)

ÏÏÏ

ÎÎÎÎÎÎ

ÌÌÌÌÌÌÌÌ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

W/RA

MBA

ENA

A0–A35 W1

ÎÎÎÎÎÎÎÎ

ÏÏÏ

tsu(EN) th(EN)

th(D)

th(EN)

No Operation

High

Figure 4. FIFO Write-Cycle Timing

tsu(EN)

Operation

tsu(EN)

ÎÎÎ

ÌÌÌÌÌÌ

ÎÎÎÎÎÎ

tsu(EN)

tpd(M-DV)

ÏÏÏ

ÏÏÏÏÏÏÏ

CLKB

CSB

tw(CLKL)

tw(CLKH)

th(EN)

W/RB

MBB

ENB

B0–B35 W3

ÎÎÎÎÎÎÎ

ten tatdis

ÌÌÌÌÌÌ

th(EN) th(EN)

High

Figure 5. FIFO Read-Cycle Timing

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ÌÌÌÌ

tsu(EN)

CLKA

A0–A35

MBA

ENA

CSA

W/RA

CLKB

CSB

W/RB

MBB

ENB

B0–B35

th(EN)

tsu(EN)

ÎÎÎÎÎ

ÏÏÏÏÏ

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

tw(CLKH) tw(CLKL)

th(EN)

tpd(C-OR)

Old Data in FIFO Output Register

ÌÌÌÌÌÌÌÌÌ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

123

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Low

High

tw(CLKL)

tw(CLKH)

High

th(EN)

tsu(EN)

th(D)

tsu(D)

tsk(1)†tc

Low

High

Low

†tsk(1) is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to the FIFO

output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(1), then the transition of

OR high and the first word load to the output register can occur one CLKB cycle later than shown.

Figure 6. OR-Flag Timing and First Data-Word Fall-Through When the FIFO Is Empty

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CLKB

B0–B35

MBB

ENB

CSB

W/RB

CLKA

CSA

W/RA

MBA

ENA

A0–A35

tsu(EN) th(EN)

th(EN)

tsu(EN)

tpd(C-IR)

FIFO Full

tsk(1)†

ÌÌÌÌ

ÎÎÎ

FIFO Output Register Next Word From FIFO

tw(CLKH) tw(CLKL)

ÎÎÎÎÎÎÎÎ

ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ

ÌÌÌÌÌÌÌÌ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

ÏÏÏÏÏÏÏÏ

Write

Low

High

Low

High th(EN)

tsu(EN)

th(D)

tsu(D)

High

tw(CLKH) tw(CLKL)

tpd(C-IR)

†

sk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tsk

(

)

, then IR can transition high one CLKA cycle later than shown.

Figure 7. IR-Flag Timing and First Available Write When the FIFO Is Full

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(X + 1) Words in FIFO

ÌÌÌÌÌ

ÎÎÎÎÎ

tsu(EN)

CLKA

ENB

ENA

th(EN)

tsu(EN)

tsk(2)†

tpd(C-AE)

X Words in FIFO

ÎÎÎÎÎ

CLKB 2tpd(C-AE)

th(EN)

ÌÌÌÌÌ

†tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than tsk(2), then AE can transition high one CLKB cycle later than shown.

NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)

Figure 8. Timing for AE When FIFO Is Almost Empty

(512 – Y) Words in FIFO

tpd(C-AF) tpd(C-AF)

tsu(EN)

ÌÌÌÌÌ

CLKA

ENB

ENA

tsu(EN) th(EN)

[512 – (Y + 1)] Words in FIFO

ÎÎÎÎÎ

th(EN)

tsk(2)‡

ÌÌÌÌÌ

ÎÎÎÎÎ

CLKB

‡tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tsk(2), then AF can transition high one CLKA cycle later than shown.

NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)

Figure 9. Timing for AF When the FIFO Is Almost Full

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ÎÎÎ

ÌÌÌ

ÏÏÏÏ

ÏÏÏ

CLKB

B0–B35

ENB

tsu(EN) th(EN)

W0 W1

High

ÏÏÏÏ

tsu(EN) th(EN)

ÏÏÏ

RTM

RFM

ÌÌ

Initiate Retransmit Mode

With W0 as First Word Retransmit From

Selected Position

tsu(EN) th(EN)

End Retransmit

Mode

NOTE A: CSB = L, W/RB = H, MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit.

Other enables are shown only to relate retransmit operations to the FIFO output register.

Figure 10. Retransmit Timing Showing Minimum Retransmit Length

th(RM)

ÌÌÌÌÌ

ÎÎÎÎÎ

CLKB

RTM High

RFM

tsu(RM)

pd(C-AE)

X or Fewer Words From Empty (X + 1) or More Words From Empty

NOTE A: X is the value loaded in the AE flag offset register.

Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X

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FIFO Filled to First Retransmit Word

ÏÏÏÏÏ

ÌÌÌÌ

CLKA

tsu(EN) th(EN)

RTM

tsk(1)†

CLKB

tpd(C-IR)

One or More Write Locations Available

†tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tsk

(

)

, then IR can transition high one CLKA cycle later than shown.

Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available

ÏÏÏÏÏ

ÌÌÌÌ

CLKA

tsu(EN) th(EN)

RTM

tsk(2)‡

(512 – Y) or More Words Past First Retransmit W ord

CLKB

tpd(C-AE)

(Y + 1) or More Write Locations Available

‡tsk(2) is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tsk(2), then AF can transition high one CLKA cycle later than shown.

NOTE A: Y is the value loaded in the AF flag offset register.

Figure 13. AF Timing From the End of Retransmit Mode When (Y + 1)

or More Write Locations Are Available

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ÏÏÏÏÏÏÏÏ

ÎÎÎÎÎÎÎÎ

CLKA

CSA

W/RA

tsu(EN)

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

th(D)

MBA

ENA

A0–A35 W1

ÎÎÎÎÎÎÎÎ

ÏÏÏ

ÎÎÎÎÎÎÎÎ

ÏÏÏ

th(EN)

tsu(D)

CLKB

th(EN)

CSB

tsu(EN)

tpd(C-MF)

MBF1

ÎÎÎÎ

W/RB

ÌÌÌÌÌÌ

MBB

ENB

ÎÎÎÎ

ÌÌÌÌ

B0–B35 FIFO Output Register

ÏÏÏÏ

W1 (remains valid in mail1 register after read)

ÌÌÌÌÌÌ

ten tpd(C-MR) tdis

tpd(M-DV)

Figure 14. Timing for Mail1 Register and MBF1 Flag

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tdis

ÌÌÌÌÌÌÌ

ÎÎÎÎÎÎÎ

ÏÏÏÏÏÏÏÏÏ

tpd(C-MR)

ÌÌÌÌÌ

CLKB

CSB

W/RA

MBB

ENB

A0–A35

CLKA

CSA

MBF2

W/RB

MBA

ENA

B0–B35

ÏÏÏÏÏÏÏ

ÎÎÎÎÎÎÎÎ

tsu(EN)

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

th(D)

ÌÌÌÌÌÌÌÌ

ÎÎÎÎÎÎÎÎ

ÏÏÏ

th(EN)

tsu(D)

th(EN)

tsu(EN)

tpd(C-MF)

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎ

ÌÌÌ

W1 (remains valid in mail2 register after read)

ten

ÎÎÎ

Figure 15. Timing for Mail2 Register and MBF2 Flag

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

JA (see Note 2): PCB package 28°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PQ package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

NOTES: 1. The input and output voltage ratings can be exceeded provided the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions

MIN MAX UNIT

VCC Supply voltage 4.5 5.5 V

VIH High-level input voltage 2 V

VIL Low-level input voltage 0.8 V

IOH High-level output current –4 mA

IOL Low-level output current 8 mA

TAOperating free-air temperature 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

VOH VCC = 4.5 V, IOH = –4 mA 2.4 V

VOL VCC = 4.5 V, IOL = 8 mA 0.5 V

IIVCC = 5.5 V, VI = VCC or 0 ±5µA

IOZ VCC = 5.5 V, VO = VCC or 0 ±5µA

ICC VCC = 5.5 V, VI = VCC – 0.2 V or 0 400 µA

CSA = VIH A0–A35 0

V55VOitt34V

CSB = VIH B0–B35 0

∆ICC

VCC = 5.5 V, One input at 3.4 V,

Other in

uts at VCC or GND

CSA = VIL A0–A35 1 mA

Other

in uts

VCC

GND

CSB = VIL B0–B35 1

All other inputs 1

CiVI = 0, f = 1 MHz 4 pF

CoVO = 0, f = 1 MHz 8 pF

‡All typical values are at VCC = 5 V, TA = 25°C.

§This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.

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timing requirements over recommended ranges of supply voltage and operating free-air

temperature (see Figures 1 through 16)

’ACT3631-15 ’ACT3631-20 ’ACT3631-30

UNIT

MIN MAX MIN MAX MIN MAX

UNIT

fclock Clock frequency, CLKA or CLKB 66.7 50 33.4 MHz

tcClock cycle time, CLKA or CLKB 15 20 30 ns

tw(CH) Pulse duration, CLKA and CLKB high 6 8 12 ns

tw(CL) Pulse duration, CLKA and CLKB low 6 8 12 ns

tsu(D) Setup time, A0–A35 before CLKA↑and B0–B35 before CLKB↑7 7.5 8 ns

tsu(SEN)‡Setup time, FS1/SEN before CLKA↑5 6 7 ns

tsu(EN2) Setup time, CSA, W/RA, and MBA to CLKA↑;

CSB, W/RB, and MBB before CLKB↑7 7.5 8 ns

tsu(RM) Setup time, R TM and RFM to CLKB↑6 6.5 7 ns

tsu(RS) Setup time, RST low before CLKA↑ or CLKB↑†567ns

tsu(FS) Setup time, FS0 and FS1 before RST high 9 10 11 ns

tsu(SD)‡Setup time, FS0/SD before CLKA↑5 6 7 ns

tsu(EN1) Setup time, ENA to CLKA↑; ENB to CLKB↑5 6 7 ns

th(D) Hold time, A0–A35 after CLKA↑and B0–B35 after CLKB↑0 0 0 ns

th(EN1) Hold time, ENA after CLKA↑; ENB after CLKB↑0 0 0 ns

th(EN2) Hold time, CSA, W/RA, and MBA after CLKA↑;

CSB, W/RB, and MBB after CLKB↑0 0 0 ns

th(RM) Hold time, RTM and RFM after CLKB↑0 0 0 ns

th(RS) Hold time, RST low after CLKA↑ or CLKB↑†567ns

th(FS) Hold time, FS0 and FS1 after RST high 0 0 0 ns

th(SP)‡Hold time, FS1/SEN high after RST high 0 0 0 ns

th(SD)‡Hold time, FS0/SD after CLKA↑0 0 0 ns

th(SEN)‡Hold time, FS1/SEN after CLKA↑0 0 0 ns

tsk(1)§Skew time between CLKA↑ and CLKB↑ for OR and IR 9 11 13 ns

tsk(2)§Skew time between CLKA↑ and CLKB↑ for AE and AF 12 16 20 ns

†Requirement to count the clock edge as one of at least four needed to reset a FIFO

‡Applies only when serial load method is used to program flag offset registers

§Skew time is not a timing constraint for proper device operation and is included to illustrate the timing relationship between CLKA cycle and CLKB

cycle.

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switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, CL = 30 pF (see Figures 1 through 15)

PARAMETER

’ACT3631-15 ’ACT3631-20 ’ACT3631-30

UNIT

PARAMETER

MIN MAX MIN MAX MIN MAX

UNIT

fmax 66.7 50 33.4 MHz

taAccess time, CLKB↑ to B0–B35 3 11 3 13 15 ns

tpd(C-IR) Propagation delay time, CLKA↑ to IR 0 8 0 10 0 12 ns

tpd(C-OR) Propagation delay time, CLKB↑ to OR 1 8 1 10 1 12 ns

tpd(C-AE) Propagation delay time, CLKB↑ to AE 1 8 1 10 1 12 ns

tpd(C-AF) Propagation delay time, CLKA↑ to AF 1 8 1 10 1 12 ns

tpd(C-MF) Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and

CLKB↑ to MBF2 low or MBF1 high 0 8 0 10 0 12 ns

tpd(C-MR) Propagation delay time, CLKA↑ to B0–B35† and CLKB↑ to

A0–A35‡3 13.5 3 15 3 17 ns

tpd(M-DV) Propagation delay time, MBB to B0–B35 valid 3 13 3 15 3 17 ns

tpd(R-F) Propagation delay time, RST low to AE low and AF high 1 15 1 20 1 30 ns

ten Enable time, CSA and W/RA low to A0–A35 active and CSB

low and W/RB high to B0–B35 active 2 12 2 13 2 14 ns

tdis Disable time, CSA or W/RA high to A0–A35 at high impedance

and CSB high or W/RB low to B0–B35 at high impedance 1 10 1 11 1 12 ns

†Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high

‡Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high

SN74ACT3631

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PARAMETER MEASUREMENT INFORMATION

1.5 V

1.5 V1.5 V

3 V

GND

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data,

Enable

Input

1.5 V 1.5 V 3 V

3 V

GND

High-Level

Input

Low-Level

Input

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

tpd tpd

Input 1.5 V 1.5 V

1.5 V1.5 V

3 V

GND

VOH

VOL

In-Phase

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOL

VOH

tPLZ ≈ 3 V

tPHZ

1.5 V 1.5 V 3 V

GND

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

tPZL

1.5 V

≈ 0 V

1.5 V

tPZH

Output

Enable

Low-Level

Output

High-Level

Output

From Output

Under Test

30 pF

(see Note A)

680 Ω

1100 Ω

5 V

LOAD CIRCUIT

NOTES: A. Includes probe and jig capacitance

B. tPZL and tPZH are the same as ten.

C. tPLZ and tPHZ are the same as tdis.

Figure 16. Load Circuit and Voltage Waveforms

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

fdata = 1/2 fclock

TA = 25°C

CL = 0 pF

I – Supply Current – mA

CC(f)

SUPPLY CURRENT

CLOCK FREQUENCY

fclock – Clock Frequency – MHz

150

100

00 1020304050

200

250

60 70

VCC = 5.5 V

VCC = 5 V

VCC = 4.5 V

Figure 17

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

SN74ACT3631-15PCB ACTIVE HLQFP PCB 120 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

SN74ACT3631-15PQ ACTIVE BQFP PQ 132 36 Green (RoHS &

no Sb/Br) CU NIPDAU Level-4-260C-72 HR

SN74ACT3631-20PCB ACTIVE HLQFP PCB 120 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

SN74ACT3631-20PQ ACTIVE BQFP PQ 132 36 Green (RoHS &

no Sb/Br) CU NIPDAU Level-4-260C-72 HR

SN74ACT3631-30PCB ACTIVE HLQFP PCB 120 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 13-Oct-2009

Addendum-Page 1

MECHANICAL DATA

MBQF001A – NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PQ (S-PQFP-G***) PLASTIC QUAD FLATPACK

100 LEAD SHOWN

0.012 (0,30)

0.008 (0,20)

0.025 (0,635)

Seating Plane

132

1.090 (27,69)

1.070 (27,18)

0.966 (24,54)

0.934 (23,72)

1.112 (28,25)

1.088 (27,64)

0.800 (20,32)

4040045/C 1 1/95

100113

6339

”D2” SQ

”D1” SQ

”D” SQ

”D3” SQ

DIM

”D”

”D2”

”D3”

”D1”

NOM

MIN

MAX

MIN

MAX

MIN

MAX

LEADS ***

0.180 (4,57) MAX

100

0.890 (22,61)

0.870 (22,10)

0.766 (19,46)

0.734 (18,64)

0.912 (23,16)

0.888 (22,56)

0.600 (15,24)

0.004 (0,10)

0.006 (0,15)

0.010 (0,25)

0.020 (0,51) MIN

0.130 (3,30)

0.150 (3,81)

0.006 (0,16) NOM

Gage Plane

0.036 (0,91)

0.046 (1,17)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MO-069

MECHANICAL DATA

MHTQ004A – JANUARY 1995 – REVISED JANUARY 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCB (S-PQFP-G120) PLASTIC QUAD FLATPACK (DIE DOWN)

4040202/C 12/96

31 0,13 NOM

Gage Plane

0,25

0,45

0,75

Seating Plane

0,05 MIN

0,23

11,60 TYP

0,13

120

15,80

16,20

13,80

1,60 MAX

1,45

1,35

14,20

0,08

0,40 M

0,07

0°–7°

Heat Slug

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Thermally enhanced molded plastic package with a heat slug (HSL)

D. Falls within JEDEC MS-026

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