DS26LV32AT
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SNLS128C –APRIL 1999–REVISED FEBRUARY 2013
DS26LV32AT 3V Enhanced CMOS Quad Differential Line Receiver
Check for Samples: DS26LV32AT
1FEATURES • Available in SOIC and CLGA Packaging
• Standard Microcircuit Drawing (SMD) 5962-
2• Low Power CMOS Design (30 mW typical) 98585
• Interoperable with Existing 5V RS-422
Networks DESCRIPTION
• Industrial and Military Temperature Range The DS26LV32A is a high speed quad differential
• Conforms to TIA/EIA-422-B (RS-422) and ITU-T CMOS receiver that meets the requirements of both
V.11 Recommendation TIA/EIA-422-B and ITU-T V.11. The CMOS
DS26LV32AT features typical low static ICC of 9 mA
• 3.3V Operation which makes it ideal for battery powered and power
• ±7V Common Mode Range @ VID = 3V conscious applications. The TRI-STATE enables, EN
• ±10V Common Mode Range @ VID = 0.2V and EN*, allow the device to be active High or active
Low. The enables are common to all four receivers.
• Receiver OPEN Input Failsafe Feature
• Guaranteed AC Parameter: The receiver output (RO) is guaranteed to be High
when the inputs are left open. The receiver can
– Maximum Receiver Skew: 4 ns detect signals as low as ±200 mV over the common
– Maximum Transition Time: 10 ns mode range of ±10V. The receiver outputs (RO) are
• Pin Compatible with DS26C32AT compatible with TTL and LVCMOS levels.
• 32 MHz Toggle Frequency
• > 6.5k ESD Tolerance (HBM)
Connection Diagram
Top View
Figure 1.
SOIC Package
See Package Numbers D0016A or NAD0016A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS26LV32AT
SNLS128C –APRIL 1999–REVISED FEBRUARY 2013
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Truth Table(1)
Enables Inputs Output
EN EN* RI+–RI−RO
L H X Z
All other VID ≥+0.2V H
combinations of VID ≤ −0.2V L
enable inputs Open(2) H
(1) L = Logic Low
H = Logic High
X = Irrelevant
Z = TRI-STATE
(2) Open, not terminated
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC)−0.5V to +7V
Enable Input Voltage (EN, EN*) −0.5V to VCC +0.5V
Receiver Input Voltage (VID: RI+, RI−) ±14V
Receiver Input Voltage
(VCM: RI+, RI−) ±14V
Receiver Output Voltage (RO) −0.5V to VCC +0.5V
Receiver Output Current (RO) ±25 mA Maximum
Maximum Package Power Dissipation @ +25°C
D0016A Package 1190 mW
NAD0016A Package 1087 mW
Derate D0016A Package 9.8 mW/°C above +25°C
Derate NAD0016A Package 7.3 mW/°C above +25°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range Soldering
(4 Sec.) +260°C
ESD Ratings (HBM, 1.5 kΩ, 100 pF)
Receiver Inputs and Enables ≥6.5 kV
Other Pins ≥2 kV
(1) “Absolute Maximum ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The Electrical Characteristics specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Operating Free Air Temperature Range (TA)
DS26LV32AT −40 +25 +85 °C
DS26LV32AW −55 +25 +125 °C
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SNLS128C –APRIL 1999–REVISED FEBRUARY 2013
Electrical Characteristics (1) (2)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
Parameter Test Conditions Pin Min Typ Max Units
VTH Differential Input Threshold VOUT = VOH or VOL VCM =−7V to +7V, −200 ±17.5 +200 mV
TA= -40°C to
+85°C RI+,
VCM =−0.5V to -200 +200 mV
RI−
+5.5V, TA= -55°C
to +125°C(3)
VHY Hysteresis VCM = 1.5V 35 mV
VIH Minimum High Level Input 2.0 V
Voltage EN,
EN*
VIL Maximum Low Level Input 0.8 V
Voltage
RIN Input Resistance VIN =−7V, +7V, TA= -40°C to +85°C 5.0 8.5 kΩ
(Other Input = GND)
VIN =−0.5V, +5.5V, TA= -55°C to +125°C 5.0 kΩ
(Other Input = GND) (3)
IIN Input Current VIN = +10V TA= -40°C to 0 1.1 1.8 mA
+85°C RI+,
(Other Input = 0V, VIN = +3V 0 0.27 mA
RI−
Power On, or VIN = 0.5V −0.02 mA
VCC = 0V) VIN =−3V 0 −0.43 mA
VIN =−10V 0 −1.26 −2.2 mA
VIN =−0.5V TA= -55°C to 0 -1.8 mA
+125°C (3)
VIN = 5.5V 0 1.8 mA
IEN Input Current VIN = 0V to VCC EN, ±1 μA
EN*
VOH High Level Output Voltage IOH =−6 mA, VID = +1V 2.4 3 V
IOH =−6 mA, VID = OPEN
VOH High Level Output Voltage IOH =−100 μA, VID = +1V VCC −0.1 V
IOH =−100 μA, VID = OPEN RO
VOL Low Level Output Voltage IOL = +6 mA, VID =−1V 0.13 0.5 V
IOZ Output TRI-STATE Leakage VOUT = VCC or GND ±50 μA
Current EN = VIL, EN* = VIH
ISC Output Short Circuit Current VO= 0V, VID ≥|200 mV| (4) −10 −35 −70 mA
ICC Power Supply Current No Load, All RI+, TA= -40°C to VCC 9 15 mA
R1−= OPEN, EN, +85°C
EN* = VCC or GND TA= -55°C to 20 mA
+125°C
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VID.
(2) All typicals are given for: VCC = +3.3V, TA= +25°C.
(3) This parameter does not meet the TIA/EIA-422-B specification.
(4) Short one output at a time to ground. Do not exceed package.
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SNLS128C –APRIL 1999–REVISED FEBRUARY 2013
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Switching Characteristics - Industrial (1) (2)
Over Supply Voltage and -40°C to +85°C Operating Temperature range, unless otherwise specified.
Parameter Test Conditions Min Typ Max Units
tPHL Propagation Delay High to Low CL= 15 pF, VCM = 1.5V (Figure 2 and Figure 3) 6 17.5 35 ns
tPLH Propagation Delay Low to High 6 17.8 35 ns
trRise Time (20% to 80%) 4.1 10 ns
tfFall Time (80% to 20%) 3.3 10 ns
tPHZ Disable Time CL= 50 pF, VCM = 1.5V (Figure 4 and Figure 5) 40 ns
tPLZ Disable Time 40 ns
tPZH Enable Time 40 ns
tPZL Enable Time 40 ns
tSK1 Skew, |tPHL −tPLH|(3) CL= 15 pF, VCM = 1.5V 0.3 4 ns
tSK2 Skew, Pin to Pin (4) 0.6 4 ns
tSK3 Skew, Part to Part (2) 7 17 ns
fMAX Maximum Operating Frequency CL= 15 pF, VCM = 1.5V 32 MHz
(5)
(1) All typicals are given for: VCC = +3.3V, TA= +25°C.
(2) tSK3 is the difference in propagation delay times between any channels of any devices. This specification (maximum limit) applies to
devices within VCC ±0.1V of one another, and a Delta TA= ±5°C (between devices) within the operating temperature range. This
parameter is guaranteed by design and characterization.
(3) tSK1 is the |tPHL – tPLH| of a channel.
(4) tSK2 is the maximum skew between any two channels within a device, either edge.
(5) All channels switching, Output Duty Cycle criteria is 40%/60% measured at 50%. Input = 1V to 2V, 50% Duty Cycle, tr/tf≤5 ns. This
parameter is guaranteed by design and characterization.
Switching Characteristics - Military
Over Supply Voltage and -55°C to +125°C Operating Temperature range, unless otherwise specified.
Parameter Test Conditions Min Max Units
tPHL Propagation Delay High to Low CL= 50 pF, VCM = 1.5V (Figure 2 and Figure 3) 6 45 ns
tPLH Propagation Delay Low to High 6 45 ns
tPHZ Disable Time CL= 50 pF, VCM = 1.5V (Figure 4 and Figure 5) 50 ns
tPLZ Disable Time 50 ns
tPZH Enable Time 50 ns
tPZL Enable Time 50 ns
tSK1 Skew, |tPHL −tPLH|(1) CL= 50 pF, VCM = 1.5V 6 ns
tSK2 Skew, Pin to Pin (2) 6 ns
(1) tSK1 is the |tPHL – tPLH| of a channel.
(2) tSK2 is the maximum skew between any two channels within a device, either edge.
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SNLS128C –APRIL 1999–REVISED FEBRUARY 2013
PARAMETER MEASUREMENT INFORMATION
A. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Duty Cycle = 50%, ZO= 50Ω, tr≤10 ns, tf≤
10 ns.
B. CLincludes probe and jig capacitance.
Figure 2. Receiver Propagation Delay and Transition Time Test Circuit
A. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Duty Cycle = 50%, ZO= 50Ω, tr≤10 ns, tf≤
10 ns.
B. CLincludes probe and jig capacitance.
C. For military grade product, tr≤6ns and tf≤6ns.
D. For military grade product the measure point is 1/2 VCC for tPLH, tPHL, tPZL, and tPZH.
Figure 3. Receiver Propagation Delay and Transition Time Waveform
Figure 4. Receiver TRI-STATE Test Circuit
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A. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Duty Cycle = 50%, ZO= 50Ω, tr≤10 ns, tf≤
10 ns.
B. CLincludes probe and jig capacitance.
C. For military grade product, tr≤6ns and tf≤6ns.
D. For military grade product the measure point is 1/2 VCC for tPLH, tPHL, tPZL, and tPZH.
Figure 5. Receiver TRI-STATE Output Enable and Disable Waveforms
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SNLS128C –APRIL 1999–REVISED FEBRUARY 2013
TYPICAL APPLICATION INFORMATION
General application guidelines and hints for differential drivers and receivers may be found in the following
application notes:
• AN-214
• AN-457
• AN-805
• AN-847
• AN-903
• AN-912
• AN-916
Power Decoupling Recommendations:
Bypass caps must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1 μF in
parallel with 0.01 μF at the power supply pin. A 10 μF or greater solid tantalum or electrolytic should be
connected at the power entry point on the printed circuit board.
RTis optional although highly recommended to reduce reflection
Figure 6. Typical Receiver Connections
Figure 7. Typical Receiver Output Waveforms
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SNLS128C –APRIL 1999–REVISED FEBRUARY 2013
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Figure 8. Typical Receiver Input Circuit
Figure 9. Typical ICC vs Frequency
Figure 10. Receiver IIN vs VIN (Power On or Power Off)
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SNLS128C –APRIL 1999–REVISED FEBRUARY 2013
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REVISION HISTORY
Changes from Revision B (February 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS26LV32ATM/NOPB ACTIVE SOIC D 16 48 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS26LV32A
TM
DS26LV32ATMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS26LV32A
TM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS26LV32ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS26LV32ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2018
Pack Materials-Page 2
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