ANALOG DEVICES FEATURES Low Cost/Channel 32-Pin DIL Hybrid Package 2.6 Arc Minute Accuracy 14-Bit Resolution Built-In Test Independent Reference Inputs High Tracking Rate APPLICATIONS Gimbal/Gyro Control Systems Robotics Engine Controllers Coordinate Conversion Military Servo Control Systems Fire Control Systems Avionic Systems Antenna Monitoring CNC Machine Tooling GENERAL DESCRIPTION The AD2S44 series are 14-bit dual channel, continuous tracking synchro/resolver-to-digital converters. They have been designed specifically for applications where space, weight and cost are at a premium. Each 32-pin hybrid device contains two independent Type II servo loop tracking converters. The ratiometric conver- sion technique employed provides excellent noise immunity and tolerance of long lead lengths. The core of each conversion is performed by state-of-the-art monolithic integrated circuits manufactured in Analog Devices proprietary BiMOS II process which combines the advantages of low power CMOS digital logic with bipolar linear circuits. The use of these ICs keeps the internal component count low and ensures high reliability. The built-in test (BIT) facility can be used in failsafe systems to provide an indication of whether the converter is tracking accurately. Each channel incorporates a high accuracy differential condition- ing circuit for signal inputs providing more than 74 dB of com- mon mode rejection. Options are available for both synchro and resolver format inputs. The converter output is via a tristate transparent latch allowing data to be read without interruption of converter operation. The A/B and OE control lines select the Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Low Cost, 14-Bit, Dual Channel Synchro/Resolver-to-Digital Converter Pw fA] Fu (Al jeonor Me Sv iab a PHASE one EGRAI UrrDOr a2 TNCHERO Seo SENSITIVE a INT! non a z DETECTOR coun vy, 414A) ty or THIS TATE ourrur LATCHES: RESOLVERY SYNCHRO: sreeo ERROR sensve [ol swtegraton aeons SINrCOS er COUNTER MULTIPLIER . SARS f j REFERENCE Figure 1. Functional Block Diagram of AD2S44 channel and present the digital position to the common data outputs. The AD2S44 also features independent reference inputs. Conse- quently, different reference frequencies may be used for each channel. MODELS AVAILABLE The AD2S44 series is available in three accuracy grades: AD2S44UM = _14-Bits +4.0 Arc Mins 55C to +125C (+2.6 Arc Mins 25C to +85C ) AD2S44TM =14-Bits = +4.0 Arc Mins 55C to + 125C AD2S44SM _=:14-Bits = +5.2 Arc Mins 55C to +125C Each grade has options available which will interface to synchros and resolvers of standard voltage and frequency. All components are 100% tested at 55C, +25C, and +125C. Devices processed to high reliability screening standards (Suffix B) receive further levels of testing and screening to ensure high levels of reliability. Full ordering information is given on the back page of this data sheet. One Technology Way; P. O. Box 9106; Norwood, MA 02062-9106 U.S.A. Tel: 617/329-4700 Twx: 710/394-6577 Telex: 924491 Cables: ANALOG NORWOODMASSSPECIFICATIONS (typical at +25C unless specified otherwise) Parameter AD2S44 Units Comments PERFORMANCE Accuracy AD2S44UM +4.0 (max) Arc Min 55C to +125C +2.6 (max) Arc Min 25C to +85C AD2S844TM +4.0 (max) Arc Min 55C to +125C AD2S844SM +5,2 (max) Arc Min 55C to +125C Tracking Rate 20 rev/s Resolution 14 Bits Output Coding Parallel (1 LSB = 1.3 arc mins) Natural Binary Repeatability 1 LSB Signal/Reference Frequency 400-2600 Hz Bandwidth 100 Hz SIGNAL INPUTS Signal Voltage 2, 11.8, 26, 90 V rms See Ordering Information Input Impedance 90 V Signal 200 ko Resistive, Tolerance +2% 26 V Signal 58 kQ 11.8 V Signal 26 kQ 2 V Signal 4.4 kQ Common Mode Rejection 74 (min) dB Common Mode Range 90 V Signal +250 V de 26 V Signal +120 V de 11.8 V Signal +60 V de 2 V Signal +12 V de REFERENCE INPUTS Reference Voltage 2, 11.8, 26, 115 V rms See Ordering Information Input Impedance 115 V Reference 270 ko Resistive, Tolerance +5% 26 V Reference 270 kQ 11.8 V Reference 25 kO. 2 V Reference 25 kOQ Common Mode Range 115 V Reference +210 Vdc 26 V Reference +210 V de 11.8 V Reference +35 V de 2 V Reference +35 V de ACCELERATION CONSTANT 62000 sec?AD2S44 Parameter AD2S44 Units Comments STEP RESPONSE Large Step! 63 (typ), 75 (max) ms 179 to 1 LSB of Error Small Step! 25 (typ), 30 (max) ms 2 to 1 LSB of Error POWER LINES +V, = + 15V? 75 (typ), 80 (max) mA Quiescent Condition -V, = -15 yv} 40 (typ), 45 (max) mA Quiescent Condition Power Dissipation 1.7 (typ), 1.9 (max) Ww Quiescent Condition DIGITAL INPUTS OE Vir 0.7 (max) Vdc I = 5 pA Vi 2.0 (min) Vdc Ip = 5 pA AB Viz 0.7 (max) V de I, = 1.2mA Vie 2.0 (min) Vdc Ip = 60 pA DIGITAL OUTPUTS (DB1-DB14) Vou} 0.4 (max) Vde I = 1.2mA Vou 2.4 (min) Vdc Ton = 60 pA Tristate Leakage Current +40 pA Drive Capability 3 (max) LSTTL Loads DATA TRANSFER See Figure 3 Time to Data Stable (After Negative Edge of OE or Change of Level of A/B) 640 (max) ns ts Time to Data in High Impedance State (After Positive Edge of OE) 200 (max) ns tp Time for Repetitive Strobing of Selected Channel 200 (min) ns tp BUILT-IN TEST OUTPUT (BIT) Sense Active Low Low = Error Condition VoL 0.4 (max) Vdc Ior = 3.2 mA Vou 2.4 (min) V de Ion = 160 pA Drive Capability 8 (max) LSTTL Loads Error Condition Set 55 (max) LSB Error Condition Cleared 45 (min) LSB DIMENSIONS 1.74 x 1.14 x 0.28 inch See Package Information 44.2 x 28.9 x 7.1 mm WEIGHT 0.80 (max) Oz 23 (max) grams NOTES 'Specified over temperature range, 55C to +125C, and for: (a) +10% signal and reference amplitude variation; (b) + 10% signal and reference harmonic distortion; (c) +5% power supply variation; (d) +10% variation in reference frequency. Bold face type indicates parameters which are 100% tested at nominal values of power supplies, input signal voltages and operating frequency. All other para- maters are guaranteed by design, not tested. Specifications subject to change without notice. ORDERING INFORMATION AD2S4 XM ~T When ordering, the converter part numbers should be suffixed by a two letter code defining the accuracy grade, and a two digit numeric code defining the signal/reference voltage and frequency. All the standard options and their option codes are shown below. For nonstandard configurations, please contact Analog Devices. Base Part Number For example, the correct part number for a component to oper- ate with 90 V signal, 115 V reference synchro format inputs and yield a +5.2 arc minute accuracy over the 55C to +125 tem- perature range would be AD2S44SM12. The same part, pro- cessed to high reliability standards would carry the designator AD2S44SM12B. Y Zz B L High-Rel Processing Z = 0 Signal, 2 V Reference, 2 Resolver Z = 1 Signal, 11.8 V Reference 26 V Synchro Z = 2 Signal, 90 V Reference, 115 V Synchro Z = 3 Signal, 11.8 V Reference. 11.8 V Resolver Z = 4 Signal, 26 V Reference, 26 V Resolver Base Part Z = 8 Signal. 11.8 V Reference, 26 V Resolver Y = 1400 Hz to 2.6 kHz Reference Frequency X = U" 55C to +125C Operating Temperature Range +4.0 Are Min Accuracy ~2.6 Arc Min Accuracy (25C + 85C) XM = T" -$5C wo + 125C Operating Temperature Range + 4.0 Are Min Accuracy X = S" -55C to +125C Operating Temperature Range + 5.2 Are Min AccuracyABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION +V 480 GND ya corsues os pears Goes +17.25 V de =Vst0GND jsyesen os waynes oc sees 17.25 V de Any Logic Input to GND (max) ............. +6.0 V dc pes @ DB7 Any Logic Input to GND (min) ............. 0.4 V de pas} (2) @ | p86 Maximum Junction Temperature .............. +150C sro] (@) sad $1, $2, $3, $4 (Line to Line)! O0'W Opin: & av i SER Ewes BA RERSEES IG 3 +600 V de TO) @) | ves 26V Optlotis = ss: 5% Sees om wees ov gr 2 +160 V de per2| () pes L8V Optiotis. wacameas we ecm te Mec + 80 Vdc per3| G) @ | vee 2 VODHOON ole eteweeenecne eeeaneneecegny mete +14 V de S1, S2, $3, $4 to GND oi AD2s44 at 90 V-Option.. 3.23) 2 S88ie Se RO Bes +600 V de _ noe to Seelal 3 26 V Option. 4: 2% eves ea eet ws +160 V de ais} (@) Ve Te Optblbs peaernes oe perpen eae +80 V de arr @ | no PVOPHON es escewnie me eHow EN TEN +14 Vdc Rio (a)| (43) @) |R.018) Run t0 Rro Raa (A Ryu (B 26 V, 115 V Options ...........-..00-, +600 V de = S _ 2 V, 11.8 V Options .............0.2222. +50 V de Ry, Rio to GND $3 (A) $3 (8) 26 V5 V CDOMHe anew mx wena on i +600 V de s2(al| (5) $2 (B) 2 V; 11.8 V Options METAR. S54 WORMS Rca +50 V de $1 (A) @ $1 (B) Storage Temperature Range ........... 65C to +150C Operating Temperature Range .......... 55C to +125C NOTE 'On synchro input options, line-to-line voltage refers to the $2-S1, $1-S3 and $3-S2 differential voltages. On resolver input options line-to-line levels refer to the $1-S3 and $2-S4 voltages. CAUTION 1. Absolute maximum ratings are the limits beyond which A damage to the device may occur. Pin Mnemonic | Description = / 2. Correct polarity voltages must be maintained on the +Vg and 17 DB8-DB14__ Parallel Output Data Bits Vs pins. 26-32 | DBI-DB7 | Parallel Output Data Bits 3. The +15 V power supply must never go below GND. 8 OE | Output Enable Input 9 AB | Channel A or B Select Input Bit Number Weight (Degrees) 10 BIT | pea Test Error Output 1 (MSB) T 180.0000 ll Ryo (A) | Input Pin for Channel A Reference Low 2 90.0000 12 Ry (A) | Input Pin for Channel A Reference High 3 | 45.0000 13-16 | S4-S1(A) | Channel A Input Signal 4 | 22.5000 j 5 11.2500 17-20 | S1-S4 (B) Channel B Input Signal 6 5.6250 21 Ry (B) Input Pin for Channel B Reference High f Poe 22 | Ryo BB) | Input Pin for Channel B Reference Low 9 | 0.7031 23 | GND | Power Supply Ground (Note: This Pin Is 10 | 0.3516 | | Electrically Connected to the Case.) 11 | 0.1758 24 -Vs | Negative Power Supply a | eK 25 +V>5 | Positive Power Supply _ 14 (LSB for 2544) 0.0220 NT ee Table |. Bit Weight Table ESD SENSITIVITY The AD2S44 features input protection circuitry consisting of large distributed diodes rT ARNIN rey] and polysilicon series resistors to dissipate both high energy discharges (Human Body . Model) and fast, low energy pulses (Charged Device Model). J Proper ESD precautions are strongly recommended to avoid functional damage or perfor- i mance degradation. For further information on ESD precautions, refer to Analog Devices ESD Prevention Manual. ESD SENSITIVE DEVICERy (A) REFERENCE Rio (A) CONDITIONER | +V5 $1 (A) Vi] HIGH PHASE GND $< 82 1A) RESOLVER/ ERROR SENSITIVE | INTEGRATOR | vco }e| UP/DOWN $3 (A) CONDITIONER |__,] MULTIPLIER salad -V, $4 (A) V, : *) BIT y AIB TRISTATE OE AD2S44 IN TEST sents DETECTION DB1 mM, ! tt io! O ps4 $1 (B) RESOLVER/ fF HIGH $2 (8) SYNCHRO SPEED PHASE UP/DOWN 53 [B) Seaman aon ERROR SENSITIVE |e] INTEGRATOR |e vco | UP/DOWN ce) 2] SINICOS AMP. DETECTOR Ry (B) REFERENCE | Rio (B) CONDITIONER Figure 1. Functional Block Diagram of AD2S44 PRINCIPLES OF OPERATION The AD2S44 series operate on a tracking principle. The output digital word continually tracks the position of the resolver/syn- chro shaft without the need for external convert commands and status wait loops. As the transducer moves through a position equivalent to the least significant bit weighting, the output digi- tal word is updated. A functional diagram of the AD2S44 is shown in Figure 1. Each channel is identical in operation, sharing power supply and output pins. Both channels operate continuously and indepen- dently of each other-the digital output from either channel is available after switching the channel select and output enable inputs. If the device is a synchro-to-digital converter, the 3-wire synchro output will be connected to $1, $2 and $3 on the unit, and a solid-state Scott-T input conditioner will convert these signals into resolver format, i.e., V,=K Ep sin wrt sin 6 V2=K Eo sin wt cos 6 Where 6 is the angle of the synchro shaft, Ep sin wt is the refer- ence signal and K is the transformation ratio of the the input signal conditioner. If the unit is a resolver-to digital converter, the 4-wire resolver output will be connected directly to $1, $2, $3 and $4 on the unit. To understand the conversion process, assume that the current word state of the up-down counter is . V, is multiplied by cosh and V, is multiplied by sind to give: K Ep sin wrt sin 0 cos b K Ep sin wrt cos 6 sin ob. These signals are subtracted by the error amplifier to give: K Eg sin wr (sin 6 cos b cos 0 sin ob) or K Eg sin wrt sin (0-o). A phase sensitive detector, integrator and voltage controlled oscillator (VCO) form a closed loop system which seeks to null sin (@). When this is accomplished, the word state of the up- down counter, @, equals, to within the rated accuracy of the converter, the synchro-resolver shaft angle, 6. CONNECTING THE CONVERTER The power supply voltages connected to V, and +Vg, pins should be +15 V and must not be reversed. It is suggested that a parallel combination of a 100 nF (ceramic) and a 6.8 wF (tantalum) capacitor be placed from each of the supply pins to GND. The pin marked GND is connected electrically to the case and should be taken to the zero volt potential in the system. The digital output is taken from Pins 26-32 and Pins 1-7. Pin 26 is the MSB, Pin 7 the LSB. The reference connections are made to REF HI and REF LO. In the case of a synchro, the signals are connected to $1, $2 and $3 according to the following convention: Esj_s3 = ERzio-rHr sin wt sin 6 Es3-52 = ERto-RHI sin wt sin (6-120) Es52-s1 = EpRto-RHI sin wt sin (0-240). For a resolver, the signals are connected to $1, $2, $3 and $4 according to the following convention: Esi_s3 = Errto-RHI sin wrt sin 6 Es2-s4 = Erto-rur sin wr cos 0CHANNEL SELECT (A/B) AIB is the channel select input. A logic high selects channel A and a logic low selects channel B. Data becomes valid 640 ns after A/B is toggled. Timing information is shown in Figure 2. OUTPUT ENABLE (OE) OE is the output enable input; the signal is active low. When set to a logic high, DB] to DB14 are in the high impedance state. When OE is set to logic low, DB1 to DB14 represent the angle of the transducer shaft (see bit weights in Table I) to within the stated accuracy of the converter. Data becomes valid 640 ns after the OE is switched. Timing information is shown in Figure 2 and detailed in the Data Transfer section of SPECIFICATIONS. DATA BITS *NOTE CONVERTER DATA OUTPUT IS INHIBITED FROM UPDATES DURING DATA VALID. a. Repetitive Reading of One Channel ae tS W *NOTE CONVERTER DATA OUTPUT IS INHIBITED FROM UPDATES DURING CHANNEL VALID CHANNEL B VALID* CHANNEL A VALID* b. Alternate Reading of Each Channel Figure 2. AD2S44 Timing Diagrams BUILT-IN TEST (BIT) BIT is the built-in test error output. This provides an over velocity or fault indication signal for the channel selected via A/B. The error voltage of each channel is continuously moni- tored; and when the error exceeds +50 bits for the currently selected channel, the BIT output goes low indicating that an error greater than approximately 1 angular degree exists and that the data is therefore invalid. The BIT signal has a built-in hysterisis, i.e., the error required to set BIT is greater than that required for it to be cleared. BIT is set when the error exceeds 55 LSBs and is cleared when the error goes below 45 LSBs. This mode of operation guarantees that BIT will not flicker when the error threshold is crossed. BIT is valid for the selected channel approximately 50 ns after the change in state of A/B. In most instances, the error condi- tion which sets BIT must persist for at least 1 period of the ref- erence signal prior to BIT responding to the condition. Conditions which cause the BIT output to show a fault are: 1. Power-Up Transient Response BIT will return to a logic high state after the AD2S44 posi- tion output synchronizes with the angle input to within 1 degree. Normally, BIT will be low at power-up for a period less than or equal to the large signal step response set- ting time of the AD2S44 after the +V., supplies have stabi- lized to within 5% of their final values. 2. Step Input > 1 Degree BIT will return to a logic high state after the selected channel of the AD2S44 has settled to with 1 degree of the input angle resulting from an instantaneous step. 3. Excessive Velocity BIT will be driven to a logic low if the maximum tracking rate of the AD2S44 is exceeded (20 RPS typical). Signal Failure BIT may be driven to a logic low state if all signal voltages to the selected channel are lost. 5. Converter/System Failure Any failure which causes the AD2S44 to fail to track the input synchro/resolver angles will drive BIT to a logic low. This may include, but is not necessarily limited to, accelera- tion conditions, poor supply voltage regulation or excessive noise on the signal connections. SCALING FOR NONSTANDARD SIGNALS A feature of these converters is that the signal and reference inputs can be resistively scaled to accommodate nonstandard input signal and reference voltages which are outside the nomi- nal +10% limits of the converter. Using this technique, it is possible to use a standard converter with a personality card in systems where a wide range of input and reference voltages are encountered. NOTE: The accuracy of the converter will be affected by the matching accuracies of resistors used for external scaling. For resolver format options, it is critical that the value of the resis- tors on the $1-S3 signal input pair be precisely matched to the $4-S82 input pair. For synchro options, the three resistors on $1, $2, $3 must be matched. In general, a 0.1% mismatch between resistor values will contribute an additional 1.7 arc minutes of error to the conversion. In addition, imbalances in resistor val- ues can greatly reduce the common mode rejection ratio of the signal inputs. To calculate the values of the external scaling resistors add 2.222 kQ extra per volt of signal in series with $1, $2, $3 and S4 (no resistor required on $4 for synchro options), and 3 kQ in extra per volt of reference in series with Ryo and Ry. DYNAMIC PERFORMANCE The transfer function of the converter is given below. On 9out Tv K, s? 1+ sT; 1+ sT2 Figure 3. Transfer Function of AD2S44Open loop transfer function: Sour = Ka 1+ sT, 6mN s? 1 + sT3 Closed loop transfer function: 8ouT _ 1+ sT 8m 1 + sT, + s/K, + 8 To/K,g where K, = 62000 sec? T, = 0.0061 sec T, = 0.001 sec. The gain and phase diagrams are shown in Figures 4 and 5. +6 +3 3-37 ' = & -6 -9 -- = -12 -15 10 100 FREQUENCY - Hz Figure 4. AD2S44 Gain Plot +180 | +135 } 1 - it 4 +90 +45 wi a 0 = a 45 =-90 = -135 -180 10 100 FREQUENCY Hz Figure 5. AD2S44 Phase Plot ACCELERATION ERROR A tracking converter employing a Type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant K, of the converter. __ Input Acceleration ~ Error in Output Angle a The numerator and denominator must have consistant angular units. For example, if K, is in sec~, then the input acceleration may be specified in degrees/sec and the error in output angle in degrees. Alternatively, the angular unit of measure may be in radians, minutes of arc, LSBs, etc. K, does not define maximum acceleration, only the error due to acceleration. The maximum acceleration for which the AD2S44 will not lose track is on the order of 5 x K, = 310,000 /sec? or about 800 revolutions/sec. K, can be used to predict the output position error due to input acceleration. For eaxample, for an acceleration of 50 revolutions/ sec with K, = 62000, Input ceSesiet [LSB/sec?] K, [sec] 50 [rev/sec?] - 2!4 [LSB/rev] = 62000 [sec] = 13.2 LSBs. RELIABILITY The reliability of these products is very high due to the exten- sive use of custom chip circuits that decrease the active compo- nent count. Calculations of the MTBF figure under various environmental conditions are available on request. Figure 6 shows the MTBF in years vs. case temperature for Naval Sheltered conditions calculated in accordance with MIL- HDBK-217E. 100 5 2 it 10 }- 5 1 i | | | 25 45 65 85 105 125 TEMPERATURE *C Figure 6. 2544 MTBF vs. Temperature STANDARD PROCESSING As part of the standard manufacturing procedure, all converters receive the following processing: Conditions 64 Hours at +125C In-House Criteria Process 1. Preseal Burn In 2. Precap Visual Inspection 3. Seal Test, Fine and Gross In-House Criteria 4. Final Electrical Test Performed at T,in> Trnaxs Tam:PROCESSING FOR HIGH RELIABILITY (B SUFFIX) Process 1. Preseal Burn In 2. Precap Visual Inspection 3. Temperature Cycling Constant Acceleration Interim Electrical Tests Operating Burn In Seal Test, Fine and Gross oy, ee 8. Final Electrical Testing (Group A) 9. External Visual Inspection Conditions 64 Hours at + 125C MIL-STD-883C, Method 2017 10 Cycles, 65C to +150C 5000G, Y1 Plane 96 Hours @ +125C MIL-STD-883C, Method 1014 Performed at Tins Tamb and Tax MIL-STD-883C, Method 2009 NOTE: Test and screening data can be supplied. Further infor- mation on request. OTHER PRODUCTS Many other products concerned with the conversion of synchro/ resolver data are manufactured by Analog Devices, some of which are listed below. The SDC/RDC1740/41/42 are hybrid synchro/resolver to digital converters with internal isolating micro transformers. The SDC/RDC1767/68 are identical to the SDC/RDC1740 series but with the additional features of analog velocity output and dc error output. The OSC1758 is a hybrid sine/cosine power oscillator which can provide a maximum power output of 1.5 watts. The device operates over a frequency range of 1 kHz to 10 kHz. The DRC1745 and DRC1746 are 14- and 16-bit natural binary latched output high power hybrid digital-to-resolver converters. The accuracies available are +2 and +4 arc minutes, and the outputs can supply 2 VA at 7 V rms. Transformers are available to convert the output to synchro or resolver format at high volt- age levels. The AD2S65/66 are similar to the DRC1745/46 but do not include the power output stage. These devices are available in accuracy grades to | arc minute. The 2880 series are monolithic ICs performing resolver to digital conversion with accuracies up to +2 arc minutes and 16-bit resolution. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). ANALOG DEVICES MEMORY DEVICES DIVN. MADE IN ENGLAND AD2S44 OPTION ETT7F 0.28+0.010 \_ ieee PIN 1 IDENTIFIER Ae 0.2 +0.010 (5.0 0,254) al L ot a TYP e___1 snore | L fe 1.74 (44.2) = PIN 1 BEAD DIFFERENT COLOR 0.600 (15.24) BOTTOM VIEW +-O 1.400 (35.56) @eeeceeseeeecene orm T+ + 0.9 (22.9) | (0.635) (GLASS BEAD STANDOFFS 0.08 DIA. +0.010 (2.03 DIA, +0254) 1.14 (29.0) TOLERANCES: +0.005 (+0.127) UNLESS OTHERWISE STATED C1351-24-10/89 PRINTED IN U.S.A.