74LVX3245WM - FAIRCHILD SEMICONDUCTOR

February 2010

74LVX3245

8-Bit Dual Supply Translating Transceiver with

3-STATE Outputs

General Description

The LVX3245 is a dual-supply, 8-bit translating transceiver

that is designed to interface between a 3V bus and a 5V

bus in a mixed 3V/5V supply environment. The Transmit/

Receive (T/R) input determines the direction of data flow.

Transmit (active-HIGH) enables data from A Ports to B

Ports; Receive (active-LOW) enables data from B Ports to

A Ports. The Output Enable input, when HIGH, disables

both A and B Ports by placing them in a high impedance

condition. The A Port interfaces with the 3V bus; the B Port

interfaces with the 5V bus.

The LVX3245 is suitable for mixed voltage applications

such as notebook computers using 3.3V CPU and 5V

peripheral components.

Features

■Bidirectional interface between 3V and 5V buses

■Inputs compatible with TTL level

■3V data flow at A Port and 5V data flow at B Port

■Outputs source/sink 24 mA

■Guaranteed simultaneous switching noise level and

dynamic threshold performance

■Implements proprietary EMI reduction circuitry

■Functionally compatible with the 74 series 245

Ordering Code:

Order Number Package Number Package Description

74LVX3245WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVX3245QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

74LVX3245MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol/s

Pin Descriptions

Pin Names Description

OE Output Enable Input

T/RTransmit/Receive Input

A0–A7Side A Inputs or 3-STATE Outputs

B0–B7Side B Inputs or 3-STATE Outputs

Connection Diagram/s

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Truth Table/s

Inputs Outputs

OE T/R

L L Bus B Data to Bus A

L H Bus A Data to Bus B

H X HIGH-Z State

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Logic Diagram/s

3 www.fairchildsemi.com

Absolute Maximum Ratings(Note 1)

Supply Voltage (VCCA, VCCB)−0.5V to +7.0V

DC Input Voltage (VI) @ OE, T/R−0.5V to VCCA + 0.5V

DC Input/Output Voltage (VI/O)

@ An−0.5V to VCCA + 0.5V

@ Bn−0.5V to VCCB + 0.5V

DC Input Diode Current (IIN)

@ OE, T/R±20 mA

DC Output Diode Current (IOK)±50 mA

DC Output Source or

Sink Current (IO)±50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)±50 mA

and Max Current @ ICCA ±100 mA

@ ICCB ±200 mA

Storage Temperature Range (TSTG)−65°C to +150°C

DC Latch-Up Source or

Sink Current ±300 mA

Maximum Junction Temperature

Under Bias (TJ)+150°C

Recommended Operating

Conditions (Note 2)

Supply Voltage

VCCA 2.7V to 3.6V

VCCB 4.5V to 5.5V

Input Voltage (VI) @ OE, T/R0V to VCCA

Input/Output Voltage (VI/O)

@ An0V to VCCA

@ Bn0V to VCCB

Free Air Operating Temperature (TA)−40°C to

+85°C

Minimum Input Edge Rate (Δt/ΔV) 8 ns/V

VIN from 30% to 70% of VCC

VCC @ 3.0V, 4.5V, 5.5V

Note 1: The “Absolute Maximum Ratings” are those values beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Recommended Operating Conditions” table will define the conditions

for actual device operation.

Note 2: Unused Pins (inputs and I/Os) must be held HIGH or LOW. They

may not float.

DC Electrical Characteristics

Symbol Parameter VCCA VCCB TA = +25°C TA = −40°C to +85°CUnits Conditions

(V) (V) Typ Guaranteed Limits

VIHA Minimum HIGH Level An, T/R, 3.6 5.0 2.0 2.0

Input Voltage OE 2.7 5.0 2.0 2.0 VOUT ≤ 0.1V or

VIHB Bn3.3 4.5 2.0 2.0 ≥ VCC − 0.1V

3.3 5.5 2.0 2.0

VILA Maximum LOW Level An, T/R, 3.6 5.0 0.8 0.8

Input Voltage OE 2.7 5.0 0.8 0.8 VOUT ≤ 0.1V or

VILB Bn3.3 4.5 0.8 0.8 ≥ VCC −0.1V

3.3 5.5 0.8 0.8

VOHA Minimum HIGH Level 3.0 4.5 2.99 2.9 2.9

IOUT = −100 μA

Output Voltage 3.0 4.5 2.65 2.35 2.25 IOH = −24 mA

2.7 4.5 2.5 2.3 2.2 IOH = −12 mA

2.7 4.5 2.3 2.1 2.0 IOH = −24 mA

VOHB 3.0 4.5 4.5 4.4 4.4 VIOUT = −100 μA

3.0 4.5 4.25 3.86 3.76 IOH = −24 mA

VOLA Maximum LOW Level 3.0 4.5 0.002 0.1 0.1

IOUT =100 μA

Output Voltage 3.0 4.5 0.21 0.36 0.44 IOL = 24 mA

2.7 4.5 0.11 0.36 0.44 IOL = 12 mA

2.7 4.5 0.22 0.42 0.5 IOL = 24 mA

VOLB 3.0 4.5 0.002 0.1 0.1 VIOUT = 100 μA

3.0 4.5 0.18 0.36 0.44 IOL = 24 mA

IIN Maximum Input

Leakage Current 3.6 5.5 ±0.1 ±1.0 μA VI = VCCB, GND

@ OE, T/R

IOZA Maximum 3-STATE VI = VIL, VIH

Output Leakage 3.6 5.5 ±0.5 ±5.0 μAOE = VCCA

@ AnVO = VCCA, GND

IOZB Maximum 3-STATE VI = VIL, VIH

Output Leakage 3.6 5.5 ±0.5 ±5.0 μAOE = VCCA

@ BnVO = VCCB, GND

www.fairchildsemi.com 4

Note 3: Worst case package.

Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND.

Note 5: Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to VCC level. Input-under-test switching:

VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1 MHz.

AC Electrical Characteristics

Symbol Parameters

TA = +25°C TA = −40°C to +85°C TA = −40°C to +85°C

Units

CL = 50 pF CL = 50 pF CL = 50 pF

VCCA = 3.3V (Note 6) VCCA = 3.3V (Note 6) VCCA = 2.7V

VCCB = 5.0V (Note 7) VCCB = 5.0V (Note 7) VCCB = 5.0V (Note 7)

Min Typ Max Min Max Min Max

tPHL Propagation Delay 1.0 5.4 8.0 1.0 8.5 1.0 9.0 ns

tPLH A to B 1.0 5.6 7.5 1.0 8.0 1.0 8.5

tPHL Propagation Delay 1.0 5.1 7.5 1.0 8.0 1.0 8.5 ns

tPLH B to A 1.0 5.7 7.5 1.0 8.0 1.0 8.5

tPZL Output Enable 1.0 4.8 8.0 1.0 8.5 1.0 9.0 ns

tPZH Time OE to B 1.0 6.3 8.5 1.0 9.0 1.0 9.5

tPZL Output Enable 1.0 6.3 8.5 1.0 9.0 1.0 9.5 ns

tPZH Time OE to A 1.0 6.8 9.0 1.0 9.5 1.0 10.0

tPHZ Output Disable 1.0 5.3 7.5 1.0 8.0 1.0 8.5 ns

tPLZ Time OE to B 1.0 4.2 7.0 1.0 7.5 1.0 8.0

tPHZ Output Disable 1.0 5.3 8.0 1.0 8.5 1.0 9.0 ns

tPLZ Time OE to A 1.0 3.7 6.5 1.0 7.0 1.0 7.5

tOSHL Output to Output

tOSLH Skew (Note 8) 1.0 1.5 1.5 1.5 ns

Data to Output

Note 6: Voltage Range 3.3V is 3.3V ± 0.3V.

Note 7: Voltage Range 5.0V is 5.0V ± 0.5V.

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.

ΔICC Maximum Bn3.6 5.5 1.0 1.35 1.5 mA VI = VCCB − 2.1V

ICCT/Input @ An, T/R, 3.6 5.5 0.35 0.5 mA VI = VCCA −0.6V

ICCA Quiescent VCCA An = VCCA or GND

Supply Current 3.6 5.5 550 μA Bn = VCCB or GND,

OE = GND, T/R = GND

ICCB Quiescent VCCB An = VCCA or GND

Supply Current 3.6 5.5 880 μA Bn = VCCB or GND,

OE = GND, T/R = VCCA

VOLPA Quiet Output Maximum 3.3 5.0 0.8 V(Note 3) (Note 4)

VOLPB Dynamic VOL 3.3 5.0 1.5

VOLVA Quiet Output Minimum 3.3 5.0 −0.8 V(Note 3) (Note 4)

VOLVB Dynamic VOL 3.3 5.0 −1.2

VIHDA Minimum HIGH Level 3.3 5.0 2.0 V(Note 3) (Note 5)

VIHDB Dynamic Input Voltage 3.3 5.0 2.0

VILDA Maximum LOW Level 3.3 5.0 0.8 V(Note 3) (Note 5)

VILDB Dynamic Input Voltage 3.3 5.0 0.8

Symbol Parameter VCCA VCCB TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) (V) Typ Guaranteed Limits

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Capacitance

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC = Open

CI/O Input/Output 15 pF VCCA = 3.3V

Capacitance VCCB = 5.0V

CPD Power Dissipation A → B 55 pF VCCB = 5.0V

Capacitance (Note 9) B → A 40 VCCA = 3.3V

Note 9: CPD is measured at 10 MHz

8-Bit Dual Supply Translating Transceiver

The LVX3245 is a dual supply device capable of bidirec-

tional signal translation. This level shifting ability provides

an efficient interface between low voltage CPU local bus

with memory and a standard bus defined by 5V I/O levels.

The device control inputs can be controlled by either the

low voltage CPU and core logic or a bus arbitrator with 5V

I/O levels.

Manufactured on a sub-micron CMOS process, the

LVX3245 is ideal for mixed voltage applications such as

notebook computers using 3.3V CPU's and 5V peripheral

devices.

Power Up Considerations

To insure that the system does not experience unneces-

sary ICC current draw, bus contention, or oscillations during

power up, the following guidelines should be adhered to

(refer to Tab l e 1 ):

• Power up the control side of the device first. This is the

VCCA.

•OE should ramp with or ahead of VCCA. This will help

guard against bus contention.

• The Transmit/Receive control pin (T/R) should ramp with

VCCA, this will ensure that the A Port data pins are con-

figured as inputs. With VCCA receiving power first, the A

I/O Port should be configured as inputs to help guard

against bus contention and oscillations.

• A side data inputs should be driven to a valid logic level.

This will prevent excessive current draw.

The above steps will ensure that no bus contention or oscil-

lations, and therefore no excessive current draw occurs

during the power up cycling of these devices. These steps

will help prevent possible damage to the translator devices

and potential damage to other system components.

TABLE 1. Low Voltage Translator Power Up Sequencing Table

Device Type VCCA VCCB T/ROE A Side I/O B Side I/O Floatable Pin

Allowed

74LVX3245 3V 5V ramp ramp logic outputs No

(power up 1st) configurable with VCCA with VCCA 0V or VCCA

Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual

Supply CMOS Translating Transceivers.

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Physical Dimensions

2.65 MAX

0.20±0.10

0.10 C

15.40±0.20 A

SEE DETAIL A

0.33

0.20

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS P ACKAGE CONFO RMS TO JED EC

MS-013, ISSUE E, DATED SEPT 2005.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BU RRS.

D) LANDPATERN STANDARD: SOIC127P1030X265-24L

PIN ONE

INDICATOR

10.325

24 13

13.970

7.50±0.10

X 45°

0.75

0.25

(R0.10)

0.40~1.27

8°

0°

SEATING PLANE

(1.40)

0.25

GAGE PLANE

DETAIL A

SCALE: 2:1

SEATING PLANE

112

0.25

0.51

0.35

BCA

1.27

LAND PATTERN RECOMMENDATION

14.52

1.27 TYP

0.55 TYP

1.75 TYP

9.2

10.95

E) DRAWING FILENAME: MKT-M24BREV2

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may

change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fair-

child Semiconductor representative to verify or obtain the most recent revision. Package specifications do not

expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

.635

D. DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS

C. DRAWING CONFORMS TO

ASME Y14.5M-1994

B. ALL DIMENSIONS ARE IN MILLIMETERS

A. TH IS PACKAG E CONFORMS TO

JEDEC M0-137 VARIATION AE

NOTES :

SIDE VIEW

TOP VIEW

SEATING PLANE

GAGE PLANE

DETAIL A

END VIEW

LAND PATTERN

RECOMMENDATION

24 13

3.99

3.84 6

2X 12 TIPS

0.635

1.49

1.39

1.73 MAX

0.10 A-B

0.20 C

0.161

0.061

0.178 C A-B D

24X 0.3

0.2

0.203

0.101

E. LAND PATTERN STANDARD: SOP63P600X175-24M

F. DRAWING FILE NAME: MKT-MQA24REV2

5.60

1.75

0.4

8.74

8.59

0.71

0.61 45°

8°

2°

0.61

0.71

R0.008

0 MIN

0.254

(0.695)

7 www.fairchildsemi.com

24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings

may change in any manner without notice. Please note the revision and/or date on the drawing and con-

tact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifi-

cations do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

DATE 10/97.

MTC24REV4

112

24 13

ADETAIL

12° TOP & BOTTOM

0.75

0.45

8°

0°-

112

R0.09MIN

(1.00)

0.65 TYP

0.20 CBA

0.10 C B Z

0.10 C

7.8±0.1

0.20 TYP

(4.45)

(7.35)

(1.45)

6.4

3.2

4.4±0.1

5.9

0.65

www.fairchildsemi.com 8

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may

change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fair-

child Semiconductor representative to verify or obtain the most recent revision. Package specifications do not

expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

9 www.fairchildsemi.com