Low Capacitance, Low Charge Injection,
±15 V/+12 V iCMOS SPST in SOT-23
ADG1201/ADG1202
Rev. 0
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Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
2.4 pF off capacitance
<1 pC charge injection
Low leakage; 0.6 nA maximum @ 85°C
120 Ω on resistance
Fully specified at ±15 V, +12 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
6-lead SOT-23 package
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
FUNCTIONAL BLOCK DIAGRAM
ADG1201
SD
IN
ADG1202
SD
IN
SWITCHES SHOWN FOR A LOGIC “1” INPUT
06576-001
Figure 1.
GENERAL DESCRIPTION
The ADG1201/ADG1202 are monolithic complementary
metal-oxide semiconductor (CMOS) devices containing
an SPST switch designed in an iCMOS® (industrial CMOS)
process. iCMOS is a modular manufacturing process
combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high perform-
ance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts has been
able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high
supply voltages while providing increased performance,
dramatically lower power consumption, and reduced
package size.
The ultralow capacitance and charge injection of these
switches make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Fast switching speed coupled with
high signal bandwidth make the parts suitable for video
signal switching.
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
The ADG1201/ADG1202 contain a single-pole/single-throw
(SPST) switch. Figure 1 shows that with a logic input of 1, the
switch of the ADG1201 is closed and that of the ADG1202 is
open. Each switch conducts equally well in both directions when
on and has an input signal range that extends to the supplies. In
the off condition, signal levels up to the supplies are blocked.
PRODUCT HIGHLIGHTS
1. Ultralow capacitance.
2. <1 pC charge injection.
3. Ultralow leakage.
4. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
5. No VL logic power supply required.
6. SOT-23 package.
ADG1201/ADG1202
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions ..............................6
Typical Performance Characteristics ..............................................7
Test Circuits ..................................................................................... 10
Terminology .................................................................................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
2/08—Revision 0: Initial Version
ADG1201/ADG1202
Rev. 0 | Page 3 of 16
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
B Version1
Parameter 25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 120 Ω typ VDD = +13.5 V, VSS = −13.5 V
200 240 270 Ω max VS = ±10 V, IS = −1 mA; see Figure 20
On Resistance Flatness (RFLAT(ON)) 20 Ω typ VS = −5 V, 0 V, and +5 V; IS = −1 mA
60 72 79 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.004 nA typ VS = ±10 V, VD = ±10 V; see Figure 21
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.004 nA typ VS = ±10 V, VD = ±10 V; see Figure 21
±0.1 ±0.6 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = ±10 V; see Figure 22
±0.15 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH
±0.1 μA max
Digital Input Capacitance, CIN 2.5 pF typ
DYNAMIC CHARACTERISTICS2
tON 140 ns typ RL = 300 Ω, CL = 35 pF
170 200 230 ns max VS = 10 V; see Figure 26
tOFF 90 ns typ RL = 300 Ω, CL = 35 pF
105 130 141 ns max VS = 10 V; see Figure 26
Charge Injection −0.8 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27
Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 23
Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz
−3 dB Bandwidth 660 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 24
CS (Off) 2.4 pF typ VS = 0 V, f = 1 MHz
3 pF max VS = 0 V, f = 1 MHz
CD (Off) 2.8 pF typ VS = 0 V, f = 1 MHz
3.3 pF max VS = 0 V, f = 1 MHz
CD, CS (On) 4.7 pF typ VS = 0 V, f = 1 MHz
5.6 pF max VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1.0 μA max
IDD 60 μA typ Digital inputs = 5 V
95 μA max
ISS 0.001 μA typ Digital inputs = 0 V, 5 V or VDD
1.0 μA max
VDD/VSS ±5 to ±16.5 V min/max GND = 0 V
1 Temperature range for B version is 40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG1201/ADG1202
Rev. 0 | Page 4 of 16
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
B Version1
Parameter 25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 300 Ω typ VDD = 10.8 V, VSS = 0 V
475 567 625 Ω max VS = 0 V to 10 V, IS = −1 mA; see Figure 20
On Resistance Flatness (RFLAT(ON)) 60 Ω typ VS = 3 V, 6 V, and 9 V, IS = −1 mA
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.006 nA typ VS = 1 V or 10 V, VD = 10 V or 1 V; see Figure 21
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.006 nA typ VS = 1 V or 10 V, VD = 10 V or 1 V; see Figure 21
±0.1 ±0.6 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = 1 V or 10 V; see Figure 22
±0.15 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 μA typ VIN = VINL or VINH
±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS2
tON 190 ns typ RL = 300 Ω, CL = 35 pF
250 295 340 ns max VS = 8 V; see Figure 26
tOFF 120 ns typ RL = 300 Ω, CL = 35 pF
155 190 210 ns max VS = 8 V; see Figure 26
Charge Injection 0.8 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 27
Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 23
−3 dB Bandwidth 520 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 24
CS (Off) 2.7 pF typ VS = 6 V, f = 1 MHz
3.3 pF max VS = 6 V, f = 1 MHz
CD (Off) 3.1 pF typ VS = 6 V, f = 1 MHz
3.6 pF max VS = 6 V, f = 1 MHz
CD, CS (On) 5.3 pF typ VS = 6 V, f = 1 MHz
6.3 pF max VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1.0 μA max
IDD 60 μA typ Digital inputs = 5 V
95 μA max
VDD +5/+16.5 V min/max VSS = 0 V, GND = 0 V
1 Temperature range for B version is 40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG1201/ADG1202
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs1 VSS – 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1 GND – 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, S or D 100 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current per
Channel, S or D
30 mA
Operating Temperature Range −40°C to +125°C
Industrial (B Version)
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
6 Lead SOT-23
θJA,Thermal Impedance 229.6°C/W
θJC, Thermal Impedance 91.99°C/W
Reflow Soldering Peak
Temperature, Pb-free
260°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADG1201/ADG1202
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06576-002
V
DD 1
GND
2
V
SS 3
IN
6
D
5
S
4
ADG1201/
ADG1202
TOP VIEW
(Not to Scale)
Figure 2. SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 GND Ground (0 V) Reference.
3 VSS Most Negative Power Supply Potential.
4 S Source Terminal. Can be an input or output.
5 D Drain Terminal. Can be an input or output.
6 IN Logic Control Input.
Table 5. ADG1201/ADG1202 Truth Table
ADG1201 IN ADG1202 IN Switch Condition
1 0 On
0 1 Off
ADG1201/ADG1202
Rev. 0 | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
V
DD
= +15V
V
SS
= –15V
V
DD
= +16.5V
V
SS
= –16.5V
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE ()
200
180
160
140
120
100
60
80
0
20
40
–18 –15 –12 –9 –6 –3 3 9 15061218
06576-003
V
DD
= +13.5V
V
SS
= –13.5V
T
A
= +25ºC
Figure 3. On Resistance as a Function of VD (VS) for Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE ()
450
400
350
300
250
150
200
0
50
100
–5 –4 –3 –2 –1 2 401 3 5
06576-004
V
DD
= +5.5V
V
SS
= –5.5V
T
A
= +25°C
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
V
DD
= 13.2V
V
SS
= 0V
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE ()
450
400
350
300
250
150
200
0
50
100
024681012
06576-005
V
DD
= 12V
V
SS
= 0V
V
DD
= 10.8V
V
SS
= 0V
T
A
= 25°C
Figure 5. On Resistance as a Function of VD (VS) for Single Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE ()
250
150
200
0
50
100
–15 –10 –5 0 5 10 15
06576-006
V
DD
= +15V
V
SS
= –15V
T
A
= +125°C
T
A
= +25°C
T
A
= +85°C
T
A
= –40°C
Figure 6. On Resistance as a Function of VD (VS) for Different
Temperatures, Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE ()
600
400
500
300
200
0
100
024681012
06576-007
V
DD
= +12V
V
SS
= 0V
T
A
= +125°C
T
A
= +25°C
T
A
= +85°C
T
A
= –40°C
Figure 7. On Resistance as a Function of VD (VS) for Different
Temperatures, Single Supply
LEAKAGE CURRENT (pA)
0
–450
–400
080
06576-028
200
150
100
50
–50
–100
–150
–200
–250
–300
–350
20 40 60 100 120
V
DD
= +15V
V
SS
= –15V
V
BIAS
= ±10V
TEMPERATURE (ºC)
I
S
(OFF) + – I
D
(OFF) + –
I
S
(OFF) – + I
D
(OFF) – +
I
D
, I
S
(ON) + + I
D
, I
S
(ON) – –
Figure 8. Leakage Currents as a Function of Temperature, Dual Supply
ADG1201/ADG1202
Rev. 0 | Page 8 of 16
LEAKAGE CURRENT (pA)
0
–250
100
080
06576-026
150
–50
–100
–150
–200
50
20 40 60 100 120
TEMPERATURE (ºC)
I
S
(OFF) + – I
D
(OFF) + –
I
S
(OFF) – + I
D
(OFF) – +
I
D
, I
S
(ON) + + I
D
, I
S
(ON) – –
V
DD
= +5V
V
SS
= –5V
V
BIAS
= ±4.5V
Figure 9. Leakage Currents as a Function of Temperature, Dual Supply
LEAKAGE CURRENT (pA)
0
–200
100
080
06576-027
300
250
200
150
–50
–100
–150
50
20 40 60 100 120
TEMPERATURE (ºC)
I
S
(OFF) + – I
D
(OFF) + –
I
S
(OFF) – + I
D
(OFF) – +
I
D
, I
S
(ON) + + I
D
, I
S
(ON) –
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1/10V
Figure 10. Leakage Currents as a Function of Temperature, Single Supply
120
0
0
06576-021
LOGIC LEVEL, INx (V)
I
DD
(µA)
V
DD
= 12V
V
SS
= 0V
V
DD
= +15V
V
SS
= –15V
I
DD
PER CHANNEL
T
A
= 25ºC
100
80
60
40
20
2 4 6 8 101214
Figure 11. IDD vs. Logic Level
0.5
–0.5
–15 15
06576-022
INPUT VOLTAGE (V)
CHARGE INJECTION (pC)
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–10 –5 0 5 10
T
A
= 25ºC
V
DD
= +15V
V
SS
= –15V
V
DD
= +5V
V
SS
= –5V
V
DD
= 12V
V
SS
= 0V
Figure 12. Charge Injection vs. Source Voltage
300
0
–40 120
06576-023
TEMPERATURE (ºC)
TIME (ns)
250
200
150
100
50
200 20406080100
15V DS t
ON
15V DS t
OFF
12V SS t
ON
12V SS t
OFF
Figure 13. TON/TOFF Times vs. Temperature
–120
10k 1G
06576-016
FREQUNCY (Hz)
OFF ISOLATION (dB)
100k 1M 10M 100M
–20
–40
0
–60
–80
–100
V
DD
= 15V
V
SS
= –15V
T
A
= 25ºC
Figure 14. Off Isolation vs. Frequency
ADG1201/ADG1202
Rev. 0 | Page 9 of 16
–14
10k 1G
06576-0017
FREQUNCY (Hz)
INSERTION LOSS (dE)
100k 1M 10M 100M
0
–2
–4
–6
–8
–10
–12
V
DD
= 15V
V
SS
= –15V
T
A
= 25ºC
Figure 15. On Response vs. Frequency
FREQUENCY (Hz)
THD + N (%)
10
1
0.1
0.01
10 100 1k 10k 100k
LOAD = 10k
T
A
= 25°C
V
DD
= +5V, V
SS
= –5V, V
S
= +3.5V rms
V
DD
= +15V, V
SS
= –15V, V
S
= +5V rms
06576-024
Figure 16. THD + N vs. Frequency
2
–15 15
06576-018
INPUT VOLTAGE (V)
CAPACITANCE (pF)
6
5.5
5
4.5
4
3.5
3
2.5
–10 –5 0 5 10
SOURCE/DRAIN ON
SOURCE OFF
DRAIN OFF
V
DD
= 15V
V
SS
= –15V
T
A
= 25ºC
Figure 17. Capacitance vs. Input Voltage, Dual Supply
2
012
06576-019
INPUT VOLTAGE (V)
CAPACITANCE (pF)
6
5.5
5
4.5
4
3.5
3
2.5
246810
SOURCE/DRAIN ON
SOURCE OFF
DRAIN OFF
V
DD
= 12V
V
SS
= 0V
T
A
= 25ºC
Figure 18. Capacitance vs. Input Voltage, Single Supply
0
–100
100k 1M 10M
06576-025
FREQUENCY (Hz)
ACPSRR (dB)
100M
–10
–20
–30
–40
–50
–60
–70
–80
–90
V
DD
= +15V
V
SS
= –15V
Vp-p = 0.63V
T
A
= 25ºC
DECOUPLING CAPS ON
NO DECOUPLING CAPS ON
Figure 19. ACPSRR vs. Frequency
ADG1201/ADG1202
Rev. 0 | Page 10 of 16
TEST CIRCUITS
I
DS
V1
SD
V
S
R
ON
= V1/I
DS
06576-008
Figure 20. On Resistance
SD
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
06576-009
Figure 21. Off Leakage
SD
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
06576-010
Figure 22. On Leakage
VOUT
50
NETWORK
ANALYZER
RL
50
IN
VIN
S
D
50
OFF ISOLATION = 20 LOG
VOUT
VS
VS
VDD VSS
0.1µF
V
DD
0.1µF
VSS
GND
06576-013
Figure 23. Off Isolation
V
OUT
50
NETWORK
ANALYZER
R
L
50
IN
V
IN
S
D
INSERTION LOSS = 20 LOG
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
06576-014
Figure 24. Bandwidth
V
OUT
R
S
AUDIO PRECISION
R
L
10k
IN
V
IN
S
D
V
S
V p-p
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
06576-015
Figure 25. THD + Noise
ADG1201/ADG1202
Rev. 0 | Page 11 of 16
V
S
IN
SD
GND
R
L
300
C
L
35pF
V
OUT
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
ADG1201
ADG1202
V
IN
V
IN
V
OUT
t
ON
t
OFF
50% 50%
90% 90%
50% 50%
06576-011
Figure 26. Switching Times
IN
V
OUT
ADG1201
ADG1202
V
IN
V
IN
V
OUT
OFF
V
OUT
ON
Q
INJ
= C
L
× V
OUT
SD
V
DD
V
SS
V
DD
V
SS
V
S
R
S
GND
C
L
1nF
06576-012
Figure 27. Charge Injection
ADG1201/ADG1202
Rev. 0 | Page 12 of 16
TERMINOLOGY
IDD
The positive supply current.
ISS
The negative supply current.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, measured with reference
to ground.
CD (Off)
The off switch drain capacitance, measured with reference
to ground.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
CIN
The digital input capacitance.
tON
The delay between applying the digital control input and the
output switching on. See Figure 26.
tOFF
The delay between applying the digital control input and the
output switching off. See Figure 26.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
ACPSRR (AC Power Supply Rejection Ratio)
Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of
signal on the output to the amplitude of the modulation is
the ACPSRR.
ADG1201/ADG1202
Rev. 0 | Page 13 of 16
OUTLINE DIMENSIONS
1 3
45
2
6
2.90 BSC
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
0.22
0.08
10°
0.50
0.30
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.60
0.45
0.30
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 28. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADG1201BRJZ-R21 −40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S25
ADG1201BRJZ-REEL71 −40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S25
ADG1202BRJZ-R21 −40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S26
ADG1202BRJZ-REEL71 −40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S26
1 Z = RoHS Compliant Part.
ADG1201/ADG1202
Rev. 0 | Page 14 of 16
NOTES
ADG1201/ADG1202
Rev. 0 | Page 15 of 16
NOTES
ADG1201/ADG1202
Rev. 0 | Page 16 of 16
NOTES
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