Low Capacitance, Low Charge Injection, 15 V/+12 V iCMOS SPST in SOT-23 ADG1201/ADG1202 FUNCTIONAL BLOCK DIAGRAM 2.4 pF off capacitance <1 pC charge injection Low leakage; 0.6 nA maximum @ 85C 120 on resistance Fully specified at 15 V, +12 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 6-lead SOT-23 package ADG1201 S ADG1202 D S IN SWITCHES SHOWN FOR A LOGIC "1" INPUT D IN 06576-001 FEATURES Figure 1. APPLICATIONS Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems GENERAL DESCRIPTION The ADG1201/ADG1202 are monolithic complementary metal-oxide semiconductor (CMOS) devices containing an SPST switch designed in an iCMOS(R) (industrial CMOS) process. iCMOS is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. The ADG1201/ADG1202 contain a single-pole/single-throw (SPST) switch. Figure 1 shows that with a logic input of 1, the switch of the ADG1201 is closed and that of the ADG1202 is open. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. Ultralow capacitance. <1 pC charge injection. Ultralow leakage. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V. No VL logic power supply required. SOT-23 package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. ADG1201/ADG1202 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................5 Applications ....................................................................................... 1 ESD Caution...................................................................................5 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Product Highlights ........................................................................... 1 Test Circuits ..................................................................................... 10 Revision History ............................................................................... 2 Terminology .................................................................................... 12 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 13 Dual Supply ................................................................................... 3 Ordering Guide .......................................................................... 13 Single Supply ................................................................................. 4 REVISION HISTORY 2/08--Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADG1201/ADG1202 SPECIFICATIONS DUAL SUPPLY VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25C B Version1 -40C to -40C to +85C +125C VDD to VSS 120 200 20 60 0.004 0.1 0.004 0.1 0.04 0.15 240 270 72 79 0.6 1 0.6 1 0.6 1 2.0 0.8 0.005 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 tON tOFF Charge Injection Off Isolation Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 2.5 140 170 90 105 -0.8 80 0.15 660 2.4 3 2.8 3.3 4.7 5.6 200 230 130 141 0.001 1.0 IDD 60 95 ISS 0.001 VDD/VSS 1 2 1.0 5 to 16.5 Temperature range for B version is -40C to +125C. Guaranteed by design, not subject to production test. Rev. 0 | Page 3 of 16 Unit Test Conditions/Comments V typ max typ max VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -1 mA; see Figure 20 VS = -5 V, 0 V, and +5 V; IS = -1 mA nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max pC typ dB typ % typ MHz typ pF typ pF max pF typ pF max pF typ pF max A typ A max A typ A max A typ A max V min/max VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = 10 V; see Figure 21 VS = 10 V, VD = 10 V; see Figure 21 VS = VD = 10 V; see Figure 22 VIN = VINL or VINH RL = 300 , CL = 35 pF VS = 10 V; see Figure 26 RL = 300 , CL = 35 pF VS = 10 V; see Figure 26 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 23 RL = 10 k, 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; see Figure 24 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V, 5 V or VDD GND = 0 V ADG1201/ADG1202 SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25C B Version1 -40C to -40C to +85C +125C 0 V to VDD 300 475 60 0.006 0.1 0.006 0.1 0.04 0.15 567 625 0.6 1 0.6 1 0.6 1 2.0 0.8 0.001 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 tON tOFF Charge Injection Off Isolation -3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 3 190 250 120 155 0.8 80 295 340 190 210 2 nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max pC typ dB typ MHz typ pF typ pF max pF typ pF max pF typ pF max 0.001 A typ A max A typ A max V min/max 60 VDD 1 V typ max typ 520 2.7 3.3 3.1 3.6 5.3 6.3 1.0 IDD Unit 95 +5/+16.5 Temperature range for B version is -40C to +125C. Guaranteed by design, not subject to production test. Rev. 0 | Page 4 of 16 Test Conditions/Comments VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -1 mA; see Figure 20 VS = 3 V, 6 V, and 9 V, IS = -1 mA VDD = 13.2 V, VSS = 0 V VS = 1 V or 10 V, VD = 10 V or 1 V; see Figure 21 VS = 1 V or 10 V, VD = 10 V or 1 V; see Figure 21 VS = VD = 1 V or 10 V; see Figure 22 VIN = VINL or VINH RL = 300 , CL = 35 pF VS = 8 V; see Figure 26 RL = 300 , CL = 35 pF VS = 8 V; see Figure 26 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 23 RL = 50 , CL = 5 pF; see Figure 24 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V VSS = 0 V, GND = 0 V ADG1201/ADG1202 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D Continuous Current per Channel, S or D Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature 6 Lead SOT-23 JA,Thermal Impedance JC, Thermal Impedance Reflow Soldering Peak Temperature, Pb-free 1 Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle maximum) 30 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION -40C to +125C -65C to +150C 150C 229.6C/W 91.99C/W 260C Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. 0 | Page 5 of 16 ADG1201/ADG1202 VDD 1 GND 2 ADG1201/ ADG1202 6 IN 5 D TOP VIEW VSS 3 (Not to Scale) 4 S 06576-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. SOT-23 Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VDD GND VSS S D IN Description Most Positive Power Supply Potential. Ground (0 V) Reference. Most Negative Power Supply Potential. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input. Table 5. ADG1201/ADG1202 Truth Table ADG1201 IN 1 0 ADG1202 IN 0 1 Switch Condition On Off Rev. 0 | Page 6 of 16 ADG1201/ADG1202 TYPICAL PERFORMANCE CHARACTERISTICS 200 250 180 VDD = +13.5V VSS = -13.5V 160 200 140 ON RESISTANCE () 120 100 VDD = +15V VSS = -15V 80 VDD = +16.5V VSS = -16.5V 60 40 TA = +125C 150 TA = +85C 100 TA = +25C TA = -40C 06576-003 50 20 0 -18 -15 -12 -9 -6 -3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 0 -15 18 Figure 3. On Resistance as a Function of VD (VS) for Dual Supply 06576-006 ON RESISTANCE () VDD = +15V VSS = -15V TA = +25C -10 -5 0 5 SOURCE OR DRAIN VOLTAGE (V) 15 Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply 450 600 TA = +25C VDD = +12V VSS = 0V 400 TA = +125C 500 350 TA = +85C VDD = +5.5V VSS = -5.5V 300 ON RESISTANCE () ON RESISTANCE () 10 250 200 150 400 300 200 TA = -40C 100 TA = +25C 50 0 -5 -4 -3 -2 -1 0 1 2 3 SOURCE OR DRAIN VOLTAGE (V) 4 0 5 Figure 4. On Resistance as a Function of VD (VS) for Dual Supply 2 4 6 8 SOURCE OR DRAIN VOLTAGE (V) 10 12 200 VDD = 12V VSS = 0V 100 LEAKAGE CURRENT (pA) VDD = 10.8V VSS = 0V 350 300 250 VDD = 13.2V VSS = 0V 200 150 100 06576-005 50 0 2 VDD = +15V VSS = -15V VBIAS = 10V 150 400 4 6 8 10 SOURCE OR DRAIN VOLTAGE (V) 12 Figure 5. On Resistance as a Function of VD (VS) for Single Supply Rev. 0 | Page 7 of 16 50 0 -50 -100 -150 -200 -250 -300 IS (OFF) + - IS (OFF) - + ID, IS (ON) + + -350 -400 -450 0 20 ID (OFF) + - ID (OFF) - + ID, IS (ON) - - 40 60 80 TEMPERATURE (C) 06576-028 TA = 25C ON RESISTANCE () 0 Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply 450 0 06576-007 06576-004 100 100 120 Figure 8. Leakage Currents as a Function of Temperature, Dual Supply ADG1201/ADG1202 0.5 150 VDD = +5V VSS = -5V VBIAS = 4.5V 0.4 CHARGE INJECTION (pC) 0 -50 -100 -150 0 40 0.1 0 -0.2 80 60 TEMPERATURE (C) 100 -0.5 -15 120 0 5 10 15 300 200 250 150 15V DS tOFF 15V DS tON 12V SS t OFF 12V SS t ON 200 TIME (ns) 100 50 0 150 100 -50 -100 IS (OFF) + - IS (OFF) - + ID, IS (ON) + + -150 0 50 ID (OFF) + - ID (OFF) - + ID, IS (ON) - - 20 40 06576-027 80 60 TEMPERATURE (C) 100 0 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 13. TON/TOFF Times vs. Temperature Figure 10. Leakage Currents as a Function of Temperature, Single Supply 0 120 IDD PER CHANNEL TA = 25C -20 OFF ISOLATION (dB) 100 80 60 VDD = +15V VSS = -15V 40 VDD = 12V VSS = 0V 0 2 4 6 -40 -60 -80 -100 06576-021 20 VDD = 15V VSS = -15V TA = 25C 8 10 12 14 -120 10k 06576-016 LEAKAGE CURRENT (pA) -5 Figure 12. Charge Injection vs. Source Voltage VDD = 12V VSS = 0V VBIAS = 1/10V 250 IDD (A) -10 INPUT VOLTAGE (V) 300 0 VDD = +5V VSS = -5V -0.4 Figure 9. Leakage Currents as a Function of Temperature, Dual Supply -200 VDD = 12V VSS = 0V -0.1 -0.3 ID (OFF) + - ID (OFF) - + ID, IS (ON) - - 20 0.2 06576-023 -250 VDD = +15V VSS = -15V 06576-022 IS (OFF) + - IS (OFF) - + ID, IS (ON) + + -200 TA = 25C 0.3 50 06576-026 LEAKAGE CURRENT (pA) 100 100k 1M 10M 100M FREQUNCY (Hz) LOGIC LEVEL, INx (V) Figure 14. Off Isolation vs. Frequency Figure 11. IDD vs. Logic Level Rev. 0 | Page 8 of 16 1G ADG1201/ADG1202 0 6 VDD = 15V VSS = -15V TA = 25C 5.5 SOURCE/DRAIN ON 5 -4 CAPACITANCE (pF) -6 -8 -10 VDD = 12V VSS = 0V TA = 25C 4.5 4 3.5 DRAIN OFF 3 -14 10k 2.5 06576-0017 -12 100k 1M 10M 100M 2 1G SOURCE OFF 0 2 4 06576-019 INSERTION LOSS (dE) -2 6 8 12 10 INPUT VOLTAGE (V) FREQUNCY (Hz) Figure 15. On Response vs. Frequency Figure 18. Capacitance vs. Input Voltage, Single Supply 10 0 LOAD = 10k TA = 25C -10 -20 VDD = +15V VSS = -15V Vp-p = 0.63V TA = 25C NO DECOUPLING CAPS ON -30 THD + N (%) 1 ACPSRR (dB) VDD = +5V, VSS = -5V, VS = +3.5V rms VDD = +15V, VSS = -15V, VS = +5V rms 0.1 -40 -50 -60 DECOUPLING CAPS ON -70 0.01 10 100 1k FREQUENCY (Hz) 10k 100k 06576-025 06576-024 -80 -90 -100 100k 1M 10M FREQUENCY (Hz) Figure 19. ACPSRR vs. Frequency Figure 16. THD + N vs. Frequency 6 VDD = 15V VSS = -15V TA = 25C 5.5 SOURCE/DRAIN ON 4.5 4 3.5 DRAIN OFF 3 2.5 06576-018 CAPACITANCE (pF) 5 SOURCE OFF 2 -15 -10 -5 0 5 10 15 INPUT VOLTAGE (V) Figure 17. Capacitance vs. Input Voltage, Dual Supply Rev. 0 | Page 9 of 16 100M ADG1201/ADG1202 TEST CIRCUITS VDD VSS 0.1F 0.1F VDD NETWORK ANALYZER VSS S IDS 50 50 IN VS D VIN S GND D 06576-008 RON = V1/IDS VS RL 50 VOUT OFF ISOLATION = 20 LOG Figure 20. On Resistance VOUT VS 06576-013 V1 Figure 23. Off Isolation VDD VSS 0.1F 0.1F VDD NETWORK ANALYZER VSS S 50 IN VS D D VIN ID (OFF) A VS RL 50 GND VD INSERTION LOSS = 20 LOG Figure 21. Off Leakage VOUT VOUT WITH SWITCH VOUT WITHOUT SWITCH 06576-014 A S 06576-009 IS (OFF) Figure 24. Bandwidth VDD VSS 0.1F 0.1F VDD AUDIO PRECISION VSS RS S IN ID (ON) D NC = NO CONNECT A VD VIN GND Figure 22. On Leakage RL 10k Figure 25. THD + Noise Rev. 0 | Page 10 of 16 VOUT 06576-015 S 06576-010 NC VS V p-p D ADG1201/ADG1202 VDD VSS 0.1F VDD VSS S VS VIN ADG1201 50% 50% VIN ADG1202 50% 50% VOUT D CL 35pF RL 300 IN 90% VOUT 90% GND tOFF tON 06576-011 0.1F Figure 26. Switching Times VS VSS VDD VSS S D VIN CL 1nF IN GND ADG1201 ON VOUT VIN OFF ADG1202 VOUT QINJ = CL x VOUT Figure 27. Charge Injection Rev. 0 | Page 11 of 16 VOUT 06576-012 RS VDD ADG1201/ADG1202 TERMINOLOGY IDD The positive supply current. CD, CS (On) The on switch capacitance, measured with reference to ground. ISS The negative supply current. CIN The digital input capacitance. VD (VS) The analog voltage on Terminal D and Terminal S. tON The delay between applying the digital control input and the output switching on. See Figure 26. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. tOFF The delay between applying the digital control input and the output switching off. See Figure 26. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. ID, IS (On) The channel leakage current with the switch on. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. VINL The maximum input voltage for Logic 0. Bandwidth The frequency at which the output is attenuated by 3 dB. VINH The minimum input voltage for Logic 1. On Response The frequency response of the on switch. IINL (IINH) The input current of the digital input. Insertion Loss The loss due to the on resistance of the switch. CS (Off) The off switch source capacitance, measured with reference to ground. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. CD (Off) The off switch drain capacitance, measured with reference to ground. ACPSRR (AC Power Supply Rejection Ratio) Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. Rev. 0 | Page 12 of 16 ADG1201/ADG1202 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 1 2 3 2.80 BSC 1.60 BSC PIN 1 INDICATOR 0.95 BSC 1.30 1.15 0.90 1.90 BSC 1.45 MAX 0.15 MAX 0.50 0.30 0.22 0.08 SEATING PLANE 10 4 0 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 28. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters ORDERING GUIDE Model ADG1201BRJZ-R21 ADG1201BRJZ-REEL71 ADG1202BRJZ-R21 ADG1202BRJZ-REEL71 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 6-Lead Small Outline Transistor Package [SOT-23] 6-Lead Small Outline Transistor Package [SOT-23] 6-Lead Small Outline Transistor Package [SOT-23] 6-Lead Small Outline Transistor Package [SOT-23] Z = RoHS Compliant Part. Rev. 0 | Page 13 of 16 Package Option RJ-6 RJ-6 RJ-6 RJ-6 Branding S25 S25 S26 S26 ADG1201/ADG1202 NOTES Rev. 0 | Page 14 of 16 ADG1201/ADG1202 NOTES Rev. 0 | Page 15 of 16 ADG1201/ADG1202 NOTES (c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06576-0-2/08(0) Rev. 0 | Page 16 of 16