MC68360
QUad Integrated
Communications Controller
User’s Manual
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MC68360 USER’S MANUAL
PREFACE
The complete documentation package for the MC68360 consists of the MC68360UM/AD,
MC68360 QUad Integrated Communications Controller User’s Manual
, M68000PM/AD,
MC68000 Family Programmer’s Reference Manual,
and the MC68360/D,
MC68360 QUad
Integrated Communications Controller Product Brief
.
The
MC68360 QUad Integrated Communications Controller User’s Manual
describes the
programming, capabilities, registers, and operation of the MC68360 and the MC68EN360;
the
MC68000 Family Programmer’s Reference Manual
provides instruction details for the
MC68360; and
the
MC68360 QUad Integrated Communications Controller Product Brief
provides a brief description of the MC68360 capabilities.
This user’s manual is organized as follows:
Section 1 Introduction
Section 2 Signal Descriptions
Section 3 Memory Map
Section 4 Bus Operation
Section 5 CPU32+
Section 6 System Integration Module (SIM60)
Section 7 Communication Processor Module (CPM)
Section 8 IEEE 1149.1 Test Access Port
Section 9 Applications
Section 10 Electrical Characteristics
Section 11 Ordering Information and Mechanical Data
Appendix A Serial Performance
Appendix B Development Tools and Support
Appendix C RISC Microcode from RAM
Appendix D MC68MH360 Product Brief
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Table of Contents
Paragraph Title Page
Number Number
MC68360 USER’S MANUAL
Section 1
Introduction
1.1 QUICC Key Features .............................................................................. 1-1
1.2 QUICC Architecture Overview................................................................. 1-4
1.2.1 CPU32+ Core.......................................................................................... 1-5
1.2.2 System Integration Module (SIM60)........................................................ 1-5
1.2.3 Communications Processor Module (CPM)............................................ 1-6
1.3 Upgrading Designs from the MC68302................................................... 1-6
1.3.1 Architectural Approach............................................................................ 1-6
1.3.2 Hardware Compatibility Issues................................................................ 1-7
1.3.3 Software Compatibility Issues.................................................................1-7
1.4 QUICC Glueless System Design............................................................. 1-8
1.5 QUICC Serial Configurations .................................................................. 1-9
1.6 QUICC Serial Configuration Examples ................................................. 1-16
1.7 QUICC System Bus Configurations ...................................................... 1-17
Section 2
Signal Descriptions
2.1 System Bus Signal Index ........................................................................2-1
2.1.1 Address Bus............................................................................................2-1
2.1.1.1 Address Bus (A27–A0)............................................................................2-1
2.1.1.2 Address Bus (A31–A28)..........................................................................2-1
2.1.2 Function Codes (FC3–FC0)....................................................................2-5
2.1.3 Data Bus.................................................................................................. 2-5
2.1.3.1 Data Bus (D31–D16)............................................................................... 2-5
2.1.3.2 Data Bus (D15–D0)................................................................................. 2-6
2.1.4 Parity....................................................................................................... 2-6
2.1.4.1 Parity (PRTY0)........................................................................................2-6
2.1.4.2 Parity (PRTY1)........................................................................................2-6
2.1.4.3 Parity (PRTY2)........................................................................................2-6
2.1.4.4 Parity (PRTY3)........................................................................................2-6
2.1.5 Memory Controller................................................................................... 2-6
2.1.5.1 Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0) ...................2-6
2.1.5.2 Chip Select/Row Address Select/Interrupt Acknowledge (CS7/RAS7/IACK7).
2-6
2.1.5.3 Column Address Select/Interrupt Acknowledge (CAS3–CAS0/IACK6, 3, 2,
1). 2-7
2.1.5.4 Address Multiplex (AMUX)......................................................................2-7
2.1.6 Interrupt Request Level (IRQ7–IRQ1)..................................................... 2-7
2.1.7 Bus Control Signals.................................................................................2-7
2.1.7.1 Data and Size Acknowledge (DSACK1–DSACK0).................................2-8
2.1.7.2 Autovector/Interrupt Acknowledge (AVEC/IACK5)..................................2-8
2.1.7.3 Address Strobe (AS). ..............................................................................2-8
2.1.7.4 Data Strobe (DS)..................................................................................... 2-8
Thi d t t d ith F M k 4 0 4
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2.1.7.5 Transfer Size (SIZ1, SIZ0).......................................................................2-8
2.1.7.6 Read/Write (R/W).....................................................................................2-8
2.1.7.7 Output Enable/Address Multiplex (OE/AMUX).........................................2-9
2.1.7.8 Byte Write Enable (WE3–WE0)...............................................................2-9
2.1.8 Bus Arbitration Signals.............................................................................2-9
2.1.8.1 Bus Request (BR)....................................................................................2-9
2.1.8.2 Bus Grant (BG)........................................................................................2-9
2.1.8.3 Bus Grant Acknowledge (BGACK). .........................................................2-9
2.1.8.4 Read-Modify-Write Cycle/Initial Configuration (RMC/CONFIG0).............2-9
2.1.8.5 Bus Clear Out/Initial Configuration/Row Address Select Double-Drive (BCL-
RO/CONFIG1/RAS2DD).2-9
2.1.9 System Control Signals..........................................................................2-10
2.1.9.1 Soft Reset (RESETS). ...........................................................................2-10
2.1.9.2 Hard Reset (RESETH)...........................................................................2-10
2.1.9.3 Halt (HALT)............................................................................................2-10
2.1.9.4 Bus Error (BERR). .................................................................................2-10
2.1.10 Clock Signals.........................................................................................2-10
2.1.10.1 System Clock Outputs (CLKO2–CLKO1). .............................................2-10
2.1.10.2 Crystal Oscillator (EXTAL, XTAL)..........................................................2-11
2.1.10.3 External Filter Capacitor (XFC)..............................................................2-11
2.1.10.4 Clock Mode Select (MODCK1–MODCK0).............................................2-11
2.1.11 Instrumentation and Emulation Signals .................................................2-11
2.1.11.1 Instruction Fetch/Development Serial Input (IFETCH/DSI)....................2-11
2.1.11.2 Instruction Pipe/Development Serial Output (
IPIPE0/DSO
)...................2-11
2.1.11.3 Instruction Pipe/Row Address Select Double-Drive (
IPIPE1/RAS1DD
).2-11
2.1.11.4 Breakpoint/Development Serial clock (BKPT/DSCLK). .........................2-11
2.1.11.5 Freeze/Initial Configuration (FREEZE/CONFIG2). ................................2-12
2.1.12 Test Signals...........................................................................................2-12
2.1.12.1 TRI-State Signal (TRIS).........................................................................2-12
2.1.12.2 Test Reset (TRST).................................................................................2-12
2.1.12.3 Test Clock (TCK). ..................................................................................2-12
2.1.12.4 Test Mode Select (TMS)........................................................................2-12
2.1.12.5 Test Data In (TDI)..................................................................................2-12
2.1.12.6 Test Data Out (TDO)..............................................................................2-12
2.1.13 Initial Configuration Pins (CONFIG).......................................................2-12
2.1.14 Power Signals........................................................................................2-13
2.1.14.1 VCCSYN and GNDSYN.........................................................................2-13
2.1.14.2 VCCCLK and GNDCLK. ........................................................................2-13
2.1.14.3 GNDS1 and GNDS2..............................................................................2-13
2.1.14.4 VCC and GND. ......................................................................................2-13
2.1.14.5 NC4–NC1...............................................................................................2-13
2.2 System Bus Signal Index in Slave Mode...............................................2-14
2.3 On-Chip Peripherals Signal Index..........................................................2-15
Section 3
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Number Number
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QUICC Memory Map
3.1 Dual-Port RAM Memory Map.................................................................. 3-2
3.2 CPM Sub-Module Base Addresses.........................................................3-3
3.3 Internal Registers Memory Map..............................................................3-4
3.3.1 SIM Registers Memory Map.................................................................... 3-4
3.3.2 CPM Registers Memory Map.................................................................. 3-6
Section 4
Bus Operation
4.1 Bus Transfer Signals............................................................................... 4-2
4.1.1 Bus Control Signals.................................................................................4-3
4.1.2 Function Codes (FC3–FC0)....................................................................4-3
4.1.3 Address Bus (A31–A0)............................................................................4-4
4.1.4 Address Strobe (AS) ...............................................................................4-4
4.1.5 Data Bus (D31-D0).................................................................................. 4-4
4.1.6 Data Strobe (DS)..................................................................................... 4-4
4.1.7 Output Enable (OE).................................................................................4-4
4.1.8 Byte Write Enable (WE0, WE1, WE2, WE3)........................................... 4-4
4.1.9 Bus Cycle Termination Signals ............................................................... 4-5
4.1.9.1 Data transfer and size acknowledge (DSACK1 and DSACK0)...............4-5
4.1.9.2 Bus Error (BERR).................................................................................... 4-5
4.1.9.3 Autovector (AVEC).................................................................................. 4-6
4.2 Data Transfer Mechanism....................................................................... 4-6
4.2.1 Dynamic Bus Sizing ................................................................................4-6
4.2.2 Misaligned Operands ............................................................................4-11
4.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment..................4-19
4.2.4 Bus Operation .......................................................................................4-20
4.2.5 Synchronous Operation with DSACKx..................................................4-21
4.2.6 Fast Termination Cycles........................................................................ 4-21
4.3 Data Transfer Cycles............................................................................. 4-22
4.3.1 Read Cycle............................................................................................4-23
4.3.2 Write Cycle............................................................................................ 4-26
4.3.3 Read-Modify-Write Cycle ...................................................................... 4-28
4.4 CPU Space Cycles................................................................................4-31
4.4.1 Breakpoint Acknowledge Cycle.............................................................4-31
4.4.2 LPSTOP Broadcast Cycle.....................................................................4-35
4.4.3 Module Base Address Register (MBAR) Access .................................. 4-36
4.4.4 Interrupt Acknowledge Bus Cycles........................................................ 4-36
4.4.4.1 Interrupt Acknowledge Cycle—Terminated Normally............................ 4-36
4.4.4.2 Autovector Interrupt Acknowledge Cycle. .............................................4-38
4.4.4.3 Spurious Interrupt Cycle........................................................................ 4-40
4.5 Bus Exception Control Cycles............................................................... 4-41
4.5.1 Bus Errors ............................................................................................. 4-42
4.5.2 Retry Operation..................................................................................... 4-44
4.5.3 Halt Operation.......................................................................................4-46
4.5.4 Double Bus Fault...................................................................................4-48
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4.6 Bus Arbitration .......................................................................................4-49
4.6.1 Bus Request ..........................................................................................4-52
4.6.2 Bus Grant...............................................................................................4-53
4.6.3 Bus Grant Acknowledge ........................................................................4-53
4.6.4 Bus Arbitration Control...........................................................................4-54
4.6.5 Slave (Disable CPU32+) Mode Bus Arbitration .....................................4-55
4.6.6 Slave (Disable CPU32+) Mode Bus Exceptions....................................4-59
4.6.6.1 HALT......................................................................................................4-59
4.6.6.2 RETRY...................................................................................................4-59
4.6.7 Internal Accesses...................................................................................4-59
4.6.8 Show Cycles..........................................................................................4-62
4.7 Reset Operation.....................................................................................4-63
Section 5
CPU32+
5.1 Overview..................................................................................................5-1
5.1.1 Features...................................................................................................5-2
5.1.2 Loop Mode Instruction Execution.............................................................5-3
5.1.3 Vector Base Register...............................................................................5-4
5.1.4 Exception Handling..................................................................................5-4
5.1.5 Addressing Modes...................................................................................5-5
5.2 Architecture Summary .............................................................................5-5
5.2.1 Programming Model.................................................................................5-6
5.2.2 Registers..................................................................................................5-7
5.3 Instruction Set..........................................................................................5-8
5.3.1 M68000 Family Compatibility.................................................................5-10
5.3.1.1 New Instructions. ...................................................................................5-10
5.3.1.2 Low-Power Stop (LPSTOP)...................................................................5-10
5.3.1.3 Table Lookup and Interpolate (TBL)......................................................5-10
5.3.1.4 Unimplemented Instructions. .................................................................5-10
5.3.2 Instruction Format and Notation.............................................................5-10
5.3.3 Instruction Summary..............................................................................5-13
5.3.3.1 Condition Code Register........................................................................5-17
5.3.3.2 Data Movement Instructions..................................................................5-19
5.3.3.3 Integer Arithmetic Operations................................................................5-19
5.3.3.4 Logic Instructions...................................................................................5-21
5.3.3.5 Shift and Rotate Instructions..................................................................5-22
5.3.3.6 Bit Manipulation Instructions..................................................................5-23
5.3.3.7 Binary-Coded Decimal (BCD) Instructions.............................................5-24
5.3.3.8 Program Control Instructions.................................................................5-24
5.3.3.9 System Control Instructions...................................................................5-25
5.3.3.10 Condition Tests......................................................................................5-26
5.3.4 Using the TBL Instructions.....................................................................5-27
5.3.4.1 Table Example 1: Standard Usage........................................................5-28
5.3.4.2 Table Example 2: Compressed Table....................................................5-29
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5.3.4.3 Table Example 3: 8-Bit Independent Variable.......................................5-30
5.3.4.4 Table Example 4: Maintaining Precision...............................................5-32
5.3.4.5 Table Example 5: Surface Interpolations ..............................................5-33
5.3.5 Nested Subroutine Calls........................................................................ 5-33
5.3.6 Pipeline Synchronization with the NOP Instruction...............................5-34
5.4 Processing States .................................................................................5-34
5.4.1 State Transitions ...................................................................................5-34
5.4.2 Privilege Levels.....................................................................................5-34
5.4.2.1 Supervisor Privilege Level..................................................................... 5-35
5.4.2.2 User Privilege Level .............................................................................. 5-35
5.4.2.3 Changing Privilege Level....................................................................... 5-35
5.5 Exception Processing............................................................................5-36
5.5.1 Exception Vectors .................................................................................5-36
5.5.1.1 Types of Exceptions..............................................................................5-36
5.5.1.2 Exception Processing Sequence........................................................... 5-38
5.5.1.3 Exception Stack Frame.........................................................................5-38
5.5.1.4 Multiple Exceptions ...............................................................................5-39
5.5.2 Processing of Specific Exceptions ........................................................5-40
5.5.2.1 Reset..................................................................................................... 5-40
5.5.2.2 Bus Error...............................................................................................5-40
5.5.2.3 Address Error........................................................................................5-42
5.5.2.4 Instruction Traps.................................................................................... 5-42
5.5.2.5 Software Breakpoints............................................................................5-43
5.5.2.6 Hardware Breakpoints........................................................................... 5-43
5.5.2.7 Format Error.......................................................................................... 5-43
5.5.2.8 Illegal or Unimplemented Instructions...................................................5-44
5.5.2.9 Privilege Violations................................................................................ 5-44
5.5.2.10 Tracing .................................................................................................. 5-45
5.5.2.11 Interrupts............................................................................................... 5-46
5.5.2.12 Return from Exception........................................................................... 5-47
5.5.3 Fault Recovery......................................................................................5-48
5.5.3.1 Types of Faults......................................................................................5-51
5.5.3.1.1 Type I—Released Write Faults ............................................................. 5-51
5.5.3.1.2 Type II—Prefetch, Operand, RMW, and MOVEP Faults....................... 5-51
5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer ............................. 5-52
5.5.3.1.4 Type IV—Faults During Exception Processing .....................................5-52
5.5.3.2 Correcting a Fault.................................................................................. 5-53
5.5.3.2.1 Type I—Completing Released Writes via Software .............................. 5-53
5.5.3.2.2 Type I—Completing Released Writes via RTE ..................................... 5-53
5.5.3.2.3 Type II—Correcting Faults via RTE....................................................... 5-54
5.5.3.2.4 Type III—Correcting Faults via Software............................................... 5-54
5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart........................ 5-55
5.5.3.2.6 Type III—Correcting Faults via RTE...................................................... 5-55
5.5.3.2.7 Type IV—Correcting Faults via Software..............................................5-55
5.5.4 CPU32+ Stack Frames ......................................................................... 5-56
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5.5.4.1 Four-Word Stack Frame ........................................................................5-56
5.5.4.2 Six-Word Stack Frame...........................................................................5-56
5.5.4.3 Bus Error Stack Frame ..........................................................................5-56
5.6 Development Support............................................................................5-59
5.6.1 CPU32+ Integrated Development Support ............................................5-59
5.6.1.1 Background Debug Mode (BDM) Overview...........................................5-59
5.6.1.2 Deterministic Opcode Tracking Overview..............................................5-60
5.6.1.3 On-Chip Hardware Breakpoint Overview...............................................5-60
5.6.2 Background Debug Mode......................................................................5-60
5.6.2.1 Enabling BDM........................................................................................5-60
5.6.2.2 BDM Sources.........................................................................................5-61
5.6.2.2.1 External BKPT Signal ............................................................................5-62
5.6.2.2.2 BGND Instruction...................................................................................5-62
5.6.2.2.3 Double Bus Fault ...................................................................................5-62
5.6.2.3 Entering BDM.........................................................................................5-62
5.6.2.4 Command Execution..............................................................................5-62
5.6.2.5 BDM Registers.......................................................................................5-63
5.6.2.5.1 Fault Address Register (FAR)................................................................5-63
5.6.2.5.2 Return Program Counter (RPC).............................................................5-63
5.6.2.5.3 Current Instruction Program Counter (PCC)..........................................5-63
5.6.2.6 Returning from BDM..............................................................................5-63
5.6.2.7 Serial Interface.......................................................................................5-63
5.6.2.7.1 CPU Serial Logic....................................................................................5-65
5.6.2.7.2 Development System Serial Logic.........................................................5-66
5.6.2.8 Command Set........................................................................................5-68
5.6.2.8.1 Command Format..................................................................................5-68
5.6.2.8.2 Command Sequence Diagram...............................................................5-69
5.6.2.8.3 Command Set Summary........................................................................5-69
5.6.2.8.4 Read A/D Register (RAREG/RDREG)...................................................5-71
5.6.2.8.5 Write A/D Register (WAREG/WDREG) .................................................5-71
5.6.2.8.6 Read System Register (RSREG)...........................................................5-71
5.6.2.8.7 Write System Register (WSREG)..........................................................5-72
5.6.2.8.8 Read Memory Location (READ) ............................................................5-73
5.6.2.8.9 Write Memory Location (WRITE)...........................................................5-74
5.6.2.8.10 Dump Memory Block (DUMP)................................................................5-75
5.6.2.8.11 Fill Memory Block (FILL)........................................................................5-76
5.6.2.8.12 Resume Execution (GO)........................................................................5-77
5.6.2.8.13 Call User Code (CALL)..........................................................................5-77
5.6.2.8.14 Reset Peripherals (RST)........................................................................5-79
5.6.2.8.15 No Operation (NOP) ..............................................................................5-79
5.6.2.8.16 Future Commands.................................................................................5-80
5.6.3 Deterministic Opcode Tracking..............................................................5-80
5.6.3.1 Instruction Fetch (IFETCH)....................................................................5-80
5.6.3.2 Instruction Pipe (IPIPE1–IPIPE0) ..........................................................5-80
5.6.3.3 Opcode Tracking during Loop Mode......................................................5-82
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5.7 Instruction Execution Timing.................................................................5-82
5.7.1 Resource Scheduling............................................................................5-83
5.7.1.1 Microsequencer..................................................................................... 5-83
5.7.1.2 Instruction Pipeline................................................................................5-83
5.7.1.3 Bus Controller Resources ..................................................................... 5-83
5.7.1.3.1 Prefetch Controller ................................................................................ 5-84
5.7.1.3.2 Write-Pending Buffer............................................................................. 5-84
5.7.1.3.3 Microbus Controller...............................................................................5-85
5.7.1.4 Instruction Execution Overlap ...............................................................5-85
5.7.1.5 Effects of Wait States............................................................................5-86
5.7.1.6 Instruction Execution Time Calculation.................................................5-86
5.7.1.7 Effects of Negative Tails........................................................................ 5-87
5.7.2 Instruction Timing Tables......................................................................5-88
5.7.2.1 Fetch Effective Address ........................................................................5-90
5.7.2.2 Calculate Effective Address ..................................................................5-91
5.7.2.3 MOVE Instruction..................................................................................5-92
5.7.2.4 Special-Purpose MOVE Instruction.......................................................5-92
5.7.2.5 Arithmetic/Logic Instructions ................................................................. 5-93
5.7.2.6 Immediate Arithmetic/Logic Instructions................................................ 5-95
5.7.2.7 Binary-Coded Decimal and Extended Instructions................................5-95
5.7.2.8 Single Operand Instructions..................................................................5-96
5.7.2.9 Shift/Rotate Instructions........................................................................5-96
5.7.2.10 Bit Manipulation Instructions .................................................................5-97
5.7.2.11 Conditional Branch Instructions............................................................. 5-98
5.7.2.12 Control Instructions ...............................................................................5-99
5.7.2.13 Exception-Related Instructions and Operations..................................5-100
5.7.2.14 Save and Restore Operations.............................................................5-101
Section 6
System Integration Module (SIM60)
6.1 Module Overview..................................................................................... 6-1
6.2 Module Base Address Register (MBAR)................................................. 6-3
6.3 System Configuration and Protection......................................................6-3
6.3.1 System Configuration.............................................................................. 6-5
6.3.1.1 SIM60 Interrupt Generation.....................................................................6-6
6.3.1.2 Simultaneous SIM60 Interrupt Sources................................................... 6-8
6.3.1.2.1 Bus Monitor.............................................................................................6-8
6.3.1.2.2 Spurious Interrupt Monitor....................................................................... 6-8
6.3.1.2.3 Double Bus Fault Monitor........................................................................6-9
6.3.1.2.4 Software Watchdog Timer (SWT) ........................................................... 6-9
6.3.2 Periodic Interrupt Timer (PIT)................................................................ 6-10
6.3.2.1 PIT Period Calculation........................................................................... 6-10
6.3.2.2 Using the PIT as a Real-Time Clock.....................................................6-11
6.3.3 Freeze Support...................................................................................... 6-11
6.3.4 Low-Power Stop Support ......................................................................6-11
6.4 Low Power in Normal Operation ........................................................... 6-12
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6.5 SIM60 System Clock Generation...........................................................6-12
6.5.1 Clock Generation Methods ....................................................................6-12
6.5.2 Oscillator Prescaler (Divide by 128).......................................................6-13
6.5.3 Phase-Locked Loop (PLL).....................................................................6-14
6.5.3.1 Frequency Multiplication........................................................................6-14
6.5.3.2 Skew Elimination....................................................................................6-15
6.5.4 Low-Power Divider.................................................................................6-15
6.5.5 QUICC Internal Clock Signals................................................................6-15
6.5.5.1 SPCLK...................................................................................................6-16
6.5.5.2 General System Clock...........................................................................6-16
6.5.5.3 BRGCLK................................................................................................6-17
6.5.5.4 SyncCLK................................................................................................6-17
6.5.5.5 SIMCLK..................................................................................................6-18
6.5.5.6 CLKO1...................................................................................................6-18
6.5.5.7 CLKO2...................................................................................................6-18
6.5.6 PLL Power Pins .....................................................................................6-19
6.5.6.1 VCCSYN................................................................................................6-19
6.5.6.2 GNDSYN................................................................................................6-19
6.5.6.3 XFC........................................................................................................6-19
6.5.7 CLKO Power Pins..................................................................................6-19
6.5.7.1 VCCCLK ................................................................................................6-19
6.5.7.2 GNDCLK................................................................................................6-19
6.5.8 Configuration Pins (MODCK1–MODCK0) .............................................6-19
6.6 Breakpoint Logic....................................................................................6-20
6.7 External Bus Interface Control...............................................................6-21
6.7.1 Initial Configuration................................................................................6-22
6.7.2 Port D.....................................................................................................6-22
6.7.3 Port E.....................................................................................................6-23
6.8 Slave (Disable CPU32+) Mode..............................................................6-23
6.8.1 MBAR in a Multiple QUICC System.......................................................6-24
6.8.2 Global Chip Select (CS0) in Slave Mode...............................................6-25
6.8.3 Bus Clear in Slave Mode .......................................................................6-25
6.8.4 Interrupts in Slave Mode........................................................................6-26
6.8.5 Pin Differences in Slave Mode...............................................................6-26
6.8.6 Other Functionality in Slave Mode.........................................................6-27
6.9 Programmer’s Model..............................................................................6-27
6.9.1 Module Base Address Register (MBAR)................................................6-27
6.9.2 Module Base Address Register Enable (MBARE).................................6-29
6.9.3 System Configuration and Protection Registers....................................6-29
6.9.3.1 Module Configuration Register (MCR)...................................................6-29
6.9.3.2 Autovector Register (AVR).....................................................................6-34
6.9.3.3 Reset Status Register (RSR).................................................................6-34
6.9.3.4 Software Watchdog Interrupt Vector Register (SWIV)...........................6-35
6.9.3.5 System Protection Control Register (SYPCR).......................................6-35
6.9.3.6 Periodic Interrupt Control Register (PICR).............................................6-37
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6.9.3.7 Periodic Interrupt Timer Register (PITR)............................................... 6-38
6.9.3.8 Software Service Register (SWSR)....................................................... 6-39
6.9.3.9 CLKO Control Register (CLKOCR)....................................................... 6-39
6.9.3.10 PLL Control Register (PLLCR).............................................................. 6-40
6.9.3.11 Clock Divider Control Register (CDVCR).............................................. 6-42
6.9.3.12 Breakpoint Address Register (BKAR) ................................................... 6-44
6.9.3.13 Breakpoint Control Register (BKCR)..................................................... 6-44
6.9.4 Port E Pin Assignment Register (PEPAR) ............................................ 6-48
6.10 Memory Controller................................................................................. 6-50
6.10.1 Memory Controller Key Features .......................................................... 6-50
6.10.2 Memory Controller Overview................................................................. 6-51
6.11 General-Purpose Chip-Select Overview (SRAM Banks)....................... 6-56
6.11.1 Associated Registers............................................................................. 6-56
6.11.2 8-, 16-, and 32-Bit Port Size Configuration............................................ 6-56
6.11.3 Write Protect Configuration...................................................................6-56
6.11.4 Programmable Wait State Configuration............................................... 6-56
6.11.5 Address and Address Space Checking.................................................6-57
6.11.6 SRAM Bank Parity................................................................................. 6-57
6.11.7 External Master Support........................................................................ 6-57
6.11.8 Global (Boot) Chip-Select Operation..................................................... 6-58
6.11.9 SRAM Bus Error.................................................................................... 6-58
6.12 DRAM Controller Overview (DRAM Banks).......................................... 6-58
6.12.1 DRAM Normal Access Support............................................................. 6-60
6.12.2 DRAM Page Mode Support...................................................................6-60
6.12.3 DRAM Burst Access Support................................................................6-61
6.12.4 DRAM Bank Parity ................................................................................ 6-62
6.12.5 Refresh Operation................................................................................. 6-62
6.12.6 DRAM Bank External Master Support................................................... 6-63
6.12.7 Double-Drive RAS Lines ....................................................................... 6-63
6.12.8 DRAM Bus Error.................................................................................... 6-63
6.13 Programming Model.............................................................................. 6-64
6.13.1 Global Memory Register (GMR)............................................................ 6-64
6.13.2 Memory Controller Status Register (MSTAT)........................................ 6-69
6.13.3 Base Register (BR) ............................................................................... 6-70
6.13.4 Option Register (OR)............................................................................. 6-74
6.13.5 DRAM-SRAM Performance Summary;................................................. 6-78
Section 7
Communication Processor Module (CPM)
Introduction.............................................................................................. 7-1
7.1 RISC Controller.......................................................................................7-3
7.1.1 RISC Controller Configuration Register (RCCR).................................... 7-4
7.1.2 RISC Microcode Revision Number......................................................... 7-5
7.2 Command Set ........................................................................................7-5
7.2.1 Command Register Examples................................................................. 7-8
7.2.2 Command Execution Latency .................................................................7-8
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7.3 Dual-Port RAM.........................................................................................7-8
7.3.1 Buffer Descriptors..................................................................................7-10
7.3.2 Parameter RAM.....................................................................................7-10
7.4 RISC Timer Tables ................................................................................7-11
7.4.1 RISC Timer Table Parameter RAM .......................................................7-12
7.4.2 RISC Timer Table Entries......................................................................7-14
7.4.3 RISC Timer Event Register (RTER) ......................................................7-14
7.4.4 RISC Timer Mask Register (RTMR) ......................................................7-14
7.4.5 SET TIMER Command..........................................................................7-14
7.4.6 RISC Timer Initialization Sequence.......................................................7-14
7.4.7 RISC Timer Initialization Example .........................................................7-15
7.4.8 RISC Timer Interrupt Handling..............................................................7-16
7.4.9 RISC Timer Table Algorithm.................................................................7-16
7.4.10 RISC Timer Table Application: Track the RISC Loading.......................7-16
7.5 Timers...................................................................................................7-17
7.5.1 Timer Key Features ...............................................................................7-17
7.5.2 General-Purpose Timer Units...............................................................7-18
7.5.2.1 Cascaded Mode.....................................................................................7-19
7.5.2.2 Timer Global Configuration Register (TGCR)........................................7-20
7.5.2.3 Timer Mode Register (TMR1, TMR2, TMR3, TMR4).............................7-21
7.5.2.4 Timer Reference Registers (TRR1, TRR2, TRR3, TRR4).....................7-22
7.5.2.5 Timer Capture Registers (TCR1, TCR2, TCR3, TCR4).........................7-22
7.5.2.6 Timer Counter (TCN1, TCN2, TCN3, TCN4).........................................7-22
7.5.2.7 Timer Event Registers (TER1, TER2, TER3, TER4).............................7-22
7.5.3 Timer Examples.....................................................................................7-23
7.6 IDMA Channels......................................................................................7-24
7.6.1 IDMA Key Features;..............................................................................7-25
7.6.2 IDMA Registers.....................................................................................7-26
7.6.2.1 IDMA Channel Configuration Register (ICCR).......................................7-26
7.6.2.2 Channel Mode Register (CMR)..............................................................7-28
7.6.2.3 Source Address Pointer Register (SAPR) .............................................7-30
7.6.2.4 Destination Address Pointer Register (DAPR).......................................7-31
7.6.2.5 Function Code Register (FCR) ..............................................................7-31
7.6.2.6 Byte Count Register (BCR)....................................................................7-31
7.6.2.7 Channel Status Register (CSR).............................................................7-32
7.6.2.8 Channel Mask Register (CMAR)............................................................7-33
7.6.2.9 Data Holding Register (DHR).................................................................7-33
7.6.3 Interface Signals...................................................................................7-33
7.6.3.1 DREQ and DACK...................................................................................7-33
7.6.3.2 DONEx...................................................................................................7-33
7.6.4 IDMA Operation....................................................................................7-34
7.6.4.1 Single Buffer ..........................................................................................7-34
7.6.4.2 Auto Buffer and Buffer Chaining............................................................7-34
7.6.4.2.1 IDMA Parameter RAM...........................................................................7-35
7.6.4.2.2 IDMA Buffer Descriptors (BDs)..............................................................7-36
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7.6.4.2.3 IDMA Commands (INIT_IDMA)............................................................. 7-38
7.6.4.3 Starting the IDMA.................................................................................. 7-38
7.6.4.4 Requesting IDMA Transfers.................................................................. 7-39
7.6.4.4.1 Internal Maximum Rate.........................................................................7-39
7.6.4.4.2 Internal Limited Rate.............................................................................7-39
7.6.4.4.3 External Burst Mode..............................................................................7-40
7.6.4.4.4 External Cycle Steal.............................................................................. 7-42
7.6.4.5 IDMA Bus Arbitration............................................................................. 7-43
7.6.4.6 IDMA Operand Transfers......................................................................7-45
7.6.4.6.1 Dual Address Mode...............................................................................7-45
7.6.4.6.2 Single Address Mode (Flyby Transfers)................................................ 7-48
7.6.4.6.3 Fast-Termination Option........................................................................ 7-50
7.6.4.6.4 Externally Recognizing IDMA Operand Transfers................................. 7-51
7.6.4.7 Bus Exceptions...................................................................................... 7-51
7.6.4.7.1 Reset..................................................................................................... 7-51
7.6.4.7.2 Bus Error...............................................................................................7-51
7.6.4.7.3 Retry...................................................................................................... 7-51
7.6.4.8 Ending the IDMA Transfer.....................................................................7-52
7.6.4.8.1 Single Buffer Mode Termination............................................................ 7-52
7.6.4.8.2 Auto Buffer Mode Termination. .............................................................7-53
7.6.4.8.3 Buffer Chaining Mode Termination........................................................ 7-54
7.6.5 IDMA Examples.................................................................................... 7-55
7.6.5.1 Single Buffer Examples.........................................................................7-55
7.6.5.2 Buffer Chaining Example....................................................................... 7-55
7.6.5.3 Auto Buffer Example .............................................................................7-56
7.7 SDMA Channels....................................................................................7-57
7.7.1 SDMA Bus Arbitration and Bus Transfers............................................. 7-57
7.7.2 SDMA Registers.................................................................................... 7-59
7.7.2.1 SDMA Configuration Register (SDCR).................................................. 7-59
7.7.2.2 SDMA Status Register (SDSR)............................................................. 7-61
7.7.2.3 SDMA Address Register (SDAR).......................................................... 7-61
7.8 Serial Interface with Time Slot Assigner................................................ 7-62
7.8.1 SI Key Features.................................................................................... 7-62
7.8.2 TSA Overview ...................................................................................... 7-64
7.8.3 Enabling Connections to the TSA ........................................................7-67
7.8.4 SI RAM................................................................................................. 7-68
7.8.4.1 One Multiplexed Channel with Static Frames ....................................... 7-69
7.8.4.2 One Multiplexed Channel with Dynamic Frames .................................. 7-69
7.8.4.3 Two Multiplexed Channels with Static Frames...................................... 7-70
7.8.4.4 Two Multiplexed Channels with Dynamic Frames................................. 7-71
7.8.4.5 Programming SI RAM Entries...............................................................7-72
7.8.4.6 SI RAM Programming Example ............................................................ 7-75
7.8.4.7 SI RAM Dynamic Changes.................................................................... 7-75
7.8.5 SI Registers...........................................................................................7-77
7.8.5.1 SI Global Mode Register (SIGMR)........................................................ 7-77
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7.8.5.2 SI Mode Register (SIMODE)..................................................................7-78
7.8.5.3 SI Clock Route Register (SICR).............................................................7-86
7.8.5.4 SI Command Register (SICMR).............................................................7-87
7.8.5.5 SI Status Register (SISTR)....................................................................7-87
7.8.5.6 SI RAM Pointers (SIRP).........................................................................7-88
7.8.5.6.1 SIRP When RDM = 00 (One Static TDM)..............................................7-89
7.8.5.6.2 SIRP When RDM = 01 (One Dynamic TDM).........................................7-89
7.8.5.6.3 SIRP When RDM = 10 (Two Static TDMs)............................................7-90
7.8.5.6.4 SIRP When RDM = 11 (Two Dynamic TDMs).......................................7-90
7.8.6 SI IDL Interface Support .......................................................................7-90
7.8.6.1 IDL Interface Example ...........................................................................7-91
7.8.6.2 IDL Interface Programming....................................................................7-95
7.8.7 SI GCI Support......................................................................................7-96
7.8.7.1 SI GCI Activation/Deactivation Procedure.............................................7-98
7.8.7.2 SI GCI Programming..............................................................................7-98
7.8.7.2.1 Normal Mode GCI Programming ...........................................................7-98
7.8.7.2.2 SCIT Programming................................................................................7-98
7.8.8 Serial Interface Synchronization..........................................................7-100
7.8.9 NMSI Configuration..............................................................................7-100
7.9 Baud Rate Generators (BRGs)............................................................7-103
7.9.1 Autobaud Support...............................................................................7-105
7.9.2 BRG Configuration Register (BRGC)..................................................7-106
7.9.3 UART Baud Rate Examples ...............................................................7-108
7.10 Serial Communication Controllers (SCCs)...........................................7-109
7.10.1 SCC Overview .....................................................................................7-110
7.10.2 General SCC Mode Register (GSMR)................................................7-111
7.10.3 SCC Protocol-Specific Mode Register (PSMR)..................................7-120
7.10.4 SCC Data Synchronization Register (DSR)........................................7-121
7.10.5 SCC Transmit on Demand Register (TODR)......................................7-121
7.10.6 SCC Buffer Descriptors.......................................................................7-122
7.10.7 SCC Parameter RAM..........................................................................7-124
7.10.7.1 BD Table Pointer (RBASE, TBASE)....................................................7-125
7.10.7.2 SCC Function Code Registers (RFCR, TFCR)....................................7-125
7.10.7.3 Maximum Receive Buffer Length Register (MRBLR) ..........................7-127
7.10.7.4 Receiver BD Pointer (RBPTR).............................................................7-127
7.10.7.5 Transmitter BD Pointer (TBPTR).........................................................7-127
7.10.7.6 Other General Parameters...................................................................7-128
7.10.8 Interrupts from the SCCs....................................................................7-128
7.10.8.1 SCC Event Register (SCCE) ...............................................................7-128
7.10.8.2 SCC Mask Register (SCCM) ...............................................................7-129
7.10.8.3 SCC Status Register (SCCS) ..............................................................7-129
7.10.9 SCC Initialization.................................................................................7-129
7.10.10 SCC Interrupt Handling........................................................................7-130
7.10.11 SCC Timing Control.............................................................................7-130
7.10.11.1 Synchronous Protocols........................................................................7-130
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7.10.11.2 Asynchronous Protocols......................................................................7-134
7.10.12 Digital Phase-Locked Loop (DPLL).....................................................7-135
7.10.12.1 Data Encoding.....................................................................................7-135
7.10.12.2 DPLL Operation...................................................................................7-136
7.10.13 Clock Glitch Detection......................................................................... 7-139
7.10.14 Disabling the SCCs on the Fly ............................................................7-139
7.10.14.1 SCC Transmitter Full Sequence.......................................................... 7-140
7.10.14.2 SCC Transmitter Shortcut SEQUENCE.............................................. 7-140
7.10.14.3 SCC Receiver Full Sequence..............................................................7-140
7.10.14.4 SCC Receiver Shortcut Sequence......................................................7-141
7.10.14.5 Switching Protocols.............................................................................7-141
7.10.15 Saving Power......................................................................................7-141
7.10.16 UART Controller.................................................................................. 7-141
7.10.16.1 UART Key Features............................................................................7-143
7.10.16.2 Normal Asynchronous Mode...............................................................7-143
7.10.16.3 Synchronous Mode .............................................................................7-144
7.10.16.4 UART Memory Map............................................................................. 7-145
7.10.16.5 UART Programming Model.................................................................7-147
7.10.16.6 UART Command Set........................................................................... 7-147
7.10.16.6.1 Transmit Commands........................................................................... 7-147
7.10.16.6.2 Receive Commands............................................................................ 7-148
7.10.16.7 UART Address Recognition (Receiver)............................................... 7-149
7.10.16.8 UART Control Characters (Receiver).................................................. 7-150
7.10.16.9 Wake-Up Timer (Receiver).................................................................. 7-151
7.10.16.10 Break Support (Receiver)....................................................................7-151
7.10.16.11 Send Break (Transmitter).................................................................... 7-153
7.10.16.12 Sending a Preamble (Transmitter)......................................................7-153
7.10.16.13 Fractional Stop Bits (Transmitter)........................................................ 7-153
7.10.16.14 UART Error-Handling Procedure......................................................... 7-154
7.10.16.14.1 Transmission Error.............................................................................. 7-155
7.10.16.14.2 Reception Errors .................................................................................7-155
7.10.16.15 UART Mode Register (PSMR) ............................................................ 7-156
7.10.16.16 UART Receive Buffer Descriptor (Rx BD)........................................... 7-159
7.10.16.17 UART Transmit Buffer Descriptor (Tx BD).......................................... 7-163
7.10.16.18 UART Event Register (SCCE)............................................................. 7-164
7.10.16.19 UART Mask Register (SCCM)............................................................. 7-167
7.10.16.20 SCC Status Register (SCCS).............................................................. 7-167
7.10.16.21 SCC UART Example........................................................................... 7-167
7.10.16.22 S-Records Programming Example...................................................... 7-169
7.10.17 HDLC Controller.................................................................................. 7-169
7.10.17.1 HDLC Controller Key Features............................................................ 7-170
7.10.17.2 HDLC Channel Frame Transmission Processing................................ 7-171
7.10.17.3 HDLC Channel Frame Reception Processing.....................................7-172
7.10.17.4 HDLC Memory Map............................................................................. 7-172
7.10.17.5 HDLC Programming Model.................................................................7-174
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7.10.17.6 HDLC Command Set...........................................................................7-175
7.10.17.6.1 Transmit Commands............................................................................7-175
7.10.17.6.2 Receive Commands.............................................................................7-176
7.10.17.7 HDLC Error-handling Procedure..........................................................7-176
7.10.17.7.1 Transmission Errors.............................................................................7-176
7.10.17.7.2 Reception Errors..................................................................................7-177
7.10.17.8 HDLC Mode Register (PSMR).............................................................7-178
7.10.17.9 HDLC Receive Buffer Descriptor (Rx BD) ...........................................7-179
7.10.17.10 HDLC Transmit Buffer Descriptor (Tx BD)...........................................7-183
7.10.17.11 HDLC Event Register (SCCE).............................................................7-184
7.10.17.12 HDLC Mask Register (SCCM).............................................................7-186
7.10.17.13 SCC Status Register (SCCS) ..............................................................7-187
7.10.17.14 SCC HDLC Example #1.......................................................................7-187
7.10.17.15 SCC HDLC Example #2.......................................................................7-189
7.10.18 HDLC Bus Controller ...........................................................................7-189
7.10.18.1 HDLC Bus Key Features......................................................................7-192
7.10.18.2 HDLC Bus Operation...........................................................................7-192
7.10.18.2.1 Accessing the HDLC Bus.....................................................................7-192
7.10.18.2.2 More Performance...............................................................................7-193
7.10.18.2.3 Delayed RTS Mode..............................................................................7-194
7.10.18.2.4 Using the TSA......................................................................................7-195
7.10.18.3 HDLC Bus Memory Map and Programming ........................................7-196
7.10.18.3.1 GSMR Programming............................................................................7-196
7.10.18.3.2 PSMR Programming............................................................................7-196
7.10.18.3.3 HDLC Bus Controller Example ............................................................7-196
7.10.19 AppleTalk Controller ............................................................................7-196
7.10.19.1 LocalTalk Bus Operation......................................................................7-197
7.10.19.2 Appletalk Controller Key Features.......................................................7-198
7.10.19.3 QUICC AppleTalk Hardware Connection.............................................7-198
7.10.19.4 AppleTalk Memory Map and Programming Model...............................7-198
7.10.19.4.1 GSMR Programming............................................................................7-199
7.10.19.4.2 PSMR Programming............................................................................7-200
7.10.19.4.3 TODR Programming............................................................................7-200
7.10.19.4.4 AppleTalk Controller Example .............................................................7-200
7.10.20 BISYNC Controller...............................................................................7-200
7.10.20.1 BISYNC Controller Features................................................................7-201
7.10.20.2 BISYNC Channel Frame Transmission ...............................................7-201
7.10.20.3 BISYNC Channel Frame Reception.....................................................7-202
7.10.20.4 BISYNC Memory Map..........................................................................7-203
7.10.20.5 BISYNC Command Set........................................................................7-204
7.10.20.5.1 Transmit Commands............................................................................7-204
7.10.20.5.2 Receive Commands.............................................................................7-205
7.10.20.6 BISYNC Control Character Recognition..............................................7-206
7.10.20.7 BSYNC-BISYNC SYNC Register.........................................................7-207
7.10.20.8 BDLE-BISYNC DLE Register...............................................................7-208
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7.10.20.9 Transmitting and Receiving the Synchronization Sequence...............7-208
7.10.20.10 BISYNC Error-Handling PROCEDURE............................................... 7-209
7.10.20.10.1 Transmission Errors............................................................................7-209
7.10.20.10.2 Reception Errors .................................................................................7-209
7.10.20.11 BISYNC Mode Register (PSMR)......................................................... 7-209
7.10.20.12 BISYNC Receive Buffer Descriptor (Rx BD).......................................7-211
7.10.20.13 BISYNC Transmit Buffer Descriptor (Tx BD)....................................... 7-213
7.10.20.14 BISYNC Event Register (SCCE)......................................................... 7-216
7.10.20.15 BISYNC Mask Register (SCCM)......................................................... 7-217
7.10.20.16 SCC Status Register (SCCS).............................................................. 7-217
7.10.20.17 Programming the BISYNC Controller.................................................. 7-217
7.10.20.18 SCC BISYNC Example .......................................................................7-218
7.10.21 Transparent Controller ........................................................................7-220
7.10.21.1 Transparent Controller Features.........................................................7-221
7.10.21.2 Transparent Channel Frame Transmission Processing...................... 7-221
7.10.21.3 Transparent Channel Frame Reception Processing...........................7-222
7.10.21.4 Achieving Synchronization in Transparent Mode................................7-223
7.10.21.4.1 In-Line Synchronization Pattern..........................................................7-223
7.10.21.4.2 Transparent Synchronization Example ...............................................7-224
7.10.21.5 Transparent Memory Map................................................................... 7-225
7.10.21.6 Transparent Command Set.................................................................7-226
7.10.21.6.1 Transmit Commands........................................................................... 7-226
7.10.21.6.2 Receive Commands............................................................................ 7-227
7.10.21.7 Transparent Error-Handling Procedure............................................... 7-227
7.10.21.7.1 Transmission Errors............................................................................7-227
7.10.21.7.2 Reception Errors .................................................................................7-228
7.10.21.8 Transparent Mode Register (PSMR)................................................... 7-228
7.10.21.9 Transparent Receive Buffer Descriptor (Rx BD).................................7-228
7.10.21.10 Transparent Transmit Buffer Descriptor (Tx BD)................................. 7-230
7.10.21.11 Transparent Event Register (SCCE)................................................... 7-232
7.10.21.12 Transparent Mask Register (SCCM)................................................... 7-233
7.10.21.13 SCC Status Register (SCCS).............................................................. 7-233
7.10.21.14 SCC Transparent Example .................................................................7-233
7.10.22 RAM Microcodes................................................................................. 7-235
7.10.23 Ethernet Controller..............................................................................7-235
7.10.23.1 Ethernet On QUICC—MC68EN360....................................................7-236
7.10.23.2 Ethernet Key Features ........................................................................7-237
7.10.23.3 Learning Ethernet on the QUICC........................................................7-238
7.10.23.4 Connecting QUICC to Ethernet...........................................................7-239
7.10.23.5 Ethernet Channel Frame Transmission............................................... 7-241
7.10.23.6 Ethernet Channel Frame Reception....................................................7-242
7.10.23.7 CAM Interface .....................................................................................7-243
7.10.23.8 Ethernet Memory Map.........................................................................7-246
7.10.23.9 Ethernet Programming Model .............................................................7-250
7.10.23.10 Ethernet Command Set.......................................................................7-250
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7.10.23.10.1 Transmit Commands............................................................................7-250
7.10.23.10.2 Receive Commands.............................................................................7-251
7.10.23.10.3 SET GROUP ADDRESS Command....................................................7-251
7.10.23.11 Ethernet Address Recognition.............................................................7-252
7.10.23.12 Hash Table Algorithm ..........................................................................7-253
7.10.23.13 Interpacket Gap Time ..........................................................................7-254
7.10.23.14 Collision Handling................................................................................7-254
7.10.23.15 Internal and External Loopback...........................................................7-255
7.10.23.16 Ethernet Error-handling Procedure......................................................7-255
7.10.23.16.1 Transmission Errors.............................................................................7-255
7.10.23.16.2 Reception Errors..................................................................................7-256
7.10.23.17 Ethernet Mode Register (PSMR).........................................................7-256
7.10.23.18 Ethernet Receive Buffer Descriptor (Rx BD)........................................7-258
7.10.23.19 Ethernet Transmit Buffer Descriptor (Tx BD).......................................7-261
7.10.23.20 Ethernet Event Register (SCCE) .........................................................7-264
7.10.23.21 Ethernet Mask Register (SCCM) .........................................................7-265
7.10.23.22 Ethernet Status Register (SCCS) ........................................................7-265
7.10.23.23 SCC Ethernet Example........................................................................7-266
7.11 Serial Management Controllers (SMCs)..............................................7-268
7.11.1 SMC Overview.....................................................................................7-268
7.11.2 General SMC Mode Register (SMCMR)..............................................7-270
7.11.3 SMC Buffer Descriptors.......................................................................7-270
7.11.4 SMC Parameter RAM..........................................................................7-270
7.11.4.1 BD Table Pointer (RBASE, TBASE)....................................................7-271
7.11.4.2 SMC Function Code Registers (RFCR, TFCR) ...................................7-272
7.11.4.3 Maximum Receive Buffer Length Register (MRBLR) ..........................7-273
7.11.4.4 Receiver Buffer Descriptor Pointer (RBPTR).......................................7-273
7.11.4.5 Transmitter Buffer Descriptor Pointer (TBPTR)...................................7-274
7.11.4.6 Other General Parameters...................................................................7-274
7.11.5 Disabling the SMCs on the Fly.............................................................7-274
7.11.5.1 SMC Transmitter Full Sequence..........................................................7-275
7.11.5.2 SMC Transmitter Shortcut Sequence..................................................7-275
7.11.5.3 SMC Receiver Full Sequence..............................................................7-275
7.11.5.4 SMC Receiver Shortcut Sequence......................................................7-276
7.11.5.5 Switching Protocols..............................................................................7-276
7.11.6 Saving Power.......................................................................................7-276
7.11.7 SMC as a UART ..................................................................................7-276
7.11.7.1 SMC UART Key Features....................................................................7-276
7.11.7.2 SMC UART Comparison......................................................................7-276
7.11.7.3 SMC UART Memory Map....................................................................7-277
7.11.7.4 SMC UART Transmission Processing.................................................7-278
7.11.7.5 SMC UART Reception Processing......................................................7-279
7.11.7.6 SMC UART Programming Model.........................................................7-279
7.11.7.7 SMC UART Command Set..................................................................7-279
7.11.7.7.1 Transmit Commands............................................................................7-279
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7.11.7.7.2 Receive Commands............................................................................ 7-280
7.11.7.8 Send Break (Transmitter).................................................................... 7-280
7.11.7.9 Sending a Preamble (Transmitter)......................................................7-280
7.11.7.10 SMC UART Error-Handling Procedure................................................ 7-281
7.11.7.10.1 Overrun Error ...................................................................................... 7-281
7.11.7.10.2 Parity Error..........................................................................................7-281
7.11.7.10.3 Idle Sequence Receive .......................................................................7-281
7.11.7.10.4 Framing Error......................................................................................7-281
7.11.7.10.5 Break Sequence..................................................................................7-281
7.11.7.11 SMC UART Mode Register (SMCMR)................................................ 7-281
7.11.7.12 SMC UART Receive Buffer Descriptor (Rx BD).................................. 7-283
7.11.7.13 SMC UART Transmit Buffer Descriptor (Tx BD)................................. 7-286
7.11.7.14 SMC UART Event Register (SMCE)...................................................7-288
7.11.7.15 SMC UART Mask Register (SMCM)................................................... 7-290
7.11.8 SMC UART Example........................................................................... 7-290
7.11.9 SMC Interrupt Handling.......................................................................7-291
7.11.10 SMC as a Transparent Controller........................................................ 7-291
7.11.10.1 SMC Transparent Controller KEY Features........................................ 7-291
7.11.10.2 SMC Transparent Comparison............................................................ 7-292
7.11.10.3 SMC Transparent Memory Map.......................................................... 7-292
7.11.10.4 SMC Transparent Transmission Processing....................................... 7-292
7.11.10.5 SMC Transparent Reception Processing............................................7-293
7.11.10.6 Using the SMSYNx Pin for Synchronization........................................7-293
7.11.10.7 Using the TSA for Synchronization .....................................................7-295
7.11.10.8 SMC Transparent Command Set........................................................7-297
7.11.10.8.1 Transmit Commands........................................................................... 7-297
7.11.10.8.2 Receive Commands............................................................................ 7-297
7.11.10.9 SMC Transparent Error-Handling Procedure...................................... 7-298
7.11.10.9.1 Transmission Error (Underrun)............................................................ 7-298
7.11.10.9.2 Reception Error (Overrun)................................................................... 7-298
7.11.10.10 SMC Transparent Mode Register (SMCMR)....................................... 7-298
7.11.10.11 SMC Transparent Receive Buffer Descriptor (Rx BD)........................ 7-299
7.11.10.12 SMC Transparent Transmit Buffer Descriptor (Tx BD)........................ 7-300
7.11.10.13 SMC Transparent Event Register (SMCE).......................................... 7-302
7.11.10.14 SMC Transparent Mask Register (SMCM).......................................... 7-303
7.11.11 SMC Transparent NMSI Example....................................................... 7-303
7.11.12 SMC Transparent TSA Example......................................................... 7-304
7.11.13 SMC Interrupt Handling.......................................................................7-305
7.11.14 SMC as a GCI Controller..................................................................... 7-305
7.11.14.1 SMC GCI Memory Map....................................................................... 7-306
7.11.14.1.1 SMC Monitor Channel Transmission................................................... 7-306
7.11.14.1.2 SMC Monitor Channel Reception........................................................7-307
7.11.14.2 SMC C/I Channel Handling.................................................................7-307
7.11.14.2.1 SMC C/I Channel Transmission.......................................................... 7-307
7.11.14.2.2 SMC C/I Channel Reception...............................................................7-307
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7.11.14.3 SMC Commands in GCI Mode ............................................................7-307
7.11.14.4 SMC GCI Mode Register (SMCMR)....................................................7-308
7.11.14.5 SMC Monitor Channel Rx BD..............................................................7-309
7.11.14.6 SMC Monitor Channel Tx BD...............................................................7-310
7.11.14.7 SMC C/I Channel Receive Buffer Descriptor (Rx BD).........................7-310
7.11.14.8 SMC C/I Channel Transmit Buffer Descriptor (Tx BD).........................7-311
7.11.14.9 SMC Event Register (SMCE)...............................................................7-311
7.11.14.10 SMC Mask Register (SMCM)...............................................................7-312
7.12 Serial Peripheral Interface (SPI)..........................................................7-312
7.12.1 Overview..............................................................................................7-312
7.12.2 SPI Key Features.................................................................................7-313
7.12.3 SPI Clocking and Pin Functions...........................................................7-314
7.12.4 SPI Transmit/Receive Process............................................................7-315
7.12.4.1 SPI Master Mode.................................................................................7-315
7.12.4.2 SPI Slave Mode...................................................................................7-316
7.12.4.3 SPI Multi-Master Operation..................................................................7-316
7.12.5 SPI Programming Model......................................................................7-317
7.12.5.1 SPI Mode Register (SPMODE)............................................................7-317
7.12.5.2 SPI Command Register (SPCOM).......................................................7-319
7.12.5.3 SPI Parameter RAM Memory Map ......................................................7-320
7.12.5.3.1 BD Table Pointer (RBASE, TBASE)....................................................7-320
7.12.5.3.2 SPI Function Code Registers (RFCR, TFCR)......................................7-321
7.12.5.3.3 Maximum Receive Buffer Length Register (MRBLR) ..........................7-322
7.12.5.3.4 Receiver Buffer Descriptor Pointer (RBPTR).......................................7-322
7.12.5.3.5 Transmitter Buffer Descriptor Pointer (TBPTR)...................................7-323
7.12.5.3.6 Other General Parameters...................................................................7-323
7.12.5.4 SPI Commands....................................................................................7-323
7.12.5.4.1 INIT TX PARAMETERS Command.....................................................7-323
7.12.5.4.2 CLOSE Rx BD Command....................................................................7-323
7.12.5.4.3 INIT RX PARAMETERS Command.....................................................7-323
7.12.5.5 SPI Buffer Descriptor Ring...................................................................7-324
7.12.5.5.1 SPI Receive Buffer Descriptor (Rx BD) ...............................................7-324
7.12.5.5.2 SPI Transmit Buffer Descriptor (Tx BD)...............................................7-326
7.12.5.6 SPI Event Register (SPIE)...................................................................7-328
7.12.5.7 SPI Mask Register (SPIM)...................................................................7-329
7.12.6 SPI Master Example............................................................................7-329
7.12.7 SPI Slave Example..............................................................................7-330
7.12.8 SPI Interrupt Handling..........................................................................7-331
7.13 Parallel Interface Port (PIP).................................................................7-331
7.13.1 PIP Key Features.................................................................................7-331
7.13.2 PIP Overview.......................................................................................7-332
7.13.3 General-Purpose I/O Pins (Port B) ......................................................7-333
7.13.4 Interlocked Data Transfers...................................................................7-333
7.13.5 Pulsed Data Transfers.........................................................................7-334
7.13.5.1 Busy Signal..........................................................................................7-335
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7.13.5.2 Pulsed Handshake Timing ..................................................................7-336
7.13.6 Transparent Data Transfers................................................................7-338
7.13.7 Programming Model............................................................................ 7-338
7.13.7.1 Parameter RAM................................................................................... 7-338
7.13.7.2 PIP Configuration Register (PIPC)...................................................... 7-339
7.13.7.3 PIP Timing Parameters Register (PTPR)............................................ 7-341
7.13.7.4 PIP Buffer Descriptors.........................................................................7-341
7.13.7.5 PIP Event Register (PIPE) ..................................................................7-341
7.13.7.6 PIP Mask Register (PIPM) .................................................................. 7-342
7.13.8 Centronics Controller Overview........................................................... 7-342
7.13.8.1 Centronics Controller Key Features....................................................7-344
7.13.8.2 Centronics Channel Transmission ......................................................7-345
7.13.8.3 Centronics Transmitter Memory Map.................................................. 7-345
7.13.8.4 Buffer Descriptor Table Pointer (TBASE)............................................ 7-346
7.13.8.5 Status Mask Register (SMASK)..........................................................7-346
7.13.8.6 Centronics Function Code Register (CFCR)....................................... 7-346
7.13.8.7 Transmitter Buffer Descriptor Pointer (TBPTR)................................... 7-347
7.13.8.8 Centronics Transmitter Programming Model....................................... 7-347
7.13.8.9 Centronics Transmitter Command Set................................................ 7-347
7.13.8.9.1
STOP TRANSMIT
Command.............................................................. 7-347
7.13.8.9.2
RESTART TRANSMIT
Command....................................................... 7-347
7.13.8.9.3
INIT TX PARAMETERS C
ommand..................................................... 7-348
7.13.8.10 Transmission Errors............................................................................7-348
7.13.8.10.1 Buffer Descriptor Not Ready ...............................................................7-348
7.13.8.10.2 Printer Off-Line Error........................................................................... 7-348
7.13.8.10.3 Printer Fault.........................................................................................7-348
7.13.8.10.4 Paper Error..........................................................................................7-348
7.13.8.10.5 Centronics Transmitter Buffer Descriptor............................................ 7-348
7.13.8.11 Centronics Transmitter Event Register (PIPE).................................... 7-349
7.13.8.12 Centronics Channel Reception............................................................7-350
7.13.8.13 Centronics Receiver Memory Map...................................................... 7-350
7.13.8.14 Buffer Descriptor Table Pointer (RBASE) ...........................................7-351
7.13.8.15 Centronics Function Code Register (CFCR)....................................... 7-351
7.13.8.16 Receiver Buffer Descriptor Pointer (RBPTR)......................................7-352
7.13.8.17 Centronics Receiver Programming Model........................................... 7-352
7.13.8.18 Centronics Control Characters............................................................ 7-352
7.13.8.19 Centronics Silence Period...................................................................7-354
7.13.8.20 Centronics Receiver Command Set....................................................7-354
7.13.8.20.1
INIT RX PARAMETERS
Command....................................................7-354
7.13.8.20.2
CLOSE
RX BD
Command................................................................... 7-354
7.13.8.21 Receiver Errors ...................................................................................7-354
7.13.8.21.1 Buffer Descriptor Busy ........................................................................7-354
7.13.8.22 Centronics Receive Buffer Descriptor.................................................7-354
7.13.8.23 Centronics Receiver Event Register (PIPE)........................................7-355
7.13.9 Port B Registers..................................................................................7-356
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7.13.9.1 Port B Assignment Registers (PBPAR) ...............................................7-356
7.13.9.2 Data Direction Register (PBDIR) .........................................................7-356
7.13.9.3 Data Register (PBDAT)........................................................................7-356
7.13.9.4 Open-Drain Register (PBODR)............................................................7-356
7.14 Parallel I/O Ports..................................................................................7-356
7.14.1 Parallel I/O Key Features.....................................................................7-357
7.14.2 Parallel I/O Overview...........................................................................7-357
7.14.3 Port A Pin Functions............................................................................7-357
7.14.4 Port A Registers...................................................................................7-359
7.14.4.1 Port A Open-Drain Register (PAODR).................................................7-359
7.14.4.2 Port A Data Register (PADAT).............................................................7-359
7.14.4.3 Port A Data Direction Register (PADIR) ..............................................7-359
7.14.4.4 Port A Pin Assignment Register (PAPAR)...........................................7-359
7.14.5 Port A Examples..................................................................................7-360
7.14.6 Port B Pin Functions............................................................................7-362
7.14.7 Port B Registers...................................................................................7-363
7.14.7.1 Port B Open-Drain Register (PBODR).................................................7-363
7.14.7.2 Port B Data Register (PBDAT).............................................................7-364
7.14.7.3 Port B Data Direction Register (PBDIR) ..............................................7-364
7.14.7.4 Port B Pin Assignment Register (PBPAR)...........................................7-364
7.14.8 Port B Example....................................................................................7-365
7.14.9 Port C Pin Functions............................................................................7-365
7.14.10 Port C Registers...................................................................................7-367
7.14.10.1 Port C Data Register (PCDAT)............................................................7-368
7.14.10.2 Port C Data Direction Register (PCDIR)..............................................7-368
7.14.10.3 Port C Pin Assignment Register (PCPAR)...........................................7-368
7.14.10.4 Port C Special Options (PCSO)...........................................................7-368
7.14.10.5 Port C Interrupt Control Register (PCINT)...........................................7-369
7.15 CPM Interrupt Controller (CPIC)..........................................................7-369
7.15.1 Overview..............................................................................................7-370
7.15.2 CPM Interrupt Source Priorities...........................................................7-372
7.15.2.1 SCC Relative Priority...........................................................................7-372
7.15.2.2 Highest Priority Interrupt......................................................................7-372
7.15.2.3 Nested Interrupts .................................................................................7-373
7.15.3 Masking Interrupt Sources in the CPM................................................7-374
7.15.4 Interrupt Vector Generation and Calculation........................................7-375
7.15.5 CPIC Programming Model...................................................................7-377
7.15.5.1 CPM Interrupt Configuration Register (CICR)......................................7-377
7.15.5.2 CPM Interupt Pending Register (CIPR)...............................................7-379
7.15.5.3 CPM Interrupt Mask Register (CIMR)..................................................7-380
7.15.5.4 CPM Interrupt In-Service Register (CISR)...........................................7-380
7.15.6 Interrupt Handler Examples.................................................................7-381
7.15.6.1 Example 1—PC6 Interrupt Handler .....................................................7-381
7.15.6.2 Example 2—SCC1 Interrupt Handler...................................................7-381
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Section 8
Scan Chain Test Access Port
8.1 Overview ................................................................................................. 8-1
8.2 TAP Controller......................................................................................... 8-2
8.3 Boundary Scan Register .........................................................................8-3
8.4 Instruction Register ...............................................................................8-10
8.4.1 EXTEST ................................................................................................ 8-10
8.4.2 SAMPLE/PRELOAD.............................................................................. 8-10
8.4.3 BYPASS................................................................................................ 8-11
8.4.4 CLAMP.................................................................................................. 8-11
8.4.5 HI-Z ....................................................................................................... 8-11
8.5 QUICC Restrictions............................................................................... 8-11
8.6 Non-Scan Chain Operation...................................................................8-12
Section 9
Applications
9.1 Minimum System Configuration .............................................................. 9-1
9.1.1 QUICC Hardware Configuration.............................................................. 9-1
9.1.1.1 QUICC Basic Accesses........................................................................... 9-1
9.1.1.2 Clocking Strategy....................................................................................9-3
9.1.1.3 Resetting the QUICC............................................................................... 9-3
9.1.1.4 Interrupts................................................................................................. 9-3
9.1.1.5 Bus Arbitration.........................................................................................9-3
9.1.1.6 Breakpoint Generation. ...........................................................................9-3
9.1.1.7 Bus Monitor Function. .............................................................................9-3
9.1.1.8 Spurious Interrupt Monitor....................................................................... 9-3
9.1.1.9 Software Watchdog.................................................................................9-3
9.1.1.10 Double Bus Fault.....................................................................................9-4
9.1.1.11 JTAG and Three-State............................................................................9-4
9.1.1.12 QUICC Serial Ports.................................................................................9-4
9.1.2 Memory Interfaces................................................................................... 9-4
9.1.2.1 QUICC Memory Interface Pins................................................................ 9-4
9.1.2.2 Regular EPROM...................................................................................... 9-5
9.1.2.3 Flash EPROM. ........................................................................................ 9-5
9.1.2.4 SRAM...................................................................................................... 9-6
9.1.2.5 EEPROM................................................................................................. 9-7
9.1.2.6 DRAM SIMM. .......................................................................................... 9-8
9.1.2.7 DRAM Devices........................................................................................ 9-9
9.1.3 Software Configuration..........................................................................9-10
9.1.3.1 Basic Initialization..................................................................................9-10
9.1.3.2 Configuring the Memory Controller. ...................................................... 9-11
9.1.3.3 Using the QUICC in 16-Bit Data Bus Mode........................................... 9-12
9.2 How to take A QUICC Software Test-Drive........................................... 9-13
Step 1: Decide on Reset Stack Pointer and Initial Program Counter....9-13
Step 2: Stay in Supervisor Mode...........................................................9-13
Step 3: Write the VBR...........................................................................9-14
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Step 4: Write the MBAR.........................................................................9-14
Step 5: Verify a Dual-Port RAM Location...............................................9-14
Step 6: Is This a Power-Up Reset?........................................................9-14
Step 7: Deal with the Clock Synthesizer................................................9-14
Step 8: Initialize System Protection .......................................................9-15
Step 9: Clear Entire Dual-Port RAM ......................................................9-15
Step 10: Write the PEPAR.....................................................................9-15
Step 11: Remap Chip Select 0...............................................................9-15
Step 12: Initialize the System RAM........................................................9-15
Step 13: Copy the EVT to System RAM................................................9-16
Step 14: Initialize All Other Memory and Peripherals ............................9-16
Step 15: Initialize the Rest of the SIM60................................................9-16
Step 16: Generate a SIM60 Interrupt.....................................................9-16
Step 17: Test the CPM...........................................................................9-17
Step 18: Generate Interrupts with the CPM...........................................9-17
Step 19: Enable External Interrupts.......................................................9-17
Step 20: Enable External Bus Masters..................................................9-18
Step 21: Off to the Races.......................................................................9-18
9.3 Porting MC68302 IMP Code to the MC68360 QUICC...........................9-18
9.3.1 CPU and Compilers...............................................................................9-18
9.3.2 Differences/Similarities ..........................................................................9-18
9.3.3 Notes About Porting...............................................................................9-19
9.3.4 How To Port MC68302 Functions..........................................................9-19
9.3.4.1 System Configuration Registers. ...........................................................9-19
9.3.4.1.1 Base Address Register (BAR). ..............................................................9-19
9.3.4.1.2 System Control Register (SCR).............................................................9-20
9.3.4.2 System RAM..........................................................................................9-21
9.3.4.2.1 Buffer Descriptors..................................................................................9-21
9.3.4.2.2 Protocol-Independent Parameter RAM Values......................................9-21
9.3.4.2.3 Protocol-Dependent Parameter RAM Values........................................9-22
9.3.4.3 Internal Registers (System Integration Block)........................................9-23
9.3.4.4 Internal Registers (Communication Processor).....................................9-26
9.4 Using the QUICC MC68040 Companion Mode.....................................9-31
9.4.1 MC68EC040 to QUICC Interface...........................................................9-32
9.4.1.1 MC68EC040 Reads And Writes to QUICC............................................9-32
9.4.1.2 Clocking Strategy...................................................................................9-34
9.4.1.3 Reset Strategy.......................................................................................9-34
9.4.1.4 Interrupts................................................................................................9-34
9.4.2 Memory Interfaces.................................................................................9-37
9.4.2.1 QUICC Memory Interface Pins. .............................................................9-37
9.4.2.2 Regular EPROM....................................................................................9-38
9.4.2.3 Burst EPROM. .......................................................................................9-38
9.4.2.4 Flash EPROM........................................................................................9-41
9.4.2.5 Regular SRAM.......................................................................................9-41
9.4.2.6 Burst SRAM...........................................................................................9-41
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9.4.2.7 EEPROM............................................................................................... 9-45
9.4.2.8 DRAM SIMM ......................................................................................... 9-45
9.4.2.9 DRAM Devices...................................................................................... 9-46
9.4.3 Software Configuration..........................................................................9-48
9.4.3.1 Basic Initialization..................................................................................9-49
9.4.3.2 Configuring the Memory Controller. ...................................................... 9-49
9.4.4 Interfacing Multiple QUICCs to an MC68EC040...................................9-51
9.5 Selecting Cache Modes on the MC68EC040........................................9-51
9.5.1 The Algorithm........................................................................................ 9-52
9.5.2 Protection.............................................................................................. 9-52
9.5.3 MC68EC040 Cache Behavior...............................................................9-53
9.5.4 Enabling the Caching Modes ................................................................9-53
9.6 Interfacing the QUICC to the 53C90 scsi controller .............................. 9-54
9.6.1 SCSI General Overview........................................................................9-54
9.6.2 Physical Interface..................................................................................9-54
9.6.3 Logical Interface....................................................................................9-59
9.6.4 Functional Description........................................................................... 9-61
9.6.5 Hardware Configuration ........................................................................ 9-62
9.6.5.1 Clocking Strategy..................................................................................9-62
9.6.5.2 Reset Strategy....................................................................................... 9-62
9.6.5.3 Read/Write timing.................................................................................. 9-62
9.6.5.4 Interrupt Handling..................................................................................9-62
9.6.5.5 IDMA1 Setup and Timing......................................................................9-64
9.6.5.6 QUICC I/O Ports.................................................................................... 9-65
9.6.6 Active SCSI Terminations ..................................................................... 9-65
9.6.7 Software Configuration..........................................................................9-65
9.6.7.1 Configuring IDMA1................................................................................ 9-65
9.6.7.2 Configuring The Memory Controller......................................................9-66
9.7 Using the QUICC as a TAP Controller for Board Self-Test................... 9-66
9.7.1 Board Layout.........................................................................................9-67
9.7.2 Board Testing........................................................................................9-68
9.7.3 Microcontroller Interface........................................................................ 9-70
9.7.4 Test Pattern Generation........................................................................9-72
9.8 Interfacing an MC68EC030 Master to the QUICC In Slave Mode ........9-74
9.8.1 MC68EC030 to QUICC Interface..........................................................9-74
9.8.1.1 MC68EC030 Reads and Writes to QUICC............................................ 9-75
9.8.1.2 Clocking Strategy..................................................................................9-75
9.8.1.3 Reset Strategy....................................................................................... 9-77
9.8.1.4 Interrupts............................................................................................... 9-77
9.8.1.5 Bus Arbitration.......................................................................................9-78
9.8.1.6 Breakpoint Generation ..........................................................................9-78
9.8.1.7 Bus Monitor Function ............................................................................9-78
9.8.1.8 Spurious Interrupt Monitor..................................................................... 9-78
9.8.1.9 Software Watchdog...............................................................................9-79
9.8.1.10 Periodic Interval Timer .......................................................................... 9-79
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9.8.1.11 MC68EC030 Caching Configuration......................................................9-79
9.8.1.12 Double Bus Fault ...................................................................................9-79
9.8.1.13 JTAG and Three-State...........................................................................9-79
9.8.1.14 QUICC Serial Ports................................................................................9-79
9.8.2 Memory Interfaces.................................................................................9-79
9.8.2.1 QUICC Memory Interface Pins ..............................................................9-80
9.8.2.2 Regular EPROM or Flash EPROM........................................................9-80
9.8.2.3 Regular SRAM.......................................................................................9-82
9.8.2.4 EEPROM ...............................................................................................9-84
9.8.2.5 DRAM SIMM..........................................................................................9-84
9.8.2.6 DRAM Devices.......................................................................................9-86
9.8.3 Software Configuration ..........................................................................9-86
9.8.3.1 Basic Initialization ..................................................................................9-86
9.8.3.2 Configuring the Memory Controller........................................................9-87
9.8.4 Interfacing Multiple QUICCs to an MC68EC030....................................9-89
9.8.5 Using a Higher Speed MC68EC030 Master with the QUICC................9-89
9.9 Putting a Background Debug Mode Connector on a Target Board .......9-90
Section 10
Electrical Characteristics
10.1 Maximum Ratings..................................................................................10-1
10.2 Thermal Characteristics.........................................................................10-2
10.3 Power Considerations............................................................................10-2
10.4 AC Electrical Specification Definitions...................................................10-3
10.5 DC Electrical Specifications...................................................................10-5
10.6 AC Power Dissipation............................................................................10-6
10.7 AC Electrical Specifications Control Timing...........................................10-7
10.8 External Capacitor for PLL.....................................................................10-8
10.9 Bus Operation AC Timing Specifications...............................................10-9
10.9 Bus Operation AC Timing Specifications (Continued).........................10-10
10.9 Bus Operation AC Timing Specifications (Continued)........................10-11
10.9 Bus Operation AC Timing Specifications (Continued ..........................10-12
10.10 Bus Operation—DRAM Accesses AC Timing Specifications .............10-28
10.11 030/QUICC Bus Type Slave Mode Bus Arbitration AC Electrical Specifica-
tions 10-33
10.12 030/QUICC Bus Type Slave Mode Internal Read/Write/IACK
Asynchronous Cycles AC Electrical Specifications..............................10-36
10.14 030/QUICC Bus Type SRAM/DRAM Cycles AC Electrical Specifications10-
44
10.15 040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications10-49
10.16 040 Bus Type Slave Mode Internal Read/write/IACK Cycles AC Electrical
Specifications10-51
10.17 040 Bus Type SRAM/DRAM Cycles Ac Electrical Specifications.......10-56
10.18 IDMA AC Electrical Specifications......................................................10-62
10.19 PIP/PIO AC Electrical Specifications...................................................10-64
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10.20 Interrupt Controller AC Electrical Specifications.................................. 10-66
10.21 Baud Rate Generator AC Electrical Specifications .............................10-67
10.22 Timer Electrical Specifications ............................................................ 10-68
10.23 SI Electrical Specifications..................................................................10-69
10.24 SCC in NMSI Mode—External Clock Electrical Specifications .......... 10-75
10.25 SCC in NMSI MODE—Internal Clock Electrical Specifications.......... 10-75
10.26 Ethernet Electrical Specifications.......................................................10-77
10.27 SMC Transparent Mode Electrical Specifications..............................10-80
10.28 SPI Master Electrical Specifications...................................................10-82
10.29 SPI Slave Electrical Specifications.....................................................10-83
10.30 JTAG Electrical Specifications ............................................................10-85
Section 11
Ordering Information and Mechanical Data
11.1 Standard Ordering Information..............................................................11-1
11.2 Pin Assignment—240-Lead Quad Flat Pack (QFP).............................. 11-2
11.3 Pin Assignment—241-Lead Pin Grid Array (PGA)................................ 11-4
11.4 Pin Assignment—357-Lead BALL Grid Array (BGA) ............................11-5
11.5 Package Dimensions—CQFP (FE Suffix)............................................. 11-6
11.6 Package Dimensions—PGA (RC Suffix)............................................... 11-7
11.7 Package Dimensions—BGA (ZP Suffix) ............................................... 11-8
Appendix A
Serial Performance
Appendix B
Development Tools and Support
B.1 Motorola Software Modules....................................................................B-1
B.2 Other protocol Software Support............................................................B-5
B.3 Third-Party Software Support.................................................................B-6
B.4 M68360QUADS Development System ...................................................B-6
B.5 Other Development Boards..................................................................B-10
B.6 Direct Target Development ..................................................................B-10
Appendix C
RISC Microcode from RAM
C.1 Signaling System #7 Controller..............................................................C-1
C.1.1 Performance............................................................................................C-2
C.2 Multiple GCI Controller............................................................................C-3
C.2.1 Typical Application ..................................................................................C-3
C.2.2 MGCI Controller Key Features................................................................C-3
C.2.3 Performance............................................................................................C-4
C.3 ATOM1/ATM Controller...........................................................................C-4
C.3.1 Key Features...........................................................................................C-4
C.3.2 Performance............................................................................................C-5
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C.4 Asynchronous HDLC for PPP.................................................................C-6
C.4.1 Key Features...........................................................................................C-6
C.4.2 Performance ...........................................................................................C-7
C.5 PROFIBUS Controller.............................................................................C-7
C.5.1 Key Features...........................................................................................C-7
C.6 Enhanced Ethernet Filtering ...................................................................C-8
C.6.1 Key Features...........................................................................................C-8
C.6.2 Performance ...........................................................................................C-8
Appendix D
MC68MH360 Product Brief
D.1 QUICC32 Key Features..........................................................................D-1
D.1.1 General...................................................................................................D-1
D.1.2 Serial Interface........................................................................................D-2
D.1.3 System Interface.....................................................................................D-2
D.2 QUICC Architecture Overview................................................................D-2
D.2.1 CPU32+ Core..........................................................................................D-3
D.2.2 System Integration Module (SIM60) .......................................................D-4
D.2.3 Communications Processor Module (CPM)............................................D-4
4.2.3.1 QUICC32 Serial Configurations..............................................................D-5
D.2.4 The QMC Microcode...............................................................................D-7
D.2.5 Data Flow................................................................................................D-8
D.2.6 Data Management ..................................................................................D-8
D.2.7 Performance ...........................................................................................D-9
D.2.8 Development Support...........................................................................D-10
D.2.9 Ordering Information.............................................................................D-10
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MC68360 USER’S MANUAL
SECTION 1
INTRODUCTION
The MC68360 QUad Integrated Communication Controller (QUICC
) is a versatile one-
chip integrated microprocessor and peripheral combination that can be used in a variety of
controller applications. It particularly excels in communications activities. The QUICC (pro-
nounced “quick”) can be described as a next-generation MC68302 with higher performance
in all areas of device operation, increased flexibility, major extensions in capability, and
higher integration. The term "quad" comes from the fact that there are four serial communi-
cations controllers (SCCs) on the device; however, there are actually seven serial channels:
four SCCs, two serial management controllers (SMCs), and one serial peripheral interface
(SPI).
The purpose of this document is to describe the operation of all QUICC functionality.
Although this document has an overview of the CPU32+, the M68000PM/AD
M68000 Fam-
ily Programmer's Reference Manual
should be used in addition to this document. The
CPU32RM/AD,
M68300 Family CPU32 Reference Manual,
also provides information on the
CPU32.
1.1 QUICC KEY FEATURES
The following list summarizes the key MC68360 QUICC features:
CPU32+ Processor (4.5 MIPS at 25 MHz)
—32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)
—Background Debug Mode
—Byte-Misaligned Addressing
Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
Up to 32 Address Lines (At Least 28 Always Available)
Complete Static Design (0–25-MHz Operation)
Slave Mode To Disable CPU32+ (Allows Use with External Processors)
—Multiple QUICCs Can Share One System Bus (One Master)
—MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion
Chip and Intelligent Peripheral (22 MIPS at 25 MHz)
—Also Supports External MC68030-Type Bus Masters
—All QUICC Features Usable in Slave Mode
Memory Controller (Eight Banks)
—Contains Complete Dynamic Random-Access Memory (DRAM) Controller
—Each Bank Can Be a Chip Select or Support a DRAM Bank
—Up to 15 Wait States
Thi d t t d ith F M k 4 0 4
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—Glueless Interface to DRAM Single In-Line Memory Modules (SIMMs), Static Ran-
dom-Access Memory (SRAM), Electrically Programmable Read-Only Memory
(EPROM), Flash EPROM, etc.
—Four
CAS
lines, Four
WE
lines, One
OE
line
—Boot Chip Select Available at Reset (Options for 8-, 16-, or 32-Bit Memory)
—Special Features for MC68040 Including Burst Mode Support
Four General-Purpose Timers
—Superset of MC68302 Timers
—Four 16-Bit Timers or Two 32-Bit Timers
—Gate Mode Can Enable/Disable Counting
Two Independent DMAs (IDMAs)
—Single Address Mode for Fastest Transfers
—Buffer Chaining and Auto Buffer Modes
—Automatically Performs Efficient Packing
—32-Bit Internal and External Transfers
System Integration Module (SIM60)
—Bus Monitor
—Double Bus Fault Monitor
—Spurious Interrupt Monitor
—Software Watchdog
—Periodic Interrupt Timer
—Low Power Stop Mode
—Clock Synthesizer
—Breakpoint Logic Provides On-Chip Hardware Breakpoints
—External Masters May Use On-Chip Features Such As Chip Selects
—On-Chip Bus Arbitration with No Overhead for Internal Masters
—IJTAG Test Access Port
Interrupts
—Seven External
IRQ
Lines
—12 Port Pins with Interrupt Capability
—16 Internal Interrupt Sources
—Programmable Priority Between SCCs
—Programmable Highest Priority Request
Communications Processor Module (CPM)
—RISC Controller
—Many New Commands (e.g., Graceful Stop Transmit, Close RxBD)
—224 Buffer Descriptors
—Supports Continuous Mode Transmission and Reception on All Serial Channels
—2.5 Kbytes of Dual-Port RAM
—14 Serial DMA (SDMA) Channels
—Three Parallel I/O Registers with Open-Drain Capability
—Each Serial Channel Can Have Its Own Pins (NMSI Mode)
Four Baud Rate Generators
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—Independent (Can Be Connected to Any SCC or SMC)
—Allows Changes During Operation
—Autobaud Support Option
Four SCCs
—Ethernet/IEEE 802.3 Optional on SCC1 (Full 10-Mbps Support)
—HDLC/SDLC
1
(All Four Channels Supported at 2 Mbps)
—HDLC Bus (Implements an HDLC-Based Local Area Network (LAN))
—AppleTalk
2
—Signaling System #7
—Universal Asynchronous Receiver Transmitter (UART)
—Synchronous UART
—Binary Synchronous Communication (BISYNC)
—Totally Transparent (Bit Streams)
—Totally Transparent (Frame Based with Optional Cyclic Redundancy Check (CRC))
—Profibus (RAM Microcode Option)
—Asynchronous HDLC
(RAM Microcode Option)
—DCMP
3
(RAM Microcode Option)
—V.14 (RAM Microcode Option)
—X.21 (RAM Microcode Option)
Two SMCs
—UART
—Transparent
—General Circuit Interface (GCI) Controller
—Can Be Connected to the Time-Division Multiplexed (TDM) Channels
One SPI
—Superset of the MC68302 SCP
—Supports Master and Slave Modes
—Supports
Multimaster Operation on the Same Bus
Time-Slot Assigner
Supports Two TDM Channels
—Each TDM Channel Can Be T1, CEPT, PCM Highway, ISDN Basic Rate,
ISDN Primary Rate, User Defined
—1- or 8-Bit Resolution
—Allows
Independent Transmit and Receive Routing, Frame Syncs, Clocking
—Allows
Dynamic Changes
—Can Be internally Connected to Six Serial Channels (Four SCCs and
Two SMCs)
1.
SDLC is a trademark of International Business Machines.
2.
AppleTalk is a registered trademark of Apple Computer, Inc.
3.
DDCMP is a trademark of Digital Equipment Corporation.
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Parallel Interface Port
—Centronics
4
Interface Support
—Supports Fast Connection Between QUICCs
240 Pins Defined: 241-Lead Pin Grid Array (PGA) and 240-Lead Plastic Quad Flat Pack
(PQFP)
1.2 QUICC ARCHITECTURE OVERVIEW
The QUICC is 32-bit controller that is an extension of other members of the Motorola
M68300 family. Like other members of the M68300 family, the QUICC incorporates the inter-
module bus (IMB). (The MC68302 is an exception, having an M68000 bus on chip.) The IMB
provides a common interface for all modules of the M68300 family, which allows Motorola
to develop new devices more quickly by using the library of existing modules. Although the
IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first
device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM.
Each module utilizes the 32-bit IMB. The MC68360 QUICC block diagram is shown in Figure
1-1.
Figure 1-1. QUICC Block Diagram
4.
Centronics is a trademark of Centronics, Inc.
EXTERNAL
BUS
INTERFACE
SYSTEM
PROTECTION
SIM 60
CPU32+
CORE
IMB (32 BIT)
RISC
CONTROLLER
SYSTEM
I/F
2.5-KBYTE
DUAL-PORT
RAM
DRAM
CONTROLLER
AND
CHIP SELECTS
CPM
PERIODIC
TIMER
CLOCK
GENERATION
OTHER
FEATURES
BREAKPOINT
LOGIC
JTAG
COMMUNICATIONS PROCESSOR
FOUR
GENERAL-
PURPOSE
TIMERS
INTERRUPT
CONTROLLER
OTHER
FEATURES
TIMER SLOT
ASSIGNER
SEVEN
SERIAL
CHANNELS
TWO
IDMAs FOURTEEN SERIAL
DMAs
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1.2.1 CPU32+ Core
The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB
and apply the larger bus width. Although the original CPU32 core had a 32-bit internal data
path and 32-bit arithmetic hardware, its interface to the IMB was 16 bits. The CPU32+ core
can operate on 32-bit external operands with one bus cycle. This allows the CPU32+ core
to fetch a long-word instruction in one bus cycle and to fetch two word-length instructions in
one bus cycle, filling the internal instruction queue more quickly. The CPU32+ core can also
read and write 32-bits of data in one bus cycle.
Although the CPU32+ instruction timings are improved, its instruction set is identical to that
of the CPU32. It will also execute the entire M68000 instruction set. It contains the same
background debug mode (BDM) features as the CPU32. No new compilers, assemblers, or
other software support tools need be implemented for the CPU32+; standard CPU32 tools
can be used.
The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted)
assumption that a 10-MHz M68000 delivers 1 VAX MIPS. If an application requires more
performance, the CPU32+ can be disabled, allowing the rest of the QUICC to operate as an
intelligent peripheral to a faster processor. The QUICC provides a special mode called
MC68040 companion mode to allow it to conveniently interface to members of the M68040
family. This two-chip solution provides a 22-MIPS performance at 25 MHz.
The CPU32+ also offers automatic byte alignment features that are not offered on the
CPU32. These features allow 16 or 32-bit data to be read or written at an odd address. The
CPU32+ automatically performs the number of bus cycles required.
1.2.2 System Integration Module (SIM60)
The SIM60 integrates general-purpose features that would be useful in almost any 32-bit
processor system. The term “SIM60” is derived from the QUICC part number, MC68360.
The SIM60 is an enhanced version of the SIM40 that exists on the MC68340 and MC68330
devices.
First, new features, such as a DRAM controller and breakpoint logic, have been added. Sec-
ond, the SIM40 was modified to support a 32-bit IMB as well as a 32-bit external system bus.
Third, new configurations, such as slave mode and internal accesses by an external master,
are supported.
Although the QUICC is always a 32-bit device internally, it may be configured to operate with
a 16-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is
supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-
bit system bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system
bus mode.
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1.2.3 Communications Processor Module (CPM)
The CPM contains features that allow the QUICC to excel in communications and control
applications. These features may be divided into three sub-groups:
Communications Processor (CP)
Two IDMA Controllers
Four General-Purpose Timers
The CP provides the communication features of the QUICC. Included are a RISC processor,
four SCCs, two SMCs, one SPI, 2.5 Kbytes of dual-port RAM, an interrupt controller, a time
slot assigner, three parallel ports, a parallel interface port, four independent baud rate gen-
erators, and fourteen serial DMA channels to support the SCCs, SMCs, and SPI.
The IDMAs provide two channels of general-purpose DMA capability. They offer high-
speed transfers, 32-bit data movement, buffer chaining, and independent request and
acknowledge logic. The RISC controller may access the IDMA registers directly in the buffer
chaining modes. The QUICC IDMAs are similar to, yet enhancements of, the two DMA chan-
nels found on the MC68340 and the one IDMA channel found on the MC68302.
The four general-purpose timers on the QUICC are functionally similar to the two general-
purpose timers found on the MC68302. However, they offer some minor enhancements,
such as the internal cascading of two timers to form a 32-bit timer. The QUICC also contains
a periodic interval timer in the SIM60, bringing the total to five on-chip timers.
1.3 UPGRADING DESIGNS FROM THE MC68302
Since the QUICC is a next-generation MC68302, many designers currently using the
MC68302 may wish to use the QUICC in a follow-on design. The following paragraphs
briefly discuss this endeavor in terms of architectural approach, hardware issues, and soft-
ware issues. See Section 9 Applications for further information.
1.3.1 Architectural Approach
The QUICC is the logical extension of the MC68302, but the overall architecture and philos-
ophy of the MC68302 design remains intact in the QUICC. The QUICC keeps the best fea-
tures of the MC68302, while making the changes required to provide for the increased
flexibility, integration, and performance requested by customers. Because the CPM is prob-
ably the most difficult module to learn, anyone who has used the MC68302 can easily
become familiar with the QUICC since the CPM architectural approach remains intact.
The most significant architectural change made on the QUICC was the translation of the
design into the standard M68300 family IMB architecture, resulting in a faster CPU and dif-
ferent system integration features.
Although the features of the SIM60 do not exactly correspond to those of the MC68302 SIM,
they are very similar. The QUICC SIM60 combines the best MC68302 SIM features with the
best MC68340 SIM features for improved performance.
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Because of the similarity of the QUICC SIM60 and CPU to other members of the M68300
family, such as the MC68332 and the MC68340, previous users of these devices will be
comfortable with these same features on the QUICC.
1.3.2 Hardware Compatibility Issues
The following list summarizes the hardware differences between the MC68302 and the
QUICC:
Pinout—The pinout is not the same. The QUICC has 240 pins; the MC68302 has 132
pins.
Package—Both devices offer PGA and PQFP packages. However, the QUICC
PQFP package has a 20-mil pitch; whereas, the MC68302 PQFP package has a
25-mil pitch.
System Bus—The system bus signals now look like those of the MC68030 as opposed
to those of the M68000. It is still possible to interface M68000 peripherals to the QUICC,
utilizing the same techniques used to interface them to an MC68020 or MC68030.
System Bus in Slave Mode—A number of QUICC pins take on new functionality in slave
mode to support an external MC68EC040. On the MC68302, the pin names generally
remained the same in slave mode.
Peripheral Timing—The external timings of the peripherals (SCCs, timers, etc.) are very
similar (if not identical) to corresponding peripherals on the MC68302.
Pin Assignments—The assignment of peripheral functions to I/O pins is different in sev-
eral ways. First, the QUICC contains more general-purpose parallel I/O pins than the
MC68302. However, the QUICC offers many more functions than even a 240-pin pack-
age would normally allow, resulting in more multifunctional pins than the MC68302.
1.3.3 Software Compatibility Issues
The following list summarizes the major software differences between the MC68302 and the
QUICC:
Since the CPU32+ is a superset of the M68000 instruction set, all previously written
code will run. However, if such code is accessing the MC68302 peripherals, it will re-
quire some modification.
The QUICC contains an 8-Kbyte block of memory as opposed to a 4-Kbyte block
on the MC68302. The register addresses within that memory map are different.
The code used to initialize the system integration features of the MC68302 has
to be modified to write the corresponding features on the QUICC SIM60. Code written
for the MC68340 may be adapted in large part.
As much as possible, QUICC CPM features were made identical to those of the
MC68302 CP. The most important benefit is that the code flow (if not the code itself) will
port easily from the MC68302 to the QUICC. The nuances learned from the MC68302
will still be useful in the QUICC.
Although the registers used to initialize the QUICC CPM are new (for example, the SCM
on the MC68302 is replaced with the GSMR and PSMR on the QUICC), most registers
retain their original purpose such as the SCC event, SCC mask, SCC status, and com-
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mand registers. The parameter RAM of the SCCs is very similar, and most parameter
RAM register names and usage are retained. More importantly, the basic structure of a
buffer descriptor (BD) on the QUICC is identical to that of the MC68302, except for a
few new bit functions that were added. (In a few cases, a bit in a BD status word had to
be shifted.)
When porting code from the MC68302 CP to the QUICC CPM, the software writer may
find that the QUICC has new options to simplify what used to be a more code-intensive
process. For specific examples, see the INIT TX AND RX PARAMETERS, GRACEFUL
STOP TRANSMIT, and CLOSE BD commands.
1.4 QUICC GLUELESS SYSTEM DESIGN
A fundamental design goal of the QUICC was ease of interface to other system components.
An example of this goal is a minimal QUICC design using EPROM and DRAM, shown in Fig-
ure 1-2.
This system interfaces gluelessly to an EPROM and a DRAM SIMM module. It also
offers parity support for the DRAM.
Figure 1-2. Minimum QUICC System Configuration
Figure 1-3 shows a larger system configuration. This system offers one EPROM, one flash
EPROM, and supports two DRAM SIMMs. Depending on the capacitance on the system
bus, external buffers may be required. From a logic standpoint, however, a glueless system
is maintained.
QUICC
MC68360
CE (ENABLE)
OE (OUTPUT ENABLE)
WE (WRITE)
DATA
ADDRESS
8-BIT BOOT
EPROM
(FLASH OR REGULAR)
CS0
OE 
WE0
DATA
ADDRESS
RAS
CAS3–CAS0
W (WRITE)
DATA
ADDRESS
PARITY
16- OR 32-BIT 
DRAM SIMM
(OPTIONAL PARITY)
RAS1
CAS3–CAS0
R/W
PRTY3–PRTY0
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