Introduction Thank you for selecting National Semiconductor products. National Semiconductor's products find wide use in applications ranging from the latest personal computers to lightweight portable consumer products. As next generation electronic systems require higher levels of performance, device functionality has rapidly increased as wafer level features have migrated down to dimensions of 0.35 m and lower. To meet the increasing demand of device complexity and functionality, package technology has evolved to provide the necessary interconnection and performance in the desired form factor. Growing markets for network servers and cellular phones are just two examples demanding newer package technologies. Standard leadframe-based packages are stretched to the limit as higher package I/O counts or the smallest possible package size are required. Array type package configurations are emerging as a technical solution of choice to fulfill these requirements. Ball Grid Array (BGA) packages have gained acceptance for high I/O count (200) devices and are becoming increasingly desirable for lower package lead count devices. BGA packaging has also been driving the implementation of advanced interconnect technologies: flip chip and fine pitch wire bonding. Flip chip technologies allow for the simultaneous formation of a large number of solder interconnects between the device and the package. Wire bond processes are advancing to allow tighter and tighter pitches, with 70 m pitch for ball bonds and 60 m pitch for wedge bonds available in production. In recent years, numerous Chip Scale Package (CSP) designs have been introduced to the market, mainly providing solutions for increased device functionality in the smallest size possible. At the forefront of CSP array package concept is National Semiconductor's wafer-level CSP, micro-SMD. The micro-SMD is the latest innovation stretching the limits of the die size package concept. This package is based on a leadless design where both the interconnection and encapsulation are applied to the die at the wafer-level. In certain applications, these new package technologies are preferred to standard ceramic or plastic packages. Furthermore, the ever-increasing use of smaller and thinner packages to house highly integrated, high-density devices challenges the existing package designs for achieving the desired thermal performance. Modified leadframe designs and exposed die attach pad (DAP) are just two solutions for thermally enhancing thin, small packages. Reliability performance of plastic packages continues to improve, providing customers the highest assurances of quality and performance. Advancements in mold compound and die attach materials minimize moisture uptake and lower package stresses for components subjected to rigorous environmental test conditions. These new materials have been critical to the successful implementation of thin (1.4 mm or less) packages. National continues to offer a diverse family of plastic and hermetic packaging options to its customers. Through-hole mounting incorporates packages with leads arranged unidirectionally (SIP and ZIP), bidirectionally (DIP), and in a bristling matrix (PGA). On the other hand, surface mounting in(c) 2000 National Semiconductor Corporation cludes two classes of packages: Flat packages that have leads aligned bidirectionally (SOP, SSOP, TSOP and TSSOP), or on all four sides (QFP); and Chip Carriers that can be leadless (LCC), or have leads either bidirectionally (SOJ) or 4-way (PLCC). This edition of the National Semiconductor Packaging Databook provides a concise guide to all the available packaging options. Aside from dimensional footprints following JEDEC and EIAJ standards, thermal resistance data are also included. The databook is organized as follows: Section 1 The various package types and families are described together with the packaging technology trends. A brief description of the most efficient way to use the databook is also provided. Section 2 Information on plastic-encapsulated packages is given. The basic package characteristics such as availability charts, dimensional data, thermal data, and lead finish type and composition are provided. A limited amount of electrical data can be found in the package electrical characterization section of the Appendix. Section 3 Information similar to those provided in Section 2 is available for hermetic packages. Section 4 Information on National Semiconductor's Ball Grid Array (BGA) packaging is presented in this section. Section 5 The micro-SMD package is described including information on package construction, thermal data, package handling, and surface mount considerations. Section 6 Laminate-based CSPs are covered in this section. Information includes thermal data, thermal data, package handling, and surface mount considerations. Section 7 The Semiconductor Packaging Assembly technology process is described in this section. Packages covered include Plastic Leadframe-packages, Plastic Ball Grid Array (PBGA), Hermetic packages, and Multi-chip packages. The process of adoption of new technologies is also reviewed. Section 8 General reliability issues dealing with plastic-encapsulated packages are addressed. This includes the test standards to www.national.com Introduction August 1999 Introduction Section 8 Appendix (Continued) qualify new packages, typical failure modes encountered in integrated circuits, and preconditioning handling procedures for packages prior to board assembly. Section 9 General information on packing carriers (e.g. tubes, trays, etc.) and packing materials is provided. Recycling of packing materials is an important topic that is discussed in this section. Application notes on thermal measurement considerations are given, together with a description of basic electrical measurement techniques and a limited summary of electrical data for packages. Guidelines for component marking are also described. Although great care has been taken to prepare this Manual, some omissions may exist. If the reader should require any further clarification, please contact your National Semiconductor representative. We strive for continuous improvement and complete customer satisfaction. Section 10 Surface mount assembly flows and process-related reliability concerns are outlined. The information covers array type packages. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.