SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D
Support Live Insertion
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
description
These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The eight latches of the ’LVT573 are transparent D-type latches. While the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low , the Q outputs are latched at the logic levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect the internal operations of the latches.
Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74L VT573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54L VT573 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LVT573 is characterized for operation from –40°C to 85°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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20
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OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54LVT573 ...J OR W PACKAGE
SN74LVT573 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q 1Q
8D
GND
LE VCC
SN54LVT573 . . . FK PACKAGE
(TOP VIEW)
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.