Low Power, High Slew Rate,
Wide Bandwidth, JFET Input
Operational Amplifiers
Quality bipolar fabrication with innovative design concepts are employed
for the MC33181/2/4, MC34181/2/4 series of monolithic operational
amplifiers. This JFET input series of operational amplifiers operates at
210 µA per amplifier and offers 4.0 MHz of gain bandwidth product and
10 V/µs slew rate. Precision matching and an innovative trim technique of
the single and dual versions provide low input offset voltages. With a JFET
input stage, this series exhibits high input resistance, low input offset voltage
and high gain. The all NPN output stage, characterized by no deadband
crossover distortion and large output voltage swing, provides high
capacitance drive capability, excellent phase and gain margins, low open
loop high frequency output impedance and symmetrical source/sink AC
frequency response.
The MC33181/2/4, MC34181/2/4 series of devices are specified over the
commercial or industrial/vehicular temperature ranges. The complete series
of single, dual and quad operational amplifiers are available in the plastic
DIP as well as the SOIC surface mount packages.
Low Supply Current: 210 µA (Per Amplifier)
Wide Supply Operating Range: ±1.5 V to ±18 V
Wide Bandwidth: 4.0 MHz
High Slew Rate: 10 V/µs
Low Input Offset Voltage: 2.0 mV
Large Output Voltage Swing: –14 V to +14 V (with ±15 V Supplies)
Large Capacitance Drive Capability: 0 pF to 500 pF
Low Total Harmonic Distortion: 0.04%
Excellent Phase Margin: 67°
Excellent Gain Margin: 6.7 dB
Output Short Circuit Protection
Offered in New TSSOP Package Including the Standard SOIC and
DIP Packages
ORDERING INFORMATION
Op Amp
Function Device Operating
Temperature Range Package
Single MC34181P
MC34181D TA = 0° to +70°CPlastic DIP
SO–8
MC33181P
MC33181D TA = –40° to +85°CPlastic DIP
SO–8
Dual MC34182P
MC34182D TA = 0° to +70°CPlastic DIP
SO–8
MC33182P
MC33182D TA = –40° to +85°CPlastic DIP
SO–8
Quad MC34184P
MC34184D
MC34184DTB TA = 0° to +70°CPlastic DIP
SO–14
TSSOP–14
MC33184P
MC33184D
MC33184DTB TA = –40° to +85°CPlastic DIP
SO–14
TSSOP–14
ON Semiconductor
Semiconductor Components Industries, LLC, 2002
March, 2002 – Rev. 2 1 Publication Order Number:
MC34181/D
MC34181,2,4
MC33181,2,4
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
P SUFFIX
PLASTIC PACKAGE
CASE 626
P SUFFIX
PLASTIC PACKAGE
CASE 646
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
PIN CONNECTIONS
(Single, Top View)
(Dual, Top View)
(Quad, Top View)
4
23
1
PIN CONNECTIONS
Offset Null
VEE
VEE
Inputs 1
Output 1
Inputs
NC
VCC
Output
Offset Null
Inputs 2
Output 2
VCC
1
2
3
4
8
7
6
5
+
1
2
3
4
8
7
6
5
1
2
1
2
3
4
5
6
78
9
10
11
12
13
14
Inputs 1
Output 1
VCC
Inputs 2
Output 2
Output 4
Inputs 4
VEE
Inputs 3
Output 3
-
+
-
+
-
+
---
+
+
-
+
-
1
81
8
14
114 1
DTB SUFFIX
PLASTIC PACKAGE
CASE 948G
(TSSOP–14)
14
1
MC34181,2,4 MC33181,2,4
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2
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (from VCC to VEE) VS+36 V
Input Differential Voltage Range VIDR Note 1 V
Input Voltage Range VIR Note 1 V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Operating Junction Temperature TJ+150 °C
Storage Temperature Range Tstg –60 to +150 °C
NOTES: 1.Either or both input voltages should not exceed the magnitude of VCC or VEE.
2.Power dissipation must be considered to ensure maximum junction temperature (TJ) is not
exceeded (see Figure 1).
Q8
Internal
Bias
Network
Neg Pos
VCC
VO
VEE
J1J2
Q9
Q7
D3
D1
C1
R6
D2R7
C2
Q4
Q6
Q5
I4
R5
R4
R2
Q3
I3
R3
R1
Q2
Q1
Null Offsets
MC3X181 (Single) Only
15
1
5
VEE
MC3X181 Input Offset
Voltage Null CIrcuit
25 k
-
+
+
Representative Schematic Diagram
(Each Amplifier)
MC34181,2,4 MC33181,2,4
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3
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (RS = 50 , VO = 0 V)
Single
TA = +25°C
TA = 0° to +70°C (MC34181)
TA = –40° to +85°C (MC33181)
Dual
TA = +25°C
TA = 0° to +70°C (MC34182)
TA = –40° to +85°C (MC33182)
Quad
TA = +25°C
TA = 0° to +70°C (MC34184)
TA = –40° to +85°C (MC33184)
VIO
0.5
1.0
4.0
2.0
3.0
3.5
3.0
4.0
4.5
10
11
11.5
mV
Average Temperature Coefficient of VIO (RS = 50 , VO = 0V) VIO/T 10 µV/°C
Input Offset Current (VCM = 0 V, VO = 0V)
TA = +25°C
TA = 0° to +70°C
TA = –40° to +85°C
IIO
0.001
0.05
1.0
2.0
nA
Input Bias Current (VCM = 0 V, VO = 0V)
TA = +25°C
TA = 0° to +70°C
TA = –40° to +85°C
IIB
0.003
0.1
2.0
4.0
nA
Input Common Mode Voltage Range VICR (VEE +4.0 V) to (VCC –2.0 V) V
Large Signal Voltage Gain (RL = 10 k, V O = ±10 V)
TA = +25°C
TA = Tlow to Thigh
AVOL 25
15 60
V/mV
Output Voltage Swing (VID = 1.0 V, RL = 10 k)
TA = +25°CVO+
VO+13.5
+14
–14
–13.5 V
Common Mode Rejection (RS = 50 , VCM = VICR, VO = 0 V) CMR 70 86 dB
Power Supply Rejection (RS = 50 , VCM = 0 V, VO = 0 V) PSR 70 84 dB
Output Short Circuit Current (VID = 1.0 V, Output to Ground)
Source
Sink
ISC 3.0
8.0 8.0
11
mA
Power Supply Current (No Load, VO = 0 V)
Single
TA = +25°C
TA = Tlow to Thigh
Dual
TA = +25°C
TA = Tlow to Thigh
Quad
TA = +25°C
TA = Tlow to Thigh
ID
210
420
840
250
250
500
500
1000
1000
µA
MC34181,2,4 MC33181,2,4
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4
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Slew Rate (Vin = –10 V to +10 V, RL = 10 k, CL = 100 pF)
AV = +1.0
AV = –1.0
SR 7.0
10
10
V/µs
Settling Time (AV = –1.0, RL = 10 k, VO = 0 V to +10 V Step)
To Within 0.10%
To Within 0.01%
ts
1.1
1.5
µs
Gain Bandwidth Product (f = 100 kHz) GBW 3.0 4.0 MHz
Power Bandwidth (AV = +1.0, RL = 10 k, VO = 20 Vpp, THD = 5.0%) BWp 120 kHz
Phase Margin (–10 V < VO < +10 V)
RL = 10 k
RL = 10 k, CL = 100 pF
fm
67
34
Degrees
Gain Margin (–10 V < VO < +10 V)
RL = 10 k
RL = 10 k, CL = 100 pF
Am
6.7
3.4
dB
Equivalent Input Noise Voltage
RS = 100 , f = 1.0 kHz en 38 nV/ Hz
Equivalent Input Noise Current
f = 1.0 kHz in 0.01 pA/ Hz
Differential Input Capacitance Ci 3.0 pF
Differential Input Resistance Ri 1012 W
Total Harmonic Distortion
AV = 10, RL = 10 k, 2.0 Vpp < VO < 20 Vpp, f = 1.0 kHz THD 0.04 %
Channel Separation (RL = 10 k, –10 V < VO < +10 V, 0 Hz < f < 10 kHz) 120 dB
Open Loop Output Impedance
(f = 1.0 MHz) |Zo| 200
8/14 Pin
Plastic
SO-8
SO-14
Figure 1. Maximum Power Dissipation versus
Temperature for Package Variations Figure 2. Input Common Mode Voltage Range
versus Temperature
TA, AMBIENT TEMPERATURE (°C)
D
P, MAXIMUM POWER DISSIPATION (mW)
-55 -40 -20 0 20 40 60 80 100 120 140 160
TA, AMBIENT TEMPERATURE (°C)
ICR
V , INPUT COMMON MODE VOLTAGE
RANGE (V)
-55 -25 0 25 50 75 100 125
VCC = +3.0 V to +15 V
VEE = -3.0 V to -15 V
VIO = 5.0 mV
VCC (VCM to VCC)
VEE
2400
2000
1600
1200
800
400
0
0
-1.0
-2.0
3.0
2.0
1.0
0
TSSOP-14
MC34181,2,4 MC33181,2,4
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5
VEE
VCC
VCC = +15 V
VEE = -15 V
TA = +25°C
Figure 3. Input Bias Current
versus Temperature Figure 4. Input Bias Current versus
Input Common Mode Voltage
Figure 5. Output Voltage Swing
versus Supply Voltage Figure 6. Output Saturation Voltage
versus Load Current
Figure 7. Output Saturation Voltage versus
Load Resistance to Ground Figure 8. Output Saturation Voltage versus
Load Resistance to VCC
TA, AMBIENT TEMPERATURE (°C)
IB
I, INPUT BIAS CURRENT (nA)
-55 -25 0 25 50 75 100 125
VCC = +15 V
VEE = -15 V
VCM = 0 V
VICR, INPUT COMMON MODE VOLTAGE (V)
-10 -5.0 0 5.0 10
VCC = +15 V
VEE = -15 V
TA = 25°C
VCC, |VEE|, SUPPLY VOLTAGE (V)
0 2.0 4.0 6.0 8.0 10 12 14 16
VO, OUTPUT VOLTAGE SWING (V)
RL Connected to Ground
TA = 25°C
RL = 10 k
IL, LOAD CURRENT (mA)
Sink
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
VCC = +15 V
VEE = -15 V
TA = +25°C
Source
sat
V , OUTPUT SATURATION VOLTAGE (V)
RL, LOAD RESISTANCE TO GROUND ()
1.0 k 10 k 100 k 1.0 M
VEE
VCC
VCC = +15 V
VEE = -15 V
TA = +25°C
RL, LOAD RESISTANCE ()
1.0 k 10 k 100 k 1.0 M
VCC
VEE
sat
V , OUTPUT SATURATION VOLTAGE (V) sat
V , OUTPUT SATURATION VOLTAGE (V) IB
I, INPUT BIAS CURRENT (nA)
1000
100
10
1.0
0.1
0.01
0.001
20
15
10
5
0
40
30
20
10
0
0
-1.0
-2.0
-3.0
+3.0
+2.0
+1.0
0
0
-1.0
-2.0
-3.0
3.0
2.0
1.0
0
0
-1.0
-2.0
-3.0
3.0
2.0
1.0
0
MC34181,2,4 MC33181,2,4
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6
100
10
1.0
AV = 1000
VCC = +15 V
VEE = -15 V
VO = 2.0 Vpp
RL = 10 k
TA = 25°C
VCC = +15 V
VEE = -15 V
RL = 10 k
THD = 1.0%
TA = 25°C
100 10
AV = 1000 1.0
VCC = +15 V
VEE = -15 V
VCM = 0 V
VO = 0 V
IO = 10 µA
TA = 25°C
A , OPEN LOOP VOLTAGE GAIN (dB)
Figure 9. Output Short Circuit Current
versus Temperature Figure 10. Output Impedance versus Frequency
Figure 11. Output Voltage Swing
versus Frequency Figure 12. Output Distortion versus
Frequency
Figure 13. Open Loop Voltage Gain
versus Temperature Figure 14. Open Loop Voltage Gain and
Phase versus Frequency
TA, AMBIENT TEMPERATURE (°C)
SC
I, OUTPUT SHORT CIRCUIT CURRENT (mA)
-55 -25 0 25 50 75 100 125
Sink
Source
VCC = +15 V
VEE = -15 V
RL 0.1
VID = 1.0 V
f, FREQUENCY (Hz)
O
|Z|, OUTPUT IMPEDANCE ()
100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)
1.0 k 10 k 109 k 1.0 M
,
VOOUTPUT VOLTAGE SWING (Vp-p
)
f, FREQUENCY (Hz)
THD, TOTAL HARMONIC DISTORTION (%)
10 100 1.0 k 10 k 100 k
VOL
A, OPEN LOOP VOLTAGE GAIN (V/mV)
TA, AMBIENT TEMPERATURE (°C)
-55 -25 0 25 50 75 100 125
f, FREQUENCY (Hz)
VOL
1.0 10 100 1.0 k 10 k 1.0 M 10 M 100 M100 k
Phase
Gain
, EXCESS PHASE
(
DEGREES
)
φ
30
20
10
0
300
200
100
0
30
24
18
12
6
0
1.0
0.8
0.6
0.4
0.2
0
70
60
50
40
30
20
100
80
60
40
20
0
VCC = +15 V
VEE = -15 V
RL = 10 k
f 10 Hz
TA = 25°C
VCC = +15 V
VEE = -15 V
VO = 0 V
RL = 10 k
TA = 25°C
0
45
90
135
180
MC34181,2,4 MC33181,2,4
http://onsemi.com
7
CL = 100 pF
CL = 10 pF
VCC = +15 V
VEE = -15 V
RL = 10 kto
-10 V < VO < +10 V
Figure 15. Normalized Gain Bandwidth
Product versus Temperature Figure 16. Output Voltage Overshoot
versus Load Capacitance
Figure 17. Phase Margin versus
Load Capacitance Figure 18. Gain Margin versus
Load Capacitance
Figure 19. Phase Margin
versus Temperature Figure 20. Gain Margin
versus Temperature
TA, AMBIENT TEMPERATURE (°C)
GBW, GAIN BANDWIDTH PRODUCT (NORMALIZED)
-55 -25 0 25 50 75 100 125
CL, LOAD CAPACITANCE (pF)
OS
V, OUTPUT VOLTAGE OVERSHOOT (%)
10 100 1.0 k
CL, LOAD CAPACITANCE (pF)
, PHASE MARGIN (DEGREES)
φm
10 100 1.0 k
CL, LOAD CAPACITANCE (pF)
Am, GAIN MARGIN (dB)
10 100 1.0 k
, PHASE MARGIN (DEGREES)
φm
-55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
CL = 100 pF
CL = 10 pF
Am, GAIN MARGIN (dB)
-55 -25 0 25 50 75 100 125
1.3
1.2
1.1
0.9
0.8
0.7
1.0
100
80
60
40
20
0
70
60
50
40
30
20
10
0
10
8.0
6.0
4.0
2.0
0
70
60
50
40
30
20
10
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
VCC = +15 V
VEE = -15 V
RL = 10 k
VCC = +15 V
VEE = -15 V
RL = 10 k
VO = 100 mVpp
-10 V < VO < +10 V
AV = +1.0
TA = 25°C
VCC = +15 V
VEE = -15 V
RL = 10 kto
-10 V < VO < +10 V
TA = 25°C
VCC = +15 V
VEE = -15 V
RL = 10 kto
-10 V < VO < +10 V
TA = 25°C
VCC = +15 V
VEE = -15 V
RL = 10 kto
-10 V < VO < +10 V
MC34181,2,4 MC33181,2,4
http://onsemi.com
8
+PSR (VCC = ±1.5 V)
-PSR (VEE = ±1.5 V)
+PSR = 20Log VO/ADM
VCC
-PSR = 20Log VO/ADM
VEE
VCC = +15 V
VEE = -15 V
TA = 25°C
VCC
VEE
ADM
-
+VO
|I|, I , SUPPLY CURRENT (NORMALIZED)
Figure 21. Normalized Slew Rate
versus Temperature Figure 22. Common Mode Rejection
versus Frequency
Figure 23. Input Noise Voltage
versus Frequency Figure 24. Power Supply Rejection
versus Temperature
Figure 25. Power Supply Rejection
versus Frequency Figure 26. Normalized Supply Current
versus Supply Voltage
TA, AMBIENT TEMPERATURE (°C)
SR, SLEW RATE (NORMALIZED)
-55 -25 0 25 50 75 100 125
f, FREQUENCY (Hz)
CMR, COMMON MODE REJECTION (dB)
100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)
en, INPUT NOISE VOLTAGE ()
10 100 1.0 k 10 k 100 k
nV/ Hz
TA < AMBIENT TEMPERATURE (°C)
PSR, POWER SUPPLY REJECTION (dB)
-55 -25 0 25 50 75 100 125
Positive Supply
Negative Supply
VCC, VEE = 3.0 V
f 10 Hz
f, FREQUENCY (Hz)
PSR, POWER SUPPLY REJECTION (dB)
100 1.0 k 10 k 100 k 1.0 M
VCC, |VEE|, SUPPLY VOLTAGE (V)
EE CC
0 5.0 10 15 20
TA = 25°C
125°C
-55°C
1.1
1.0
0.9
0.8
0.7
0.6
0.5
140
120
100
80
60
40
20
0
100
80
60
40
20
0
110
100
90
80
140
120
100
80
60
40
20
0
1.2
1.1
1.0
0.9
0.8
0.7
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 10 k
CL = 100 pF
Vin = -10 V to +10 V
VCC = +15 V
VEE = -15 V
VCM = 3.0 V
TA = 25°C
VCC = +15 V
VEE = -15 V
VCM = 0 V
TA = 25°C
VCC = +15 V
VEE = -15 V
TA = 25°C
RL =
VO = 0V
CMR = 20 Log
ADM
-
+
VCM VO
X ADM
VCM
VO
MC34181,2,4 MC33181,2,4
http://onsemi.com
9
Figure 27. Channel Separation versus Frequency Figure 28. Transient Response
Figure 29. Small Signal Transient Reponse
f, FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
10 k 100 k 1.0 M 10 M
VCC = +15 V
VEE = -15 V
TA = +25°C
O
V, OUTPUT VOLTAGE (5.0 V/DIV)
t, TIME (2.0 µs/DIV)
O
V, OUTPUT VOLTAGE (20 mV/DIV)
t, TIME (0.5 µs/DIV)
VCC = +15 V
VEE = -15 V
RL = 10 k
AV = +1.0
TA = 25°C
VCC = +15 V
VEE = -15 V
RL = 10 k
AV = +1.0
TA = 25°C
140
120
100
80
60
40
20
0
MC34181,2,4 MC33181,2,4
http://onsemi.com
10
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
OUTLINE DIMENSIONS
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040

SEATING
PLANE
1
4
58
A0.25 MCB SS
0.25 MBM
h
C
X 45
L
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.10 0.25
B0.35 0.49
C0.18 0.25
D4.80 5.00
E
1.27 BSCe
3.80 4.00
H5.80 6.20
h
0 7
L0.40 1.25
0.25 0.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
EH
A
Be
B
A1
CA
0.10
MC34181,2,4 MC33181,2,4
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11
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
OUTLINE DIMENSIONS – continued
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
17
14 8
B
A
F
HG D K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L0.300 BSC 7.62 BSC
M0 10 0 10
N0.015 0.039 0.39 1.01

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
 
MC34181,2,4 MC33181,2,4
http://onsemi.com
12
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MC34181/D
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