ON Semiconductor MC34181,2,4 MC33181,2,4 Low Power, High Slew Rate, Wide Bandwidth, JFET Input Operational Amplifiers Quality bipolar fabrication with innovative design concepts are employed for the MC33181/2/4, MC34181/2/4 series of monolithic operational amplifiers. This JFET input series of operational amplifiers operates at 210 A per amplifier and offers 4.0 MHz of gain bandwidth product and 10 V/s slew rate. Precision matching and an innovative trim technique of the single and dual versions provide low input offset voltages. With a JFET input stage, this series exhibits high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. The MC33181/2/4, MC34181/2/4 series of devices are specified over the commercial or industrial/vehicular temperature ranges. The complete series of single, dual and quad operational amplifiers are available in the plastic DIP as well as the SOIC surface mount packages. * Low Supply Current: 210 A (Per Amplifier) * * * * * * * * * * * 8 8 1 1 P SUFFIX PLASTIC PACKAGE CASE 626 D SUFFIX PLASTIC PACKAGE CASE 751 (SO-8) PIN CONNECTIONS Offset Null Inputs VEE NC 1 8 2 - 7 VCC 3 + 6 Output 5 Offset Null 4 (Single, Top View) Output 1 Wide Supply Operating Range: 1.5 V to 18 V Inputs 1 Wide Bandwidth: 4.0 MHz + 3 VEE High Slew Rate: 10 V/s 1 2 1 2 4 8 VCC 7 Output 2 6 + Inputs 2 5 (Dual, Top View) Low Input Offset Voltage: 2.0 mV Large Output Voltage Swing: -14 V to +14 V (with 15 V Supplies) Large Capacitance Drive Capability: 0 pF to 500 pF Low Total Harmonic Distortion: 0.04% 14 Excellent Phase Margin: 67 14 1 1 Excellent Gain Margin: 6.7 dB Output Short Circuit Protection Offered in New TSSOP Package Including the Standard SOIC and DIP Packages D SUFFIX PLASTIC PACKAGE CASE 751A (SO-14) P SUFFIX PLASTIC PACKAGE CASE 646 14 1 ORDERING INFORMATION Op Amp Function Single Dual Quad Device Operating Temperature Range Package MC34181P MC34181D TA = 0 to +70C Plastic DIP SO-8 MC33181P MC33181D TA = -40 to +85C Plastic DIP SO-8 MC34182P MC34182D TA = 0 to +70C Plastic DIP SO-8 MC33182P MC33182D TA = -40 to +85C Plastic DIP SO-8 MC34184P MC34184D MC34184DTB TA = 0 to +70C Plastic DIP SO-14 TSSOP-14 MC33184P MC33184D MC33184DTB TA = -40 to +85C Semiconductor Components Industries, LLC, 2002 March, 2002 - Rev. 2 Plastic DIP SO-14 TSSOP-14 1 DTB SUFFIX PLASTIC PACKAGE CASE 948G (TSSOP-14) PIN CONNECTIONS Output 1 Inputs 1 1 2 3 VCC Inputs 2 Output 2 14 + 1 4 -+ 4 5 6 13 2 3 + - 7 Inputs 4 12 11 + - Output 4 10 VEE Inputs 3 9 8 Output 3 (Quad, Top View) Publication Order Number: MC34181/D MC34181,2,4 MC33181,2,4 MAXIMUM RATINGS Rating Symbol Value Unit VS +36 V Input Differential Voltage Range VIDR Note 1 V Input Voltage Range VIR Note 1 V Output Short Circuit Duration (Note 2) tSC Indefinite sec Operating Junction Temperature TJ +150 C Storage Temperature Range Tstg -60 to +150 C Supply Voltage (from VCC to VEE) NOTES: 1. Either or both input voltages should not exceed the magnitude of V CC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 1). Representative Schematic Diagram (Each Amplifier) VCC Internal Bias Network Neg Q8 Q9 J1 J2 Q7 Pos D1 C1 D3 + R6 Q1 Q2 R2 Q5 I3 R4 R3 1 R7 C2 Q3 R1 VEE D2 Q4 Q6 I4 R5 5 Null Offsets MC3X181 (Single) Only + 5 1 25 k MC3X181 Input Offset Voltage Null CIrcuit http://onsemi.com 2 VEE VO MC34181,2,4 MC33181,2,4 DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristics Symbol Input Offset Voltage (RS = 50 , VO = 0 V) Single TA = +25C TA = 0 to +70C (MC34181) TA = -40 to +85C (MC33181) Dual TA = +25C TA = 0 to +70C (MC34182) TA = -40 to +85C (MC33182) Quad TA = +25C TA = 0 to +70C (MC34184) TA = -40 to +85C (MC33184) Min Typ Max VIO Average Temperature Coefficient of VIO (RS = 50 , VO = 0V) VIO/T Input Offset Current (VCM = 0 V, VO = 0V) TA = +25C TA = 0 to +70C TA = -40 to +85C IIO Input Bias Current (VCM = 0 V, VO = 0V) TA = +25C TA = 0 to +70C TA = -40 to +85C IIB Input Common Mode Voltage Range VICR Large Signal Voltage Gain (RL = 10 k, VO = 10 V) TA = +25C TA = Tlow to Thigh AVOL Output Voltage Swing (VID = 1.0 V, RL = 10 k) TA = +25C Unit mV -- -- -- 0.5 -- -- 2.0 3.0 3.5 -- -- -- 1.0 -- -- 3.0 4.0 4.5 -- -- -- 4.0 -- -- 10 11 11.5 -- 10 -- -- -- -- 0.001 -- -- 0.05 1.0 2.0 -- -- -- 0.003 -- -- 0.1 2.0 4.0 V/C nA nA (VEE +4.0 V) to (VCC -2.0 V) V V/mV 25 15 60 -- -- -- VO+ VO- +13.5 -- +14 -14 -- -13.5 V Common Mode Rejection (RS = 50 , VCM = VICR, VO = 0 V) CMR 70 86 -- dB Power Supply Rejection (RS = 50 , VCM = 0 V, VO = 0 V) PSR 70 84 -- dB 3.0 8.0 8.0 11 -- -- Output Short Circuit Current (VID = 1.0 V, Output to Ground) Source Sink ISC Power Supply Current (No Load, VO = 0 V) Single TA = +25C TA = Tlow to Thigh ID mA A -- -- 210 -- 250 250 -- -- 420 -- 500 500 -- -- 840 -- 1000 1000 Dual TA = +25C TA = Tlow to Thigh Quad TA = +25C TA = Tlow to Thigh http://onsemi.com 3 MC34181,2,4 MC33181,2,4 AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristics Symbol Slew Rate (Vin = -10 V to +10 V, RL = 10 k, CL = 100 pF) AV = +1.0 AV = -1.0 Min Typ Max SR Settling Time (AV = -1.0, RL = 10 k, VO = 0 V to +10 V Step) To Within 0.10% To Within 0.01% Unit V/s 7.0 -- 10 10 -- -- -- -- 1.1 1.5 -- -- s ts Gain Bandwidth Product (f = 100 kHz) GBW 3.0 4.0 -- MHz Power Bandwidth (AV = +1.0, RL = 10 k, VO = 20 Vpp, THD = 5.0%) BWp -- 120 -- kHz -- -- 67 34 -- -- -- -- 6.7 3.4 -- -- Phase Margin (-10 V < VO < +10 V) RL = 10 k RL = 10 k, CL = 100 pF fm Gain Margin (-10 V < VO < +10 V) RL = 10 k RL = 10 k, CL = 100 pF Am Equivalent Input Noise Voltage RS = 100 , f = 1.0 kHz en -- 38 -- nV/ Hz Equivalent Input Noise Current f = 1.0 kHz in -- 0.01 -- pA/ Hz Differential Input Capacitance Ci -- 3.0 -- pF Differential Input Resistance Ri -- 1012 -- W THD -- 0.04 -- % Channel Separation (RL = 10 k, -10 V < VO < +10 V, 0 Hz < f < 10 kHz) -- -- 120 -- dB Open Loop Output Impedance (f = 1.0 MHz) |Zo| -- 200 -- Total Harmonic Distortion AV = 10, RL = 10 k, 2.0 Vpp < VO < 20 Vpp, f = 1.0 kHz P, D MAXIMUM POWER DISSIPATION (mW) Figure 1. Maximum Power Dissipation versus Temperature for Package Variations V ICR, INPUT COMMON MODE VOLTAGE RANGE (V) 2000 8/14 Pin Plastic TSSOP-14 SO-14 1200 800 SO-8 400 0 -55 -40 -20 dB Figure 2. Input Common Mode Voltage Range versus Temperature 2400 1600 Degrees 0 -1.0 VCC (VCM to VCC) -2.0 3.0 2.0 1.0 0 20 40 60 80 100 120 140 160 TA, AMBIENT TEMPERATURE (C) http://onsemi.com 4 VCC = +3.0 V to +15 V VEE = -3.0 V to -15 V VIO = 5.0 mV 0 -55 VEE -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 MC34181,2,4 MC33181,2,4 Figure 3. Input Bias Current versus Temperature Figure 4. Input Bias Current versus Input Common Mode Voltage 20 VCC = +15 V VEE = -15 V VCM = 0 V 100 10 I, IB INPUT BIAS CURRENT (nA) I, IB INPUT BIAS CURRENT (nA) 1000 1.0 0.1 0.01 0.001 -55 -25 0 25 50 75 100 V sat , OUTPUT SATURATION VOLTAGE (V) 5.0 10 4.0 6.0 8.0 V sat , OUTPUT SATURATION VOLTAGE (V) 10 12 14 0 VCC -1.0 VCC = +15 V VEE = -15 V TA = +25C -2.0 -3.0 Source +3.0 +2.0 Sink +1.0 0 16 VEE 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 VCC, |VEE|, SUPPLY VOLTAGE (V) IL, LOAD CURRENT (mA) Figure 7. Output Saturation Voltage versus Load Resistance to Ground Figure 8. Output Saturation Voltage versus Load Resistance to VCC 0 V sat , OUTPUT SATURATION VOLTAGE (V) VO, OUTPUT VOLTAGE SWING (V) 10 VCC -3.0 VCC -2.0 -3.0 3.0 2.0 VEE 10 k 0 10 -1.0 VCC = +15 V VEE = -15 V TA = +25C -2.0 0 1.0 k 0 Figure 6. Output Saturation Voltage versus Load Current RL = 10 k 1.0 -5.0 Figure 5. Output Voltage Swing versus Supply Voltage 20 -1.0 5 VICR, INPUT COMMON MODE VOLTAGE (V) 30 2.0 10 TA, AMBIENT TEMPERATURE (C) RL Connected to Ground TA = 25C 0 15 0 -10 125 40 0 VCC = +15 V VEE = -15 V TA = 25C 100 k 1.0 M 3.0 VCC = +15 V VEE = -15 V TA = +25C 2.0 1.0 0 1.0 k RL, LOAD RESISTANCE TO GROUND () VEE 10 k 100 k RL, LOAD RESISTANCE () http://onsemi.com 5 1.0 M MC34181,2,4 MC33181,2,4 20 VCC = +15 V VEE = -15 V RL 0.1 VID = 1.0 V 300 200 Sink 10 -25 0 25 50 75 100 0 100 125 100 1.0 k 10 k 100 k 1.0 M Figure 11. Output Voltage Swing versus Frequency Figure 12. Output Distortion versus Frequency 18 12 6 0 1.0 k 10 k 109 k 1.0 THD, TOTAL HARMONIC DISTORTION (%) VCC = +15 V VEE = -15 V RL = 10 k THD = 1.0% TA = 25C 0.8 0.6 VCC = +15 V VEE = -15 V VO = 2.0 Vpp RL = 10 k TA = 25C AV = 1000 0.4 100 0.2 10 1.0 0 10 1.0 M 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 13. Open Loop Voltage Gain versus Temperature Figure 14. Open Loop Voltage Gain and Phase versus Frequency 70 100 A VOL, OPEN LOOP VOLTAGE GAIN (dB) A, VOL OPEN LOOP VOLTAGE GAIN (V/mV) 1.0 f, FREQUENCY (Hz) 24 60 50 40 VCC = +15 V VEE = -15 V RL = 10 k f 10 Hz TA = 25C 30 20 -55 10 TA, AMBIENT TEMPERATURE (C) 30 VO ,OUTPUT VOLTAGE SWING (V p-p ) AV = 1000 100 Source 0 -55 VCC = +15 V VEE = -15 V VCM = 0 V VO = 0 V IO = 10 A TA = 25C -25 0 25 50 75 100 125 80 VCC = +15 V VEE = -15 V VO = 0 V RL = 10 k TA = 25C Gain 60 Phase 45 40 90 20 135 0 1.0 TA, AMBIENT TEMPERATURE (C) 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) http://onsemi.com 6 0 , EXCESS PHASE (DEGREES) 30 Figure 10. Output Impedance versus Frequency |Z|, O OUTPUT IMPEDANCE () I, SC OUTPUT SHORT CIRCUIT CURRENT (mA) Figure 9. Output Short Circuit Current versus Temperature 1.0 M 10 M 180 100 M Figure 15. Normalized Gain Bandwidth Product versus Temperature V, OS OUTPUT VOLTAGE OVERSHOOT (%) 1.3 VCC = +15 V VEE = -15 V RL = 10 k 1.2 1.1 1.0 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125 20 0 10 100 10 50 40 30 20 m 10 10 100 1.0 k 8.0 6.0 4.0 2.0 100 1.0 k CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF) Figure 19. Phase Margin versus Temperature Figure 20. Gain Margin versus Temperature 10 CL = 10 pF 60 9.0 50 40 CL = 100 pF 30 VCC = +15 V VEE = -15 V RL = 10 k to -10 V < VO < +10 V 20 -25 VCC = +15 V VEE = -15 V RL = 10 k to -10 V < VO < +10 V TA = 25C 0 10 1.0 k A m, GAIN MARGIN (dB) 40 Figure 18. Gain Margin versus Load Capacitance 70 m , PHASE MARGIN (DEGREES) 60 Figure 17. Phase Margin versus Load Capacitance VCC = +15 V VEE = -15 V RL = 10 k to -10 V < VO < +10 V TA = 25C 10 -55 80 VCC = +15 V VEE = -15 V RL = 10 k VO = 100 mVpp -10 V < VO < +10 V AV = +1.0 TA = 25C CL, LOAD CAPACITANCE (pF) 60 0 100 TA, AMBIENT TEMPERATURE (C) 70 , PHASE MARGIN (DEGREES) Figure 16. Output Voltage Overshoot versus Load Capacitance A m, GAIN MARGIN (dB) GBW, GAIN BANDWIDTH PRODUCT (NORMALIZED) MC34181,2,4 MC33181,2,4 0 25 50 8.0 CL = 10 pF 7.0 6.0 5.0 CL = 100 pF 4.0 3.0 VCC = +15 V VEE = -15 V RL = 10 k to -10 V < VO < +10 V 2.0 1.0 75 100 0 -55 125 TA, AMBIENT TEMPERATURE (C) -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) http://onsemi.com 7 100 125 MC34181,2,4 MC33181,2,4 Figure 21. Normalized Slew Rate versus Temperature Figure 22. Common Mode Rejection versus Frequency CMR, COMMON MODE REJECTION (dB) SR, SLEW RATE (NORMALIZED) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -55 VCC = +15 V VEE = -15 V AV = +1.0 RL = 10 k CL = 100 pF Vin = -10 V to +10 V -25 0 25 50 75 100 125 PSR, POWER SUPPLY REJECTION (dB) 20 0 10 100 1.0 k 10 k VO X ADM 60 40 20 0 100 1.0 k 10 k 100 k 1.0 M 110 Positive Supply 100 VCC, VEE = 3.0 V f 10 Hz 90 Negative Supply -25 0 25 50 75 100 f, FREQUENCY (Hz) TA < AMBIENT TEMPERATURE (C) Figure 25. Power Supply Rejection versus Frequency Figure 26. Normalized Supply Current versus Supply Voltage 140 +PSR = 20Log VO/ADM VCC -PSR = 20Log VO/ADM VEE +PSR (VCC = 1.5 V) -PSR (VEE = 1.5 V) 60 VCC = +15 V VEE = -15 V TA = 25C 0 100 VO VCM CMR = 20 Log 80 80 -55 100 k |I|, EE I CC , SUPPLY CURRENT (NORMALIZED) en , INPUT NOISE VOLTAGE () nV/ Hz PSR, POWER SUPPLY REJECTION (dB) 40 20 ADM Figure 24. Power Supply Rejection versus Temperature 60 40 + Figure 23. Input Noise Voltage versus Frequency 80 80 100 - VCM f, FREQUENCY (Hz) VCC = +15 V VEE = -15 V VCM = 0 V TA = 25C 100 VCC = +15 V VEE = -15 V VCM = 3.0 V TA = 25C 120 TA, AMBIENT TEMPERATURE (C) 100 120 140 1.0 k ADM + VCC VO VEE 10 k 100 k 1.0 M 1.2 1.1 TA = 25C 1.0 125C 0.9 -55C VCC = +15 V VEE = -15 V TA = 25C RL = VO = 0V 0.8 0.7 0 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) f, FREQUENCY (Hz) http://onsemi.com 8 125 20 MC34181,2,4 MC33181,2,4 Figure 27. Channel Separation versus Frequency Figure 28. Transient Response 100 80 60 40 20 VCC = +15 V VEE = -15 V TA = +25C 0 10 k VCC = +15 V VEE = -15 V RL = 10 k AV = +1.0 TA = 25C V, O OUTPUT VOLTAGE (5.0 V/DIV) 120 100 k 1.0 M 10 M t, TIME (2.0 s/DIV) f, FREQUENCY (Hz) Figure 29. Small Signal Transient Reponse VCC = +15 V VEE = -15 V RL = 10 k AV = +1.0 TA = 25C V, O OUTPUT VOLTAGE (20 mV/DIV) CHANNEL SEPARATION (dB) 140 t, TIME (0.5 s/DIV) http://onsemi.com 9 MC34181,2,4 MC33181,2,4 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE K 8 5 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. -B- 1 4 F DIM A B C D F G H J K L M N -A- NOTE 2 L C J -T- N SEATING PLANE D M K MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10 0.030 0.040 G H 0.13 (0.005) M T A M B M D SUFFIX PLASTIC PACKAGE CASE 751-05 (SO-8) ISSUE R D A 8 E 5 0.25 H 1 M B M 4 h B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C e X 45 A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S http://onsemi.com 10 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.18 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 MC34181,2,4 MC33181,2,4 OUTLINE DIMENSIONS - continued P SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE L 14 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F DIM A B C D F G H J K L M N L C J N H G D SEATING PLANE K M INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0 10 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0 10 0.39 1.01 D SUFFIX PLASTIC PACKAGE CASE 751A-03 (SO-14) ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G M B M F R X 45 C -T- SEATING PLANE 0.25 (0.010) M T B J M K D 14 PL S A S http://onsemi.com 11 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC34181,2,4 MC33181,2,4 ON Semiconductor is a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). 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