VSC8140 - Vitesse Semiconductor - Datasheet.Technology

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SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Features

General Description

The VSC8140 is a SONET/SDH compatible transceiver with integrated clock generator for use in SONET/

SDH systems operating at a 2.48832Gb/s data rate. The internal clock generator uses a Phase-Locked Loop

(PLL) to mult iply ei th er a 77. 76MHz or 155.5 2MHz r efe rence cl ock i n order to provide t he 2.488 32GHz clo c k

for internal logic and output retiming. The 16-bit parallel interface incorporates an on-board FIFO eliminating

loop timing design issues by providing a f lexible parallel timing architecture. In a ddition, the device pr ovides

both facility and equipment loopback modes and two loop timing modes. The VSC8140 operates using a 3.3V

power supply, and is available in either a thermally -enhance d 128-PQFP or a thermally-enha nced 208-pin

TBGA package.

VSC8140 Block Diagram

• 2.48832Gb/s 16-Bit Transceiver

• Targeted for SONET OC-48 / SDH STM-16

Applic ations

• LVPECL Low-Speed Interface

• On-chip PLL-Based Clock Generator

• High-Speed Clock Output With Power-Down

Option

• Supports P arity at the 16-Bit Par allel T ransmit

and Receive Interfaces

• Pr ovides Eq uipment, Facilities and Split Loo p-

back Modes as well as Loop Timing Modes

• Loss of Signal (LOS) Detect input

• Meets Bellcore Jitter Performance Specifications

• Single +3.3V Supply

• 2.25 Watts Typical Power Dissipation

• Packages: 128-pin PQFP or 208-pin TBGA

RXOUT15

TXIN15

RXOUT0

RXPARITYOUT

RXCLK16O+

RXCLK16O-

RXCLKIN+

RXCLKIN-

Output R egi st er

RXCLKO16_32+

RXCLKO16_32-

Divide by

TXIN0

TXPARITYIN

TXCLK16O+

TXCLK16O-

TXOUT+

TXOUT-

Input Register

Divide by

REFCLK+

REFCLK-

2.48832GHz

PLL

TXCLK16I+

TXCLK16I-

Q D

FACLOOP

LOOPTIM0

FIFO

CNTRL

FIFORESET

Divide by

EQULOOP

D Q

RXIN+

RXIN-

TXCLKOUT+

TXCLKOUT-

LPTIMCLK+

LPTIMCLK-

Write

Pointer

Read

Pointer

16x5 FIFO

PARERR

LOS

POL

OVERFLOW

VREFOUT

voltage

gen.

REF_FREQSEL

LOOPTIM1

PARMODE

RXCLKO_FREQSEL

VREFIN

CLK128O+

CLK128O- Divide

by 128

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SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 2 

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G52251-0, Rev. 4.0

Functional Description

Transmitter Low-Speed Interface

The Upstream Device should use the TXCLK16O as the timing source for its final output latch (see Figure

1). The Upstream Device should then generate a TXCLK16I that is phase-aligned with the data. The VSC8140

will latch TXIN[15:0]± on the rising edge of TXCLK16I+. The data must meet setup and ho ld times with

respect to TXCLK16I (see Table 1).

A FIFO exists within the VS C8140 to elimina te difficult system loop timing issues. Once the PLL has

locked to the reference clock, RESET must be held low for a m inimum of five CLK16 cycles to initialize the

FIFO, then RESET should be se t high and held constant for continuous FIFO op eration. For the transparen t

mode of operation (no FIFO), simply hold RESET at a constant low state (see Figure 2).

The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between

TXCLK16O and TXCLK16I. Once RESET is asserted and the FIFO initialized, the delay between TXCLK16O

and TXCLK16I can dec rease or increase up to one period of th e low-spee d clock (6.4ns). Should this delay dri ft

exceed one period, the write pointer and the read pointer could point to the same word in the FIFO, resulting in

a loss of tra nsm itte d d ata ( a FIFO o verf low). In the e ven t o f a FIF O ove rflow, an activ e low OV ERF LO W sig-

nal is asserted (for a minimum of five TXCLK16I cycles) which can be used to initiate a reset signal from an

external cont rolle r.

The TX CLK16O± output driver is a LVPECL output driver designed to drive a 50Ω tran sm ission line. The

transmissio n line can be DC termin ated wit h a spli t-end t erminat ion scheme (see F igure 3), or DC terminat ed by

50Ω to VCC-2V on each line (see Figure 4). At any time, the equivalent split-end termination technique can be

substituted for the traditional 50Ω to VCC-2V on each line. AC-coup li ng can be achieved by a number of met h-

ods. Figure 5 ill ustrates an AC-c oupling met hod for the occasi on when the downstr eam device provid es the bias

point for AC-coupling.

Figure 1: Low-Speed Systems Interface

write

read

16 x 5 FIFO

VSC8140

2.48832GHz

PLL

REFCLK Div 16

TXCLK16I

TXCLK16O

OVERFLOW

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SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Figure 2: Enabling FIFO Operation

Figure 3: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs

Figure 4: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs

Minimum 5 CLK16 cycles FIFO Mode Operation

Transparent Mo de Operation

Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation.

Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.

PLL locked to reference clock.

RESET

VSC8140

ZoR2 R2

R1 R1

VEE

VCC

VCCR2 + VEER1

R1+R2 = VTERM

downstream

R1||R2 = ZO

Split-e nd e quivalent termination is ZO to VTERM

R1 = 125Ω R2 = 83Ω, ZO=50Ω, VTERM= VCC-2V

VCC-2V

R1 =50Ω

VSC8140 Zo

VCC-2V

R1 =50Ω

downstream

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SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

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G52251-0, Rev. 4.0

Figure 5: AC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs

Receiver Lo w-Speed Interface

The demultiplexed serial stream is made available by a 16-bit single-ended LVPECL interface

RXOUT[15:0] with accompanying differential LVPECL divide-by-16 clock RXCLK16O± and selectable

LVPECL divide-by-16 or -32 clock RXCLK16_32O±.

RXCLKO_FREQSEL is used to select RXCLK16_32O±. RXCLKO_FREQSEL = “0” designates

RXCLK16_32O± output as 77.76MHz, RXCLKO_FREQSEL = “1” designates RXCLK16_32O± output as

155.52MHz.

The RXCLK16 O and RXCLK 16_32O o utput drivers are desi gned to drive a 5 0Ω transmission line . The

transmissio n line can be DC termin ated wit h a spli t-end t erminat ion scheme (see F igure 3), or DC terminat ed by

50Ω to VCC-2V on each line (see Figure 4). A C-coupling can be ach ieved by a numbe r of methods. Figure 5

illustrates an AC-coupling method for the occasion when the downstream device provides the bias point for

AC-coupling. The divide-by-16 output (RXCLK16O) or the divide-by-16 or -32 output (RXCLK16_32O) can

be used to provide an external looptiming reference clock (after external filteri ng with a 1x REFCLK PLL) fo r

the clock multiplication unit on the VSC8140.

The RXOUT[15:0] output drivers are designed to drive a 50Ω transmission line which can be DC termi-

nated with a split-end termination scheme (see Figure 6), or a traditional termination scheme (see Figure 7).

Figure 6: Split-end DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs

VSC8140

100nF

50Ω50Ω

100nF

VCC-2V

downstream

bias point

generated

internally

VSC8140

R1 = 125Ω

VEE

VCC

R2 = 83Ω

Split-end equivalent termination is ZO to VTERM

R1 = 125Ω R2 = 83Ω, ZO=50Ω, VTERM= VCC-2V

VCCR2 + VEER1

R1+R2 = VTERM

R1||R2 = Zo

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Figure 7: Traditional DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs

The RXO UT[15:0] outp ut drivers ca n also be appropri ately AC-co upled by a number of m ethods, ho w-

ever, DC-coupling is preferred since there is no guarantee of transition density for individual bits in the 16-bit

word. Figure 8 illustrates an AC-coupling meth od for the occasion when the downs tream device pro vides the

bias point for AC-coupling. Figure 9 illustrates an AC-coupling method for the occasion when the bias point

needs to be generated externally. The resistor values in Figure 9 were selected to generate a bias point of 1.98V,

the mid-point for LVPECL VOH and VOL as specified for the VSC8140. Resistor values should be selected to

generate the necessary bias point for the downstream device.

Figure 8: AC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs

VSC8140

VCC-2V

R1 =50Ω

VSC8140

R1 = 50Ω

VCC-2V

100nF

downstream

bias point

generated

internally

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SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

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G52251-0, Rev. 4.0

Figure 9: AC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs

Parity

Systems employing internal parity are supported by the VSC814 0. On the transmit side, a parity check is

performed between the TXPARITYIN input and the 16 TXIN[15:0] bits.

PARMOD E is use d to select even or o dd parity expected for the se 17 b its. (TXIN[15 :0] and TX PARI-

TYIN). PARMODE = “0” selects odd, PARMODE = “ 1” selects even. The PARERR ou tput (parity error out-

put) is asserted active high when the parity of the 17 bits (TXIN[15:0] and TXPARITYIN) does not conform to

the expected parity designated by PARMODE. PARERR becomes available TDV after the rising edge of

TXCLK16I. PA RERR is a NRZ pulse that is updated every 6.4 ns, i.e ., the period of TXCLK16I. The timing

relationship of PARERR to TXCLK16I is shown in Figure 17. The PARERR pin may be left open if pa rity is

unused.

On the receive side, the parity output (RXPARITYOUT) is simply the XOR of all 16 outputs.

Loss of Signal

The VSC8140 has a TTL input LOS to force the part into a Loss of Signal (LOS) state. Most optics have a

TTL output usually called Signal Detect (SD), based on the optical power of the incoming light stream.

Depending on the optics manufacturer, this signal is either active high or low. To accommodate polarity differ-

ences, the inter nal Loss of Sign al is generated when the POL and LOS i nputs a re of o pposit e states. Once acti ve,

all zeroes “0” will be propag ated downstream using the transmit clock until the op tical signal is regained and

LOS and POL are in the same logic state.

VSC8140

R3 =83Ω

VEE

VCC

R4 = 125Ω

100nF

R1 = 125Ω

VEE

VCC

R2 = 83Ω

downstream

bias point

generated

externally

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SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Figure 10: Facility Loopback Data Path

Facility Loopback

The facility loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set

high, the Facility Loopback mode is activated and the high-speed serial receive data (RXIN) is presented at the

high-speed transmit output (TXOUT), as depicted in Figure 10. In addition, the high-speed receive clock input

(RXCLKI) is selected and presented at the high-speed transmit clock output (TXCLKOUT). In Facility Loop-

back mode, the hi gh-speed re ceive data (RXI N) is also convert ed to paral lel data and pr esented at the low-sp eed

receive output pins (RXOUT [15:0]). The receive clock (RXCLKIN) is also divided down and presented at the

low-speed clock output (RXCLK16O).

Equipment Loopback Data Path

The Equipment Loopback function is controlled by the EQULOOP signal, which is active high. When the

Equipment Loopback mode is activated, the high-speed transmit data generated from the parallel to serial con-

version of the low-speed data (TXIN[15:0]) is selected and converted back to parallel data in the receiver sec-

tion and presented at the low-speed paralle l data outputs (RXOUT[15:0]), as shown in Figu re 11. The internally

generated OC-48 clock is used to generate the low-speed receive output clocks (RXCLK16O and

RXCLK16_32O). In Equipment Loopback mode, the transmit data (TXIN[15:0]) is serialized and presented at

the high-speed out put (TXOUT) along with the high-spe ed transmit clock (TXCLKOUT) which is generate d by

the on-chip PLL.

RXCLKIN+

RXCLKIN-

TXOUT+

TXOUT-

2.48832GHz

PLL

Q D

FACLOOP

D Q

RXIN+

RXIN-

TXCLKOUT+

TXCLKOUT- 1

016:1 Parallel to

Serial

1:16 Serial to

Parallel

RXOUT[15:0]

RXCLK16O

RXCLK32O

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Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

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G52251-0, Rev. 4.0

Figure 11: Equipment Loopback Data Path

Figure 12: Split Loopback Datapaths

Split Loopback

Equipmen t and Facil ity Loop back modes can b e enabled simultaneou sly. In this case, high-speed se rial dat a

received (RXIN) and clock (RXCLKIN) are muxed through to the high-speed serial outputs (TXOUT and

TXCLKOUT). The low-speed 16-bit transmit stream (TXIN[15:0]) is muxed into the low-speed 16-bit receive

output stream (RXOUT[15:0]). See Figure 12.

Looptiming

LOOPTIM0 mode b ypasses th e PLL when LOO PTI M0 is asse rted hig h. In th is mode , the PLL is b ypasse d

using the receive high-speed clock (RXCLKIN), and the entire part is synchronously clocked from a single

external source.

RXCLK32O

RXCLKIN+

RXCLKIN-

TXOUT+

TXOUT- Q D

EQULOOP

D Q

RXIN+

RXIN-

TXCLKOUT+

TXCLKOUT-

16:1 Parallel to

1:16 Serial to

Parallel

RXOUT[15:0]

RXCLK16O

TXCLK16O

TXIN[15:0]

TXCLK16I

Serial

2.48832GHz

PLL

RXCLK32O

EQULOOP

16:1 Parallel to

1:16 Serial to

Parallel

RXOUT[15:0]

RXCLK16O

TXCLK16O

TXIN[15:0]

TXCLK16I

2.48832GHz

PLL

RXCLKIN+

RXCLKIN-

TXOUT+

TXOUT- Q D

FACLOOP

D Q

RXIN+

RXIN-

TXCLKOUT+

TXCLKOUT- 1

Serial

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Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

When LOOPTIM1 is asserted high, the RXCLK16_32O or RXCLK16O output can be tied to the LPTIM-

CLK input. In order to meet jitter transfer, the RX CLK16_32O or RXCLOCK16O needs to be filtered by a 1X

PLL circuit with a narrow pass chara cteristic. The part is forced ou t of this mode in Equipmen t Loopback to

prevent the PLL from feeding its own clock back.

Clock Generator

An on-chip PL L generates the 2 .48832GHz transmit c lock from the ex ternally provide d REFCLK input.

The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip

loop filter (with two external 0.1µF peakin g cap acito rs). The loop ban dwidt h of th e PL L is wi thin t he SO NET

specified limit of 2MHz.

The custom er can select to pr ovide either a 77. 76MHz refere nce, or 2x of that refer ence, 155.52MHz.

REF_FREQ SEL is used to select the desired reference frequency. REF_F REQSE L = “0” designates REFCLK

input as 77.76MHz, REF_FREQSEL = “1” designates REFCLK input as 155.52MHz.

The REFCLK should be of high quality since noise on the REFCLK below the loop bandwidth of the PLL

will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a

VCXO may be required to avoid passing REFCLK noise with greater than 2ps RMS of jitter to the output. The

VSC814 0 will ou tput the RE FCLK noi se in ad ditio n to the intr insic jitt er from the VSC814 0 itself du ring suc h

conditions.

Loop Filter

The PLL on the VSC8140 employs a n inte rnal lo op fi lter wit h of f -chip pea kin g capaci tors. The PL L desi gn

is fully differential, therefore the loop filter must also be fully differential. One capacitor should be connec ted

between FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended

capacitors are low-inductance 0.1µF 0603 ceramic SMT X7R devices with a voltage rating equal to or greater

than 10V.

Figure 13: High-Speed Output Termination

= 50Ω

50Ω

100Ω

50Ω

Pre-Driver

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Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

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G52251-0, Rev. 4.0

Transmitter High-Speed Data and Clock Outputs

The high-s peed data and cloc k output drive rs (TXOUT and TXCLKOUT ) consist of a differential pair

designed to drive a 50Ω transmission line. The transmission line should be terminated with a 100Ω resist or at

the load between true and complement outputs (see Figure 13). No connection to a termination voltage is

required. The output driver is back terminated to 50Ω on-chip, providing a snubbing of any reflections. If used

single-end ed, the high-sp eed outpu t driver must sti ll be termi nated dif feren tial ly at the l oad with a 100Ω resistor

between true and complement outputs.

In order to save power, the high-speed transmit clock output (TXCLKOUT ) can be powered down by con-

necting the power pins VEEP_CLK and VEE_PWRDN to the VCC supply instead of to VEE.

Figure 14: AC Termination of Low-Speed LVPECL REFCLK and LPTIMCLK Inputs

Reference Clock Inputs

The incomin g low-speed reference clock inp uts are receive d by differential LVPECL inputs REFCLK± .

Off-chip termination of these inputs is required (see Figure 14).

In most situations these inputs will have high transition density and little DC offset. However, in cases

where this does not hold, direct DC connection is possible. All serial clock inputs have the same circuit topol-

ogy, as shown in Figure 14. If the input signal is driven differentially and DC-coupled to the part, the mid-point

of the input sign al swing should be centered about the input com mon-mode voltage VCM an d not exce ed the

maximum allo wable amplitu de. For single -ended , DC-coupling operat ions, it is re commended tha t the user pro-

vides an external reference voltage. The external reference should have a nominal value equivalent to the com-

mon-mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate.

VCC = 3.3V

VEE = 0V

CIN

Chip Boundary

CIN TYP = 100nF

for AC operation

R1||R2 = Zo , R1 = 83Ω R2 =125Ω

VCCR2 + VEER1

R1+R2 = VBIAS

VCC

VEE

CIN

VCC

VEE

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Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Figure 15: Termination of Low-Speed LVPECL TXIN[15:0] Inputs

Low-Speed Inputs

The incoming low-speed inputs are received by single-ended LVPECL inputs TXIN[15:0]. A reference

voltage is necessary to provide for optimal switching of the inputs. The user can either provide an input voltage

reference f rom the upstream de vice (VREFIN), or can use the referenc e voltage provided from the VSC8140

(VREFOUT). Side-by-side placement of the VREFIN and VREFOUT pins facilitates easy implementation.

For DC or AC operation, the external reference should have a nominal value equivalent to the common-

mode switch point of an LVPECL DC-coupled signal, and adhere to the DC characteristics as specified by the

Table 3 DC characteristics (VCM).

VCC = 3.3V

VEE = 0V

Chip Boundary

VREFIN

VREFOUT CIN TYP = 100nF

for AC operation

CIN

VCC

VEE

R1||R2 = Zo , R1 = 83Ω R2 =125Ω

VCCR2 + VEER1

R1+R2 = VBIAS

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Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

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G52251-0, Rev. 4.0

Figure 16: High-Speed Clock and High-Speed Data Inputs

High-Speed Clock and High-Speed Data Inputs

The incoming high-speed data and high-speed clock are received by high-speed inputs RXIN and

RXCLKIN. The inputs are internally biased to accommodate AC-coupling.

The data input receiver is internally terminated by a center-tapped resistor network. For differential input

DC-coupling, the network is terminated to the appropriate termination voltage VTERM pr ovidi ng a 50Ω to VTERM

termination for both true and complement inputs. For differential input AC-coupling, the network is terminated

to VTERM via a blocking capacitor.

In most situations, these inputs will have high transition density and little DC offset. However, in cases

where this does not hol d, direct DC connec tion is possible . All serial da ta and clo ck input s have the same circuit

topolo gy, as shown in Figure 16. The refer ence vol tage is creat ed by a resist or divi der as shown. If the input sig-

nal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-

tered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-

couplin g operations, it is reco mmended that th e user provid es an external refe rence voltage which has better

temperature and pow er supply noise rejection than the on-chip resistor divider. The external reference should

have a nominal value equivalent to the common-mode switch point of the DC-coupled signal, and can be con-

nected to eithe r side of th e differential gate.

VCC = 3.3V

VEE = 0V

CIN

Chip Boundary

CIN TYP = 100nF

CAC TYP = 100nF

VTERM

CAC

50Ω

CIN

1.65V

3kΩ

1.65V

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Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Supplies

The VSC8140 is specified as a PECL device with a s ingle positive 3.3V supply. Should the user desire to

use the device in an ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be -

3.3V. If used with VEE tied to -3.3V, the TTL c ontrol signals are still referenc ed to VEE.

Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is

recommended that the VCC power supply be decoupled using a 0.1µF and 0.01µF capa citor placed in parallel

on each VCC power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should

also be placed in parallel with the 0.1µF and 0.01µF capacitors mentioned above. Recommended capacitors are

low-inductance ceramic SMT X7R devices. For the 0.1µF capacitor, a 0603 package should be used. The

0.01µF and 0.001µF capacitors can be either 0603 or 0403 packages.

Extra care needs to be taken when decoupling the analog power supply pins (labeled VCCANA). In order to

maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8140, the analog

power sup ply pins should be filtered from the main p ower s upply wi th a 10µH C-L-C pi filter. If preferred, a

ferrite bead may be used to provide the isolation. The 0.1µF and 0.01µF decoupling capacitors are still required

and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead).

For low frequency decoupling, 47µF tantalum low-inductance SMT caps are sprinkled over the board’s

main +3.3V power supply and placed close to the C-L-C pi filter.

If the device is being used in an ECL environm ent with a -3.3V supply, then all references to decoupling

VCC must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V.

Figure 17: PLL Power Supply Decoupling Scheme

Note: V

can be tied to V

CCANA

EEANA

CCANA

10µH

0.1µF 0.1µF0.01µF

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SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 14 

VITESSE

SEMICONDUCTOR CORPORATION

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G52251-0, Rev. 4.0

AC Characteristics

Figure 18: Transmitter Parallel Data Timing Waveforms

Figure 19: Transmitter Serial Data and Clock Phase Timing

Figure 20: Transmitter Parity Timing

tTXDSU tTXDH

Valid Data 1

TXCLK16I+

Parallel Data Clock Input

TXIN[0:15]+, TXPRTYIN

Parallel Data Inputs

TXCLK16O+

Parallel Data Clock Output

= don’t care

Valid Data 2

D15

MSB LSB

Time

D14 D13

TXOUT+

Differential Serial Data Output

TXCLKO+

Differential Clock Output

NOTE: Bit 15 (MSB) is transmitted first, Bit 0 (LSB) is transmitted last.

tDH

tPD

D1 D0

tDV tD

TXCLK16I+

Parallel Data Clock Input

PARERR+

Data V alid Output

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Figure 21: Differential and Single-Ended Input / Output Voltage Measurement

Table 1: Transmitter AC Characteristics

Parameters Description Min Typ Max Units Conditions

TDTXCLK16I/TXCLK16O period —6.4—ns—

TXDSU Data setup time to the rising edge of

TXCLK16I+ 0.75 — — ns —

TTXDH Data hold time after the rising edge

of TXCLK16I+ 1.0 — — ns —

TTXDOR,

TTXDOF TXOUT± rise and fall time — — 120 ps 20% to 80% into 100Ω load.

See Figure 13 .

TXCLKDTransmit clock duty cycle 40 — 60 % —

tTXCLK16R,

tTXCLK16F TXCLK16O± rise and fall times — — 250 ps See Figure 24

TXCLK16ODTXCLK16O± duty cycle 46 — 53 % —

TXCLK16IDTXCLK16I± duty cycle 35 — 65 % Assuming 10% distortion of

TXCLK16O.

RCKDReference clock duty cycle 40 — 60 % —

TDV Parallel data to DINVALID — 3 tD + 0.3 — ns —

tDH TXCLKO period — 401.9 — ps —

tPD Cent er of output data eye from

falling edge of TXCLKO -75 — +75 ps See Figure 19

Clock Multi plier Performance

TDJ Output data jitter — — 4 ps

RMS, tested to SONET

specification (12kHz to

20MHz) with 2p s RMS ji tte r

on REFCLK.

TCJ Output clock jitter — — 4 ps

RMS, tested to SONET

specification (12kHz to

20MHz) with 2p s RMS ji tte r

on REFCLK.

Jittertol Jitter tolerance — — — — Exceeds SONET/SDH mask

Tuning Range -100 +100 ppm

Single

Ended

Swing

Differential

Swing

Differential swing is specified as equal in magnitude t o single-ended swing.

* Differential swing

(α

) is specified as | b - a | ( or | a - b | ), as is the single-ended swing.

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Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 16 

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G52251-0, Rev. 4.0

Figure 22: Receiver AC T iming Waveforms

Figure 23: Receiver Setup and Hold Time Requirements

Table 2: Re ceiver AC Characterist ics

Parameters Description Min Typ Max Units Conditions

tRXPDD Data valid from fall ing edg e of

RXCLK16O+ 0 800 ps —

tRXPD32 RXCLK32O transition from

falling edge of RXCLK16O+ 01.0ns—

RXDR, tRXDF RXOUT[15:0]+/- rise and fall

times — 300 ps 20% to 80% into DC termination.

See Figure 24.

tRXCLKR,

tRXCLKF

RXCLK16O+/- rise and fall

times — 250 ps 20% to 80% into 100Ω load.

See Figure 24.

RXCLK16ODRXCLK16O+/- duty cycle

distortion 45 55 % of

cloc k cy cle High-speed clock input at

2.48832GHz.

tRXDSU RXIN+ setup time with respect

to falling edge of RXCLKIN+ 100 — ps —

tRXDH

RXIN+ hold time with

respect to falling edge of

RXCLKIN+ 75 — ps —

RXCLKINDRXCLKIN+/- duty cycle

distortion 40 60 % of

clock cycle —

RXDSU

RXPDD

RXPD32

Valid Data 1

RXCLK16O+

Parallel Data Clock Output

RXOUT[0:15]+

Parallel Data Outputs

RXCLK32O+

Parallel Data Clock Output

= don’t care

Valid Data 2

D15

MSB LSB

Time

D14 D13

RXIN+

Differential Serial Data Input

RXCLKIN+

Differential Clock Input

NOTE: Bit 15 (MSB) is received first, Bit 0 (LSB) is received last.

tRXDSU tRXDH

D1 D0

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

DC Characteristics

Table 3: DC Characteristics

(Over recommended operating conditions)

Parameters Description Min Typ Max Units Conditions

VOHHSO Outpu t HIGH voltage (TXOUT,

TXCLKOUT) VCC-0.40 —V

CC V50Ω termination to VCC

VOLHSO Output LOW voltage (TXOUT,

TXCLKOUT) VCC-1.20 — VCC-0.50 V 50Ω termination to VCC

∆VODHSO

Output differential voltage

(TXCLKOUT) 450 600 1000

mV 100Ω termination betwe en ±

output at load. See Figure 13.

Output differential voltage

(TXOUT) 500 600 1000

VCMHSO Output common-mode voltage VCC-1.20 — VCC-0.300 V 100Ω termination be twee n ±

output at load. See Figure 13.

RHSO Back termination impedance 40 — 60 ΩGuaranteed, but not teste d

∆VIHS Serial input differential voltage

(RXIN, RXCLKIN) 200 — — mV AC-coupled, internally

biased to ( VCC+VEE)/2.

VOHL Output HIGH voltage (LVPECL) VCC-1.020 — VCC-0. 700 V See Fi gure 24

VOL Output LOW voltage (LVPECL) VCC-2.000 — VCC-1. 620 V See Fi gure 24

∆VO

Low-speed output voltage single-

ende d, peak-t o- peak swing

(LVPECL) 600 — 13 00 mV See Figure 24

VIH Input HIGH voltage (LVPECL) VCC-1.100 — VCC-0.700 V —

VIL Input LOW voltage(LVPECL) VCC-2.0 — VCC-1.540 V —

IIH Input HIGH current (LVPECL) — — 200 µA VIN=VIH (max)

IIL Input LOW current (LVPECL) -50 — — µA VIN=VIL(min)

RiInput Resistance (LVPECL) 10k — — Ω—

∆VIInput dif fe r ential volta ge

(LVPECL) 200 — — mV —

VCM Input common-mode voltage

(LVPECL) VCC-1.5 — VCC-0.5 V —

VOH Output HIGH voltage (TTL) 2.4 — — V IOH = -1.0 mA

VOL Output LOW voltage (TTL) — — 0.5 V IOL = +1.0mA

VIH Input HIGH voltage (TTL) 2.0 — 5.5 V —

VIL Input LOW voltage (TTL) 0.0 — 0.8 V —

IIH Input HIGH Current (TTL) — — 500 µA VIN = 2.4 V

IIL Input LOW current (TTL) — — -500 µA VIN = 0.5V

VCC Supply vo lta ge 3.14 — 3.47 V 3.3V± 5%

PDPower dissipat ion — 2.25 2.75 W Output s open

ICC Supp ly cu r re nt — — 800 mA O u tp uts ope n

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SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 18 

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G52251-0, Rev. 4.0

Figure 24: Parametric Measurement Information

Absolute Maximum Ratings

(1)

Power Supply Voltage (VCC)...........................................................................................................-0.5V to +3.8V

DC Input Voltage (differential inputs).....................................................................................-0.5V to VCC +0.5V

DC Input Voltage (TTL inputs).......................................................................................................-0.5V to +5.5V

DC Output Voltage (TTL outputs) .........................................................................................-0.5V to VCC + 0.5V

Output Current (TTL outputs).......................................................................................................... ........ +/-50mA

Output Current (differential outputs) .........................................................................................................+ /-50mA

Case Temperature Under Bias......................................................................................................-55oC to +125oC

Recommended Operating Conditions

Power Supply Voltage (VCC)..................................................................................................................+3.3V+5%

Operating Temperature Range ...........................................................0oC Ambient to +110oC Case Temperature

NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-

ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended

periods may affect devi ce reliability.

ESD Ratings

Proper ESD procedures should be used when handling this product. The VSC8140 is rated to the following

ESD voltages based on the human body model:

1. All pins are rated at or above 1500V.

PECL Rise and Fall Time

Serial Output Load

TrTf

80%

20% Z0 = 5 0Ω50Ω

VCC-2V

Parametric Test Load Circuit

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Package Pin Descriptions

Table 4: Packag e Pin Identification - 128 PQFP

Pin # Name I/O Level Description

1 OVERFLOW O TTL FIFO overflow indication

2VEET— GND typ. TTL VEE powe r supply

3 VCCT — +3.3V typ. TTL VCC power supply

4 VEE — GND typ. Negative po wer supply

5 HSDREF I 0V->3.3V High-speed data input termination voltage reference

6 VEE — GND typ. Negative po wer supply

7 RXIN+ I HS High-speed data input, true

8 RXIN- I HS High-speed data input, complement

9 VCC — 3.3V typ. Positive power supply

10 VEE — GND typ. Negative power supply

11 VEE — GND typ. Negative power supply

12 VCC — 3.3V typ. Positive power suppl y

13 RXCLKIN- I HS High-speed clock input, complement

14 HSCLKREF I 0V->3.3V High-speed clock input termination voltage reference

15 RXCLKIN+ I HS High-speed clock In put, true

16 VCC — 3.3V typ. Positive power suppl y

17 NC — — No connect, leav e unconne cted(1)

18 VCC — 3.3V typ. Positive power suppl y

19 VCC — 3.3V typ. Positive power suppl y

20 TXOUT+ O HS High-speed data output, true

21 TXOUT- O HS High-speed data output, compl e ment

22 VCC — 3.3V typ. Positive power suppl y

23 VEE — GND typ. Negative power supply

24 VEE — GND typ. Negative power supply

25 VEE — GND typ. Negative power supply

26 VCC — 3.3V typ. Positive power suppl y

27 VCC — 3.3V typ. Positive power suppl y

28 T XCLKOUT+ O HS High-speed clock output, true

29 T X CLKOUT- O HS H igh-speed clock output, compl ement

30 VCC — 3.3V typ. Positive power suppl y

31 VEEP_CLK — GND typ. HS clock VEE power supply (tie to VCC for power down)

32 VEEP_CLK — GND typ. HS clock VEE power supply (tie to VCC for power down)

33 VEE_PWRDN I GND typ. HS clock VEE power supply (tie to VCC for power down )

34 VCC — 3.3V typ. Positive power suppl y

35 VCC — 3.3V typ. Positive power suppl y

36 VCC — 3.3V typ. Positive power suppl y

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SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 20 

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G52251-0, Rev. 4.0

37 VEE — GND typ. Negative power supply

38 FACLOOP I TTL Facility loopback, active high

39 LOOPTIM0 I TTL Enable internal looptiming operation, active high

40 PARMODE I TTL Parity mode select

41 FI FORESET I TTL Reset to al ign FIFO write and read pointers

42 LOOPTIM1 I TTL Enable external loop timing operation, active high

43 REF_ FREQSEL I TTL Reference clock input select

44 LPTIMCLK+ I LVPECL External loop timing clock, true

45 LPTIMCLK- I LVPECL External loop timing clock, complement

46 VCC_ANA — +3.3V typ. Positive power supplys for analog parts of CMU

47 VEE_ANA — GND typ. Negative po wer supplys for analog parts of CMU

48 REFCL K + I LVPECL Reference clock input, true

49 REFCLK - I LVPECL Reference clock input, complement

50 VEE — GND typ. Negative power supply

51 FILTAO — — Loop filter pin - connect via capacitor to FILTAI (pin 53)

52 FILTAON — — Loop filter pin - connect via capacitor to FILTAIN (pin 54)

53 FILTAI — — Loop filter pin - connect via capacitor to FILTAO (pin 51)

54 FILTAIN — — Loop filter pin - connect via capacitor to FILTAON (pin 52)

55 VCC — 3.3V typ. Positive power suppl y

56 TXCLK16O+ O LVPECL Low-speed clock output, true. A divi de-by- 16 version of the PL L

clock.

57 TXCLK16O- O LVPECL Low-speed clock output, complement. A divide-by-16 version of the

PLL cl oc k.

58 VEE — GND typ. Negative power supply

59 TXCLK16I- I LVPECL Low-speed clock input for latching low-speed data, complement

60 TXCLK16I+ I LVPECL Low-speed clock input for latching low-speed data, true

61 VCC — 3.3V typ. Positive power suppl y

62 TXPARITYIN I LVPECL Transmitter parity bit input

63 TXIN15 I LVPECL Low-speed single -ended data (MSB)(2)

64 TXIN14 I LVPECL Low-speed single -ended data

65 VEE — GND typ. Negative power supply

66 VCC — 3.3V typ. Positive power suppl y

67 TXIN13 I LVPECL Low-speed single -ended data

68 TXIN12 I LVPECL Low-speed single -ended data

69 TXIN11 I LVPECL Low-speed single-ended data

70 TXIN10 I LVPECL Low-speed single -ended data

71 TXIN9 I LVPECL Low-speed single-ended data

Table 4: Packag e Pin Identification - 128 PQFP

Pin # Name I/O Level Description

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

72 VEE — GND typ. Negative power supply

73 TXIN8 I LVPECL Low-speed single-ended data

74 TXIN7 I LVPECL Low-speed single-ended data

75 TXIN6 I LVPECL Low-speed single-ended data

76 TXIN5 I LVPECL Low-speed single-ended data

77 TXIN4 I LVPECL Low-speed single-ended data

78 VCC — 3.3V typ. Positive power suppl y

79 TXIN3 I LVPECL Low-speed single-ended data

80 TXIN2 I LVPECL Low-speed single-ended data

81 VEE — GND typ. Negative power supply

82 TXIN1 I LVPECL Low-speed single-ended data

83 TXIN0 I LVPECL Low-speed single-ended data (LSB)(2)

84 VCC — 3.3V typ. Positive power suppl y

85 VREFIN I Voltage Voltage reference for single-ended TXIN VCM or VREFOUT

86 VREFOUT O Voltage Voltage reference for single-ended RXOUT (VOH+VOL)/2.

87 VCC — 3.3V typ. Positive power suppl y

88 RXOUT0 O LVPECL Low-speed single-en ded data (LSB)(2)

89 RXOUT1 O LVPECL Low-speed single-en ded data

90 VEE — GND typ. Negative power supply

91 RXOUT2 O LVPECL Low-speed single-en ded data

92 RXOUT3 O LVPECL Low-speed single-en ded data

93 VCC — 3.3V typ. Positive power suppl y

94 RXOUT4 O LVPECL Low-speed single-en ded data

95 RXOUT5 O LVPECL Low-speed single-en ded data

96 VCC — 3.3V typ. Positive power suppl y

97 RXOUT6 O LVPECL Low-speed single-en ded data

98 RXOUT7 O LVPECL Low-speed single-en ded data

99 VEE — GND typ. Negative power supply

100 RXOUT8 O LVPECL Low-speed single-ended data

101 RXOUT9 O LVPECL Low-speed single-ended data

102 VCC — 3.3V typ. Positive power sup ply

103 VCC — 3.3V typ. Positive power sup ply

104 R XOUT10 O LVPECL Low-speed single-ended data

105 RXOUT11 O LVPECL Low-speed single-ended data

106 R XOUT12 O LVPECL Low-speed single-ended data

107 VCC — 3.3V typ. Positive power sup ply

108 R XOUT13 O LVPECL Low-speed single-ended data

Table 4: Packag e Pin Identification - 128 PQFP

Pin # Name I/O Level Description

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Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 22 

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G52251-0, Rev. 4.0

NOTES: (1) No connect (NC) pin must be left unconnected. Connecting this pin to either the positive or negative power supply

rails may cause improper operation or failure of the device; or in extreme cases, cause permanent damage to the device.

(2) There has been a change in t he naming of the pins of the Low-Speed Parallel Receive and Transmit pin s of the

VSC8140. RXOUT0; pin 88 (MSB) has been changed to RXOUT15; pin 111 (MSB) an d TXIN15; pin 63 (LSB) has been

changed to TXIN0; pin 83 (LSB).

109 R XOUT14 O LVPECL Low-speed single-ended data

110 VEE — GND typ. Negative power supply

111 RXOUT15 O LVPECL Low-speed single-ended data (MSB)(2)

112 RXPARITYOUT O LVPECL Receiver parity bit output

113 VCC — 3.3V typ. Po sitiv e power supply

114 RXCLK16O- O LV PECL Parall el clock output (155.52MHz), comp lement

115 RXCLK16O+ O LVPECL Parallel clock output (155.52MHz), true

116 VEE — GND typ. Nega tive power supply

117 VCC — 3.3V typ. Po sitiv e power supply

118 RXCLK16_32O- O LVPECL Divide-by-16 or -32 clock output, complement

119 RXCL K16_32O+ O LVPECL Divide-by-16 or -32 clock output, tru e

120 CLK128O- O LVPECL Divid e - by -128 cloc k output, com pl em e nt

121 CLK128O+ O LVPECL Divide- by -128 cloc k outp ut, true

122 VCC — 3.3V typ. Positive power sup ply

123 RXCLKO_FREQSEL I TTL RXCLKO16_32 frequency select

124 LOS I TTL Loss of Signal control

125 POL I TTL Polarity Signal Control

126 EQULOOP I TTL Equipment loopback, active high

127 VCC — 3.3V typ. Positive power sup ply

128 PARERR O TTL Parity error output

Table 4: Packag e Pin Identification - 128 PQFP

Pin # Name I/O Level Description

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Package Information

STANDOFF

LEAD COPLANARITY

MAX.

0.17

.25

θ1

10° TYP.

TOP VIEW

EXPOSED

HEATSINK

EXPOSED

INTRUSION

0.127 MAX.

RAD. 2.92 ± .50

(2)

2.54 ± .50

PIN 128

PIN 1

E1E

Notes: 1) Drawing is not to scale

2) All dimensions in mm

3) Package represented is

also used for the 64,

80, & 100 PQFP packages.

Pin count drawn does

not reflect the 128 Package.

PIN 38 PIN 64

PIN 102

NOTES:

128 PQFP Package Drawings

Package #: 101-322-5

Issue #: 2

Key mm Tolerance

A2.35 MAX

A1 0.25 MAX

A2 2.00 +.10

D17.20 ±.20

D1 14.00 ±.10

E 23.20 ±.20

E1 20.00 ±.10

L.88+.15/-.10

e .50 BASIC

b .22 ±.05

q 0°-7°

R.30 TYP

R1 .20 TYP

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Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 24 

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G52251-0, Rev. 4.0

Package Pin Descriptions

Table 5: Package Pin Identification - 208 BGA

Pin # Name I/O Level Description

B17 OVERFLOW O TTL FIFO over flow indication

B16 VEET — GND typ. TTL VEE power supply

B15 VCCT — +3.3V typ. TTL VCC power supp ly

C14 VEE — GND typ. Negative power supply

D13 HSDREF I 0V->3.3V High-speed data input termination voltage reference

A16 VEE — GND typ. Negative power supply

B14 RXIN+ I HS High -spe ed da ta inpu t, true

B13 RXIN- I HS High-spe ed da ta inpu t, com plem e nt

A14 VCC — 3.3V typ. Positive power supply

A13 VEE — GND typ. Negative power supply

D11 VEE — GND typ. Negative pow er supply

C1 1 VCC — 3.3V typ. Positive power supply

B11 RXCLKIN- I HS High-speed clock input, complement

D10 HSCLKREF I 0V->3.3V High-speed clock input termination voltage reference

B10 RXCLKIN+ I HS High-speed clock input, true

A10 VCC — 3.3V typ. Positive power supply

B9 VCC — 3.3V typ. Positive power supply

D9 VCC — 3.3V typ. Positive power supply

A9 TXOUT+ O HS High-speed data output, true

A8 TXOUT- O HS High-speed data output, complement

C8 VCC — 3.3V typ. Positive power supply

D8 VEE — GND typ. Negative power supply

A7 VEE — GND typ. Negative power supply

A6 VEE — GND typ. Negative power supply

D7 VCC — 3.3V typ. Positive power supply

A5 VCC — 3.3V typ. Positive power supply

A4 TXCLKOUT+ O HS High-speed clock output, true

A3 TXCLKOUT- O HS High-speed clock output, complement

B4 VCC — 3.3V typ. Positive power supply

D5 VEEP_CLK — GND typ. HS clock VEE power supply (tie to VCC for power down)

A2 VEEP_CLK — GND typ. HS clock VEE power supply (tie to VCC for power down)

A1 VEE_PWRDN I GND typ. HS clock VEE power supply (tie to VCC for power down)

C4 VCC — 3.3V typ. Positive power supply

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Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

B3 VCC — 3.3V typ. Positive power supply

D4 VCC — 3.3V typ. Positive power supply

C3 VEE — GND typ . Negativ e power supply

C1 FACLOOP I TTL Facility loopback, active high

F4 LOOPTIM0 I TTL Enable internal looptiming operation, active high

F3 PARMODE I TTL Parity mode select

D1 FIFORESET I TTL Reset to align FIFO write and read pointers

E1 LOOPTIM1 I TTL Enable external loop timing operation, active high

G4 REF_FREQSEL I TTL Reference clock input select

G3 VEE — GND typ. Negative power supply

F2 LPTIMCLK+ I LVPECL External loop timing clock, true

G2 LPTIMCLK- I LVPECL External loop timing clock, complement

F1 VCC_ANA — +3.3V typ. Positive power supplies for analog parts of CMU

H3 VEE_ANA — GND typ. Negative power supplies for analog parts of CMU

H2 REFCLK+ I LVPECL Reference clock input, true

G1 REFCLK- I LVPECL Reference clock input,complement

H1 VEE — GND typ. Negative power supply

J2 VCC — 3.3V typ. Positive power supply

J4 FILTAO — — Loop filter pin - connect via capacitor to FILTAI (pin 53)

J3 FILTAON — — Loop filter pin - connect via capacitor to FILTAIN (pin 54)

K1 FILTAI — — Loop filter pin - connect via capacitor to FILTAO (pin 51)

K2 FILTAIN — — Loop filter pin - connect via capacitor to FILTAON (pin 52)

K3 VCC — 3.3V typ. Positive power supply

K4 TXCLK16O+ O LVPECL Low-speed clock ou tput, tr ue. A divid e-by-16 v e rsion of the PLL

clock.

L1 TXCLK16O- O LVPECL Low-speed clock output, compleme nt. A divide-by-1 6 version of the

PLL clock.

M1 VEE — GND typ. Negative pow er supply

L2 TXCLK16I- I LVPECL Low-speed clock input for latching low-speed data, complement

L3 TXCLK16I+ I LVPECL Low-speed clock input for latching low-speed data, true

L4 VCC — 3.3V typ. Positive power supply

M2 TXPARITYIN I LVPECL Transmitter parity bit input

M3 TXIN15 I LVPECL Low-speed single-ended data (MSB)(1)

M4 TXIN14 I LVPEC L Low-speed singl e-ended data

P1 VEE — GND typ. Negative power s upply

Table 5: Package Pin Identification - 208 BGA

Pin # Name I/O Level Description

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 26 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 9/6/00

G52251-0, Rev. 4.0

T3 VCC — 3.3V typ. Positive power supply

P5 TXIN13 I LVPECL Low-speed single-ended data

R5 TXIN12 I LVPECL Low-speed single-ended data

T4 TXIN11 I LVPECL Low-speed single-ended data

P6 TXIN10 I LVPECL Low-speed single-ended data

T5 TXIN9 I LVPECL Low-speed single-ended data

R6 VEE — G ND typ. Negative power supply

U5 TXIN8 I LVPECL Low-speed single-ended data

R7 TXIN7 I LVPECL Low-speed single-ended data

T6 TXIN6 I LVPECL Low-speed single-ended data

U6 TXIN5 I LVPECL Low-speed single-ended data

P8 TXIN4 I LVPECL Low-speed single-ended data

R8 VCC — 3.3V typ. Positive power supply

T8 TXIN3 I LVPECL Low-speed single-ended data

U7 TXIN2 I LVPECL Low-speed single-ended data

U8 VEE — GND typ. Negative p ower supply

T9 TXIN1 I LVPECL Low-speed single-ended data

P9 TXIN0 I LVPECL Low-speed single-ended data (LSB)(1)

R9 VCC — 3.3V typ. Positive power supply

U9 VREFIN I Voltage Voltage reference for single-ended TXIN VCM or VREFOUT

U10 VREFOUT O Voltag e Voltage reference for single-ended RXOUT (VOH+VOL)/2

T10 VCC — 3.3V typ. Positive power supply

R10 RXOUT0 O LVPECL Low-speed single-ended data (LSB)(1)

P10 RXOUT1 O LVPECL Low-speed single-ended data

U11 VEE — GND typ. Neg ative power supply

U12 RXOUT2 O LVPECL Low-speed single-ended data

T11 RXOUT3 O LVPECL Low-speed single-ended data

R11 VCC — 3.3V typ. Positive power supply

P11 RXOUT4 O LVPECL Low-speed single-ended data

U13 RXOUT5 O LVPECL Low-speed single-ended data

T12 VCC — 3.3V typ. Positive power supply

T13 RXOUT6 O LVPECL Low-speed single-ended data

R12 RXOUT7 O LVPECL Low-speed single-ended data

P12 VEE — GND typ. Negative power supply

Table 5: Packag e Pin Identification - 208 BGA

Pin # Name I/O Level Description



VITESSE

SEMICONDUCTOR CORPORATION

Page 27

9/6/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

U14 RXOUT8 O LVPECL Low-spe ed single-ended data

U15 RXOUT9 O LVPECL Low-spe ed single-ended data

R13 VCC — 3.3V typ. Positive power supply

N16 VCC — 3.3V typ. Positive power supply

P17 RXOUT10 O LVPECL Low-speed single-ended data

L14 RXOUT11 O LVPECL Low-speed single-ended data

L15 RXOUT12 O LVPECL Low-speed single-ended data

M16 VCC — 3.3V typ. Positive power supply

L16 RXOUT13 O LVPECL Low-speed single-ended data

M17 RXOUT14 O LVPECL L ow-speed single-en ded data

K14 VEE — GND typ. Negative power supply

K15 RXOUT15 O LVPECL Low-speed single-ended data (MSB)(1)

K16 RXPARITYOUT O LVPECL Receiver Parity bit output

L17 VCC — 3.3V typ. Positive power supply

J17 RXCLK16O- O LVPECL Parallel clock output (155.52MHz), complement

H17 RXCLK16O+ O LVPECL Parallel clock output (155.52MHz), true

H16 VEE — GND typ. Negative power supply

H15 VCC — 3.3V typ. Positive power supply

H14 RXCLK16_32O- O LVPECL Divide-by-16 or -32 clock output, complement

G17 RXCLK16_32O+ O LVPECL Divide-by-16 or -32 clock output, true

F17 CLK128O- O LVPECL Divide-by-128 clock output, complement

G16 CLK128O+ O LVPECL Divide- by-128 clock o utput, true

G15 VCC — 3.3V typ. Positive power supply

G14 RXCLKO_FREQSEL I TTL RXCLKO16_32 frequency select

D17 LOS I TTL Loss of Signal control

C17 POL I TTL Polarity Signal Control

E15 EQULOOP I TTL Equipment loopback, active high

D16 VCC — 3.3V typ. Positive power supply

E14 PARERR O TTL Parity error output

A17 NC — — No connect , l eave unconnected(2)

A15 NC — — No connect , l eave unconnected(2)

A12 NC — — No connect , l eave unconnected(2)

A11 NC — — No connect , l eave uncon nected(2)

B12 NC — — No connect, leave unconnected(2)

B8 NC — — No connect , leave unconnected(2)

Table 5: Package Pin Identification - 208 BGA

Pin # Name I/O Level Description

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 28 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 9/6/00

G52251-0, Rev. 4.0

B7 NC — — N o connect, leave unconnected(2)

B6 NC — — No connect , leave unconnected(2)

B5 NC — — No connect , leave unconnected(2)

B2 NC — — No connect , leave unconnected(2)

B1 NC — — No connect , leave unconnected(2)

C16 NC — — No connect, leave unconnected(2)

C15 NC — — No connect, leave unconnected(2)

C13 NC — — No connect, leave unconnected(2)

C12 NC — — No connect, leave unconnected(2)

C10 NC — — No connect, leave unconnected(2)

C9 NC — — No connect , leave unconnected(2)

C7 NC — — No connect , leave unconnected(2)

C6 NC — — No connect , leave unconnected(2)

C5 NC — — No connect , leave unconnected(2)

C2 NC — — No connect , leave unconnected(2)

D15 NC — — No connect , l eave unconnected(2)

D14 NC — — No connect , l eave unconnected(2)

D12 NC — — No connect , l eave unconnected(2)

D6 NC — — No connect, leave un connected(2)

D3 NC — — No connect, leave un connected(2)

D2 NC — — No connect, leave un connected(2)

E17 NC — — No conne c t, leave unconnected(2)

E16 NC — — No conne c t, leave unconnected(2)

E4 NC — — No connect, leave unconnect e d (2)

E3 NC — — No connect, leave unconnect e d (2)

E2 NC — — No connect, leave unconnect e d (2)

F16 NC — — No connect, leave unconnected(2)

F15 NC — — No connect, leave unconnected(2)

F14 NC — — No connect, leave unconnected(2)

H4 NC — — No connect, leave un connected(2)

J16 NC — — No connect, leave unconnected(2)

J15 NC — — No connect, leave unconnected(2)

J14 NC — — No connect, leave unconnected(2)

J1 NC — — No connect, leave unconne cted(2)

K17 NC — — No connect , l eave unconnected(2)

Table 5: Package Pin Identification - 208 BGA

Pin # Name I/O Level Description



VITESSE

SEMICONDUCTOR CORPORATION

Page 29

9/6/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

M15 NC — — No connect , leave uncon nected(2)

M14 NC — — No conne c t, leave un connecte d(2)

N17 NC — — No connect , l eave unconnected(2)

N15 NC — — No connect , l eave unconnected(2)

N14 NC — — No connect , l eave unconnected(2)

N4 NC — — No connect, leave un connected(2)

N3 NC — — No connect, leave un connected(2)

N2 NC — — No connect, leave un connected(2)

N1 NC — — No connect, leave un connected(2)

P16 NC — — No connect, leave unconnected(2)

P15 NC — — No connect, leave unconnected(2)

P14 NC — — No connect, leave unconnected(2)

P13 NC — — No connect, leave unconnected(2)

P7 NC — — No connect, leave unconnected(2)

P4 NC — — No connect, leave unconnected(2)

P3 NC — — No connect, leave unconnected(2)

P2 NC — — No connect, leave unconnected(2)

R17 NC — — No connect, leave unconnected(2)

R16 NC — — No connect, leave unconnected(2)

R15 NC — — No connect, leave unconnected(2)

R14 NC — — No connect, leave unconnected(2)

R4 NC — — No connect , leave unconnected(2)

R3 NC — — No connect , leave unconnected(2)

R2 NC — — No connect , leave unconnected(2)

R1 NC — — No connect , leave unconnected(2)

T17 NC — — No conne c t, leave unconnected(2)

T16 NC — — No conne c t, leave unconnected(2)

T15 NC — — No conne c t, leave unconnected(2)

T14 NC — — No conne c t, leave unconnected(2)

T7 NC — — No connect, leave unconnect e d (2)

T2 NC — — No connect, leave unconnect e d (2)

T1 NC — — No connect, leave unconnect e d (2)

U17 NC — — No connect , l eave unconnected(2)

U16 NC — — No connect , l eave unconnected(2)

U4 NC — — No connect, leave un connected(2)

Table 5: Package Pin Identification - 208 BGA

Pin # Name I/O Level Description

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 30 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 9/6/00

G52251-0, Rev. 4.0

NOTES: (1) There has been a change in the naming of the pins of the Low-Speed Parallel Receive and Transmit pins of the

VSC8140. RXOUT0; pin R10 (MSB) has been changed to RXOUT15; pin K15 (MSB) and TXIN15; pin M3 (LSB) has

been changed to TXIN0; pin P9 (LSB).

(2) No connect (NC) pins must be left unconnected. Connecting any of these pins to either the positive or negative power

supply rails may caus e improper operation or f ailure of the device; or in ext reme cases, cause perman ent da mage to th e

device.

U3 NC — — No connect, leave unconnected(2)

U2 NC — — No connect, leave un connected(2)

U1 NC — — No connect, leave un connected(2)

Table 5: Package Pin Identification - 208 BGA

Pin # Name I/O Level Description



VITESSE

SEMICONDUCTOR CORPORATION

Page 31

9/6/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Package Information

11. 45 DEG. 0.5 MM CHAMFER CORNER AND WHITE DOT FOR PIN1 IDENTIFICATION

10. BILATERIAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF PACKAGE BODY

8. CAVITY DEPTH VARIOUS WITH DIE THICKNESS

7. PACKAGE SURFACE SHALL BE BLACK OXIDE.

9. SUBSTRATE MATERIAL BASE IS COPPER.

BALLS AFTER DEPOPULATING.

SPHERICAL CROWNS OF THE SOLDER BALLS.

6. PRIMARY DATUM -C- AND SEATING PLANE ARE DEFINED BY THE

DIMENSION "aaa" IS MEASURED PARALLEL TO PRIMARY DATUM -C- .

PARALLEL TO PRIMARY DATUM -C- .

4. "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER

AND SYMBOL "N" IS THE MAXIMUM ALLOWABLE NUMBER OF

3. "M" REPRESENTS THE BASIC SOLDER BALL MATRIX SIZE,

2. "e" REPRESENTS THE BASIC SOLDER BALL GRID PITCH.

1. ALL DIMENSIONS ARE IN MILLIMETERS.

NOTES:

cccc

45 DEGREE 0.5MM CHAMFER

0.10 S C

0.30 S C A S B S

CORNER

(4 PLCS)

DETAIL B

DETAIL A

SIDE VIEW

TOP VIEW BOTTOM VIEW

DETAIL A

DETAIL B

-C-

aaa C

-B-

0.10

-A-

0.15

20.32 (BSC.)

23.00

0.70

0.65

0.60

0.85

0.65 0.90

0.75

1.45 1.55

ccc

208

1.27 TYP.

0.95

0.85

20.32 (BSC.)

23.00

1.65

aaa

AMAX.NOM.

MIN.REF.DIMENSIONAL REFERENCES

0.25

23.20

22.80

23.20

22.80

208 TBGA Package Drawings

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 32 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 9/6/00

G52251-0, Rev. 4.0

Package Thermal Considerations

This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the

die to the exposed surface of the heat spreader. The thermal resistance is shown in the following table:

Table 6: Thermal Resistance

Thermal Resistance with Airflow

Shown in the table below is the thermal resistance with airflow. This thermal resistance value reflects all the

thermal paths including through the leads in an environment where the leads are exposed. The temperature dif-

ference betw een the amb ient airflow tem perature a nd the case temperature s hould be the worst cas e power of

the device multiplied by the thermal resistance.

Table 7: Thermal Resistance with Airflow

Maximum Ambient Temperature without Heatsink

The worst case ambient temperature without use of a heatsink is given by the equation:

where:

θCA Theta case to ambient at appropriate airflow

ΤA(MAX) Ambient Air temperature

ΤC(MAX) Case temperature (110oC for VSC8140)

P(MAX) Power (2.75 W for VSC8140)

Symbol Description °C/W - (BGA) °C/W (PQFP)

θjc Thermal resistance from junction to case. 2.2 1.34

θca Thermal resistance from case to ambient with no airflow,

including co nduction throu gh the leads. 18.5 25.0

Airflow θca (oC/W) (BGA) θca (oC/W) (PQFP)

100 lf pm 18 21

200 lf pm 17 18

400 lf pm 16 16

TAMAX()

CMAX()

P–

MAX()

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SEMICONDUCTOR CORPORATION

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9/6/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

SC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

The results of this calculation are listed below:

Table 8: Maximum Ambient Air Temperature without Heatsink

Note that ambient air temperature varies throughout the system based on the positioning and magnitude of

heat sources and the direction of air flow.

Surface Mount Solderability

The make-up of each lead on the PQFP and TBGA packa ge is 85% Tin and 15% Lead. The soldera bility

requirements for the various methods is described below.

Reflow Soldering

This is the suitable method of soldering for these components. When using reflow soldering to mount the

IC package, sold er paste (a suspension of fine solder par ticles, flux, and bind in g agent ) is r equi red t o be appl i ed

to the printed-circuit board by screen printing, stenciling, or pressure-syringe dispensing before package place-

ment.

Throughput times (this includes preheating, soldering, and cooling) are shown in Table 9.

Table 9: Reflow Running Profile

Wave Soldering

Conventio nal singl e wave sol dering is not reco mmended for surfac e mount devices or pri nted circu it boar ds

with high component density, as solder bridging and non-wetting can present problems. Double-wave soldering

can be us ed, only if the me thod compr ises a tur bulent wave with high u pward pres sure follo wed by a smooth

laminar wave an d the footprint must inc orporate solder thieves at the downstream end. The pa ckage must be

fixed with a dropl et of a dhesi ve duri ng p lacement befo re sol deri ng. After the adhesi ve is cured, the pack age can

be soldered.

Airflow oC (TBGA) oC (PQFP)

None 59 41

100 lf pm 60 52

200 lf pm 63 60

400 lf pm 66 66

Condition TBGA PQFP

Average ramp up (from 183oC to peak temperature) 1.553oC/sec 1.5432oC/sec

Average ramp down (from peak to 183oC) -1.152oC/sec -1.085oC/sec

Preheat Temperature (125oC) 77 sec 79 sec

Temperature maintained above 183oC 80 sec 80 sec

Time within 5oC of actual peak temperature 19 sec 19 sec

Peak Temperature Range 220-225oC220-225

Peak Temperature 224oC224

Time 25oC to Peak Temperature 233 sec 228 sec

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 34 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 9/6/00

G52251-0, Rev. 4.0

Manual Soldering

When manually soldering the device to the printed circuit board, contact time should be limited to 10 sec-

onds at up to 240oC.

Layout Considerations

Refer to Application Note, AN56 “High-Speed Design Guidelines.”

Orderi ng Infor mat ion

The order number for this product is formed by a combination of the device type and package type.

Notice

Vitesse Semiconductor Corporation reserves the right to make changes in its products, specifications or

other information at any time without prior notice. Therefore the reader is cautioned to confirm tha t this data

sheet is current prior to placing any orders. The Company assumes no responsibility for any circuitry described

other than circuitry entirely embodied in a Vitesse product.

Warning

Vitesse Semiconduc tor Corporation’s produ cts are not intended for use in life support appliances, devices

or systems. Use of a Vitesse product in such applications without written consent is prohibited.

VSC8140 xx

Device Type

Package

2.48832Gb/s Multi-Rate SONET/SDH Transceiver

QR: 28-Pin PQF P, 14x20 mm

TW: 208-Pin BGA, 23x23mm