K60P100M100SF2V2
K60 Sub-Family
Supports the following:
MK60DN256VLL10,
MK60DX256VLL10, MK60DN512VLL10
Features
Operating Characteristics
Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range (ambient): -40 to 105°C
Performance
Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Memories and memory interfaces
Up to 512 KB program flash memory on non-
FlexMemory devices
Up to 256 KB program flash memory on
FlexMemory devices
Up to 256 KB FlexNVM on FlexMemory devices
4 KB FlexRAM on FlexMemory devices
Up to 128 KB RAM
Serial programming interface (EzPort)
FlexBus external bus interface
Clocks
3 to 32 MHz crystal oscillator
32 kHz crystal oscillator
Multi-purpose clock generator
System peripherals
Multiple low-power modes to provide power
optimization based on application requirements
Memory protection unit with multi-master
protection
16-channel DMA controller, supporting up to 63
request sources
External watchdog monitor
Software watchdog
Low-leakage wakeup unit
Security and integrity modules
Hardware CRC module to support fast cyclic
redundancy checks
Hardware random-number generator
Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
128-bit unique identification (ID) number per chip
Human-machine interface
Low-power hardware touch sensor interface (TSI)
General-purpose input/output
Analog modules
Two 16-bit SAR ADCs
Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
12-bit DAC
Two transimpedance amplifiers
Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
Voltage reference
Timers
Programmable delay block
Eight-channel motor control/general purpose/PWM
timer
Two 2-channel quadrature decoder/general purpose
timers
IEEE 1588 timers
Periodic interrupt timers
16-bit low-power timer
Carrier modulator transmitter
Real-time clock
Freescale Semiconductor Document Number: K60P100M100SF2V2
Data Sheet: Technical Data Rev. 3, 6/2013
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012–2013 Freescale Semiconductor, Inc.
Communication interfaces
Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability
USB full-/low-speed On-the-Go controller with on-chip transceiver
Two Controller Area Network (CAN) modules
Three SPI modules
Two I2C modules
Five UART modules
Secure Digital host controller (SDHC)
I2S module
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
2 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................5
1.1 Determining valid orderable parts......................................5
2 Part identification......................................................................5
2.1 Description.........................................................................5
2.2 Format...............................................................................5
2.3 Fields.................................................................................5
2.4 Example............................................................................6
3Terminology and guidelines......................................................6
3.1 Definition: Operating requirement......................................6
3.2 Definition: Operating behavior...........................................7
3.3 Definition: Attribute............................................................7
3.4 Definition: Rating...............................................................8
3.5 Result of exceeding a rating..............................................8
3.6 Relationship between ratings and operating
requirements......................................................................8
3.7 Guidelines for ratings and operating requirements............9
3.8 Definition: Typical value.....................................................9
3.9 Typical value conditions....................................................10
4 Ratings......................................................................................11
4.1 Thermal handling ratings...................................................11
4.2 Moisture handling ratings..................................................11
4.3 ESD handling ratings.........................................................11
4.4 Voltage and current operating ratings...............................11
5 General.....................................................................................12
5.1 AC electrical characteristics..............................................12
5.2 Nonswitching electrical specifications...............................12
5.2.1 Voltage and current operating requirements......13
5.2.2 LVD and POR operating requirements...............14
5.2.3 Voltage and current operating behaviors............14
5.2.4 Power mode transition operating behaviors.......16
5.2.5 Power consumption operating behaviors............17
5.2.6 EMC radiated emissions operating behaviors....20
5.2.7 Designing with radiated emissions in mind.........21
5.2.8 Capacitance attributes........................................21
5.3 Switching specifications.....................................................21
5.3.1 Device clock specifications.................................21
5.3.2 General switching specifications.........................22
5.4 Thermal specifications.......................................................23
5.4.1 Thermal operating requirements.........................23
5.4.2 Thermal attributes...............................................23
6 Peripheral operating requirements and behaviors....................24
6.1 Core modules....................................................................24
6.1.1 Debug trace timing specifications.......................24
6.1.2 JTAG electricals..................................................25
6.2 System modules................................................................28
6.3 Clock modules...................................................................28
6.3.1 MCG specifications.............................................28
6.3.2 Oscillator electrical specifications.......................30
6.3.3 32 kHz oscillator electrical characteristics..........33
6.4 Memories and memory interfaces.....................................33
6.4.1 Flash electrical specifications.............................33
6.4.2 EzPort switching specifications...........................38
6.4.3 Flexbus switching specifications.........................39
6.5 Security and integrity modules..........................................42
6.6 Analog...............................................................................42
6.6.1 ADC electrical specifications..............................42
6.6.2 CMP and 6-bit DAC electrical specifications......50
6.6.3 12-bit DAC electrical characteristics...................53
6.6.4 Voltage reference electrical specifications..........56
6.7 Timers................................................................................57
6.8 Communication interfaces.................................................57
6.8.1 Ethernet switching specifications........................57
6.8.2 USB electrical specifications...............................59
6.8.3 USB DCD electrical specifications......................59
6.8.4 USB VREG electrical specifications...................60
6.8.5 CAN switching specifications..............................60
6.8.6 DSPI switching specifications (limited voltage
range).................................................................61
6.8.7 DSPI switching specifications (full voltage
range).................................................................62
6.8.8 Inter-Integrated Circuit Interface (I2C) timing.....64
6.8.9 UART switching specifications............................65
6.8.10 SDHC specifications...........................................65
6.8.11 I2S/SAI switching specifications.........................66
6.9 Human-machine interfaces (HMI)......................................72
6.9.1 TSI electrical specifications................................72
7 Dimensions...............................................................................73
7.1 Obtaining package dimensions.........................................73
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 3
8 Pinout........................................................................................73
8.1 K60 signal multiplexing and pin assignments....................73
8.2 K60 pinouts.......................................................................77
9 Revision history.........................................................................78
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
4 Freescale Semiconductor, Inc.
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK60 and MK60.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field Description Values
Q Qualification status M = Fully qualified, general market flow
P = Prequalification
K## Kinetis family K60
A Key attribute D = Cortex-M4 w/ DSP
F = Cortex-M4 w/ DSP and FPU
M Flash memory type N = Program flash only
X = Program flash and FlexMemory
Table continues on the next page...
Ordering parts
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 5
Field Description Values
FFF Program flash memory size 32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB
R Silicon revision Z = Initial
(Blank) = Main
A = Revision after main
T Temperature range (°C) V = –40 to 105
C = –40 to 85
PP Package identifier FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
MJ = 256 MAPBGA (17 mm x 17 mm)
CC Maximum CPU frequency (MHz) 5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
N Packaging type R = Tape and reel
(Blank) = Trays
2.4 Example
This is an example part number:
MK60DN512ZVMD10
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
Terminology and guidelines
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
6 Freescale Semiconductor, Inc.
3.1.1 Example
This is an example of an operating requirement:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
0.9 1.1 V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol Description Min. Max. Unit
IWP Digital I/O weak pullup/
pulldown current
10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol Description Min. Max. Unit
CIN_D Input capacitance:
digital pins
7 pF
Terminology and guidelines
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 7
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
–0.3 1.2 V
3.5 Result of exceeding a rating
40
30
20
10
0
Measured characteristic
Operating rating
Failures in time (ppm)
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
Terminology and guidelines
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
8 Freescale Semiconductor, Inc.
3.6 Relationship between ratings and operating requirements
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
Never exceed any of the chip’s ratings.
During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
Lies within the range of values specified by the operating behavior
Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
Terminology and guidelines
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 9
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak
pullup/pulldown
current
10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
0.90 0.95 1.00 1.05 1.10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
150 °C
105 °C
25 °C
–40 °C
VDD (V)
I(μA)
DD_STOP
TJ
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
Terminology and guidelines
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
10 Freescale Semiconductor, Inc.
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level 3 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Ratings
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 11
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current 185 mA
VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V
VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB_DP USB_DP input voltage –0.3 3.63 V
VUSB_DM USB_DM input voltage –0.3 3.63 V
VREGIN USB regulator input –0.3 6.0 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
have CL=30pF loads,
are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
have their passive filter disabled (PORTx_PCRn[PFE]=0)
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
12 Freescale Semiconductor, Inc.
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
V
V
VIL Input low voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD V
IICDIO Digital pin negative DC injection current — single pin
VIN < VSS-0.3V -5 mA
1
IICAIO Analog2, EXTAL, and XTAL pin DC injection current —
single pin
VIN < VSS-0.3V (Negative current injection)
VIN > VDD+0.3V (Positive current injection)
-5
+5
mA
3
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
Negative current injection
Positive current injection
-25
+25
mA
VODPU Open drain pullup voltage level VDD VDD V4
VRAM VDD voltage required to retain RAM 1.2 V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT V
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
4. Open drain outputs must be pulled to VDD.
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 13
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
±80 mV
VLVDL Falling low-voltage detect threshold — low range
(LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
±60 mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
14 Freescale Semiconductor, Inc.
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Typ.1Max. Unit Notes
VOH Output high voltage — high drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
V
V
Output high voltage — low drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
V
V
IOHT Output high current total for all ports 100 mA
VOL Output low voltage — high drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOL = 10mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 5mA
0.5
0.5
V
V
2
Output low voltage — low drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1mA
0.5
0.5
V
V
IOLT Output low current total for all ports 100 mA
IINA Input leakage current, analog pins and digital
pins configured as analog inputs
VSS ≤ VIN ≤ VDD
All pins except EXTAL32, XTAL32,
EXTAL, XTAL
EXTAL (PTA18) and XTAL (PTA19)
EXTAL32, XTAL32
0.002
0.004
0.075
0.5
1.5
10
μA
μA
μA
3, 4
IIND Input leakage current, digital pins
VSS ≤ VIN ≤ VIL
All digital pins
VIN = VDD
All digital pins except PTD7
PTD7
0.002
0.002
0.004
0.5
0.5
1
μA
μA
μA
4, 5
IIND Input leakage current, digital pins
VIL < VIN < VDD
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.5 V
VDD = 1.7 V
18
12
8
3
26
49
13
6
μA
μA
μA
μA
4, 5, 6
Table continues on the next page...
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 15
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ.1Max. Unit Notes
IIND Input leakage current, digital pins
VDD < VIN < 5.5 V
1
50
μA
4, 5
ZIND Input impedance examples, digital pins
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.5 V
VDD = 1.7 V
48
55
57
85
4, 7
RPU Internal pullup resistors 20 35 50 8
RPD Internal pulldown resistors 20 35 50 9
1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted.
2. Open drain outputs must be pulled to VDD.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
5. Internal pull-up/pull-down resistors disabled.
6. Characterized, not tested in production.
7. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V.
8. Measured at VDD supply voltage = VDD min and Vinput = VSS
9. Measured at VDD supply voltage = VDD min and Vinput = VDD
+
Digital input
Source
ZIND
IIND
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSxRUN recovery times in the following table
assume this clock configuration:
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
16 Freescale Semiconductor, Inc.
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
VDD slew rate ≥ 5.7 kV/s
VDD slew rate < 5.7 kV/s
300
1.7 V / (VDD
slew rate)
μs
1
VLLS1 RUN 130 μs
VLLS2 RUN 92 μs
VLLS3 RUN 92 μs
LLS RUN 5.9 μs
VLPS RUN 5.0 μs
STOP RUN 5.0 μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V
@ 3.0V
37
38
63
64
mA
mA
2
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
@ 3.0V
@ 25°C
@ 125°C
46
47
58
77
63
79
mA
mA
mA
3, 4
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
20 mA 2
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
9 mA 5
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
1.12 mA 6
Table continues on the next page...
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 17
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
1.71 mA 7
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
0.77 mA 8
IDD_STOP Stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.74
2.45
6.61
1.41
11.5
30
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
83
425
1280
435
2000
4000
μA
μA
μA
IDD_LLS Low leakage stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
4.58
30.6
137
19.9
105
500
μA
μA
μA
9
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
3.0
18.6
84.9
23
43
230
μA
μA
μA
9
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
2.2
9.3
41.4
5.4
35
128
μA
μA
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
2.1
7.6
33.5
9
28
95.5
μA
μA
μA
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.19
0.49
2.2
0.22
0.64
3.2
μA
μA
μA
Table continues on the next page...
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
18 Freescale Semiconductor, Inc.
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VBAT Average current when CPU is not accessing RTC
registers
@ 1.8V
@ –40 to 25°C
@ 70°C
@ 105°C
@ 3.0V
@ –40 to 25°C
@ 70°C
@ 105°C
0.57
0.90
2.4
0.67
1.0
2.7
0.67
1.2
3.5
0.94
1.4
3.9
μA
μA
μA
μA
μA
μA
10
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
6. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA.
10. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies.
USB regulator disabled
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFL
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 19
Figure 2. Run mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 144LQFP and
144MAPBGA
Symbol Description Frequency
band (MHz)
144LQFP 144MAPBGA Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 23 12 dBμV 1, 2
VRE2 Radiated emissions voltage, band 2 50–150 27 24 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 28 27 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 14 11 dBμV
VRE_IEC IEC level 0.15–1000 K K 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
20 Freescale Semiconductor, Inc.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins 7 pF
CIN_D Input capacitance: digital pins 7 pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock 100 MHz
fSYS_USB System and core clock when Full Speed USB in
operation
20 MHz
fENET System and core clock when ethernet in operation
10 Mbps
100 Mbps
5
50
MHz
fBUS Bus clock 50 MHz
FB_CLK FlexBus clock 50 MHz
fFLASH Flash clock 25 MHz
fLPTMR LPTMR clock 25 MHz
VLPR mode1
fSYS System and core clock 4 MHz
Table continues on the next page...
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 21
Table 9. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fBUS Bus clock 4 MHz
FB_CLK FlexBus clock 4 MHz
fFLASH Flash clock 1 MHz
fERCLK External reference clock 16 MHz
fLPTMR_pin LPTMR clock 25 MHz
fLPTMR_ERCLK LPTMR external reference clock 16 MHz
fFlexCAN_ERCLK FlexCAN external reference clock 8 MHz
fI2S_MCLK I2S master clock 12.5 MHz
fI2S_BCLK I2S bit clock 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, and I2C signals.
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16 ns 3
External reset pulse width (digital glitch filter disabled) 100 ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 Bus clock
cycles
Port rise and fall time (high drive strength)
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
12
6
36
24
ns
ns
ns
ns
4
Table continues on the next page...
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
22 Freescale Semiconductor, Inc.
Table 10. General switching specifications (continued)
Symbol Description Min. Max. Unit Notes
Port rise and fall time (low drive strength)
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
12
6
36
24
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C
5.4.2 Thermal attributes
Board type Symbol Description 100 LQFP Unit Notes
Single-layer (1s) RθJA Thermal
resistance, junction
to ambient (natural
convection)
47 °C/W 1
Four-layer (2s2p) RθJA Thermal
resistance, junction
to ambient (natural
convection)
35 °C/W 1
Table continues on the next page...
General
K60 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 23