DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT107
Dual JK flip-flop with reset;
negative-edge trigger
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
FEATURES
•Output capability: standard
•ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr= tf= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW):
PD= CPD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay
CL= 15 pF;
VCC = 5 V
nCP to nQ 16 16 ns
nCP to nQ 1618ns
n
R to nQ, nQ 1617ns
f
max maximum clock frequency 78 73 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation
capacitance per flip-flop notes 1 and 2 30 30 pF
December 1990 3
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 8, 4, 11 1J, 2J, 1K, 2K synchronous inputs; flip-flops 1 and 2
2, 6 1Q, 2Q complement flip-flop outputs
3, 5 1Q, 2Q true flip-flop outputs
7 GND ground (0 V)
12, 9 1CP, 2CP clock input (HIGH-to-LOW, edge-triggered)
13, 10 1R, 2R asynchronous reset inputs (active LOW)
14 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
Fig.4 Functional diagram. Fig.5 Logic diagram (one flip-flop).
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP
transition
X = don’t care
↓= HIGH-to-LOW CP transition
OPERATING MODE INPUTS OUTPUTS
nRnCP J K Q Q
asynchronous reset L X X X L H
toggle H ↓hhqq
load “0” (reset) H ↓IhL H
load “1” (set) H ↓hIH L
hold “no change” H ↓IIq q
December 1990 5
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HC UNIT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41 ns 2.0
4.5
6.0 Fig.6
tPHL/ tPLH propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41 ns 2.0
4.5
6.0 Fig.6
tPHL/ tPLH propagation delay
nR to nQ, nQ
52
19
15
155
31
26
195
39
33
235
47
40 ns 2.0
4.5
6.0 Fig.7
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19 ns 2.0
4.5
6.0 Fig.6
tWclock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20 ns 2.0
4.5
6.0 Fig.6
tWreset pulse width
LOW
80
16
14
22
8
6
100
20
17
120
24
20 ns 2.0
4.5
6.0 Fig.7
trem removal time
nR to nCP
60
12
10
19
7
6
75
15
13
90
18
15 ns 2.0
4.5
6.0 Fig.7
tsu set-up time
nJ, nK to nCP
100
20
17
22
8
6
125
25
21
150
30
26 ns 2.0
4.5
6.0 Fig.6
thhold time
nJ, nK to nCP
3
3
3
−6
−2
−2
3
3
3
3
3
3ns 2.0
4.5
6.0 Fig.6
fmax maximum clock pulse
frequency
6.0
30
35
23
70
85
4.8
24
28
4.0
20
24 MHz 2.0
4.5
6.0 Fig.6
December 1990 6
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: flip-flops
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tf= tf= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
nK
nR
nCP, nJ
0.60
0.65
1.00
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP to nQ 19 36 45 54 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
nCP to nQ 21 36 45 54 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
nR to nQ, nQ 20 38 48 57 ns 4.5 Fig.7
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6
tWclock pulse width
HIGH or LOW 16 9 20 24 ns 4.5 Fig.6
tWreset pulse width
LOW 20 11 25 30 ns 4.5 Fig.7
trem removal time
nR to nCP 14 8 18 21 ns 4.5 Fig.7
tsu set-up time
nJ, nK to nCP 20 7 25 30 ns 4.5 Fig.6
thhold time
nJ, nK to nCP 5−2 5 5 ns 4.5 Fig.6
fmax maximum clock pulse
frequency 30 66 24 20 MHz 4.5 Fig.6
December 1990 7
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J
and K to nCP set-up and hold times, the output transition times and the maximum clock pulse frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays, the reset pulse width and
the nR to nCP removal time.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
