© 2001 Fairchild Semiconductor Corporation DS006037 www.fairchildsemi.com
October 1987
Revised April 2001
MM74C922 • MM74C923 16-Key Encoder • 20-Key Encoder
MM74C922 MM74C923
16-Key Encoder 20-Key Encoder
General Description
The MM74C922 and MM74C923 CMOS key encoders pro-
vide all the necessary logic to fully encode an array of
SPST switches. The keyboard scan can be implemented
by either an external clock or external capacitor. These
encoders also have on-chip pull-up devices which permit
switches with up to 50 k on resistance to be used. No
diodes in the switch array are needed to eliminate ghost
switches. The internal debounce circuit needs only a single
external capacitor and can be defeated by omitting the
capacitor. A Data Available output goes to a high level
when a valid keyboard entry has been made. The Data
Available output returns to a low level when the entered
key is released, even if another key is depressed. The Data
Available will return high to indica te a cceptan ce of t he new
key after a norma l debounce period; this two-key roll-over
is provided between any two switches.
An internal register remembers the last key pressed even
after the key is rele ased. T he 3 -STATE outputs provid e for
easy expansion and bus operation and are LPTTL compat-
ible.
Features
50 k maximum switch on resistance
On or off chip clock
On-chip row pull-up devices
2 key roll-over
Keybounce elimination with single capacitor
Last key register at outputs
3-STATE output LPTTL compatible
Wide supply range: 3V to 15V
Low power consu mp ti on
Ordering Code:
Device a ls o av ailable in Tape and Reel. Specify by a ppending s uffix let te r “X” to the or dering code.
Connection Diagrams
Pin Assignment for DIP
Top View
MM74C922
Pin Assignment for SOIC
Top View
MM74C922
Order Number Package Number Package Description
MM74C922WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74C922N N18B 18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74C923WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74C923N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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MM74C922 MM74C923
Connection Diagrams (Continued) Pin Assignment for
DIP and SOIC Package
Top View
MM74C923
Truth Tables
(Pins 0 through 11)
(Pins 12 through 19)
Note 1: Omit for MM 74C92 2
Switch 01234 5678910 11
Position Y1, X1 Y1, X2 Y1, X3 Y1, X4 Y2, X1 Y2, X2 Y2, X3 Y2, X4 Y3, X1 Y3, X2 Y3, X3 Y3, X4
D
AA 010101010101
TB 001100110011
AC 000011110000
OD 000000001111
UE (Note 1)000000000000
T
Switch 12 13 14 15 16 17 18 19
Position Y4, X1 Y4, X2 Y4, X3 Y4, X4 Y5(Not e 1), X1 Y5 (Note 1), X2 Y5 (Note 1), X3 Y5 (Note 1), X4
D
AA 0101 0 1 0 1
TB 0011 0 0 1 1
AC 1111 0 0 0 0
OD 1111 0 0 0 0
U E (Note 1) 0 0 0 0 1 1 1 1
T
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MM74C922 MM74C923
Block Diagram
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MM74C922 MM74C923
Absolute Maximum Ratings(Note 2)
Note 2: Absolute Maximum Ratings are those values beyond which the
safety of t he device ca nnot be guara nt eed. Ex cept f or Operating Tempera-
ture Range they a re not mean t to imply that the devices s hould be oper-
ated at these limits. The table of Electrical Characteristics provides
conditions for act ual devi c e operation.
DC Electrical Characteristi cs
Min/Max limits apply across temperature range unless otherwise specified
Voltage at Any Pin VCC 0.3V to V CC + 0.3V
Operating Temperature Range
MM74C922, MM74C923 40°C to +85°C
Storage Temperature Range 65°C to +150°C
Power Dissipation (P D)
Dual-In-Line 700 mW
Small Outline 500 mW
Operating VCC Range 3V to 15V
VCC 18V
Lead Temperature
(Soldering, 10 seconds) 260°C
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
VT+Posi tiv e-Going Threshold Voltage VCC = 5V, IIN 0.7 mA 3.0 3.6 4.3 V
at Osc and KBM Inputs VCC = 10V, IIN 1.4 mA 6.0 6.8 8.6 V
VCC = 15V, IIN 2.1 mA 9.0 10 12.9 V
VT Negative-Going Threshold Voltage VCC = 5V, IIN 0.7 mA 0.7 1.4 2.0 V
at Osc and KBM Inputs VCC = 10V, IIN 1.4 mA 1.4 3.2 4.0 V
VCC = 15V, IIN 2.1 mA 2.1 5 6.0 V
VIN(1) Logical 1 Input Voltage, VCC = 5V 3.5 4.5 V
Except Osc and KBM Inputs VCC = 10V 8.0 9 V
VCC = 15V 12.5 13.5 V
VIN(0) Logical 0 Input Voltage, VCC = 5V 0.5 1.5 V
Except Osc and KBM Inputs VCC = 10V 1 2 V
VCC = 15V 1.5 2.5 V
Irp Row Pull-Up Current at Y1, Y2, VCC = 5V, VIN = 0.1 VCC 25µA
Y3, Y4 and Y5 Inputs VCC = 10V 10 20 µA
VCC = 15V 22 45 µA
VOUT(1) Logical 1 Output V ol tag e VCC = 5V, IO = 10 µA4.5 V
VCC = 10V, IO = 10 µA9 V
VCC = 15V, IO = 10 µA13.5 V
VOUT(0) Logical 0 Output V ol tag e VCC = 5V, IO = 10 µA0.5V
VCC = 10V, IO = 10 µA 1V
VCC = 15V, IO = 10 µA 1.5V
Ron Column ON Resistance at VCC = 5V, VO = 0.5V 500 1400
X1, X2, X3 and X4 Outputs VCC = 10V, VO = 1V 300 700
VCC = 15V, VO = 1.5V 200 500
ICC Supply Current VCC = 5V 0.55 1.1 mA
Osc at 0V, (one Y low) VCC = 10V 1.1 1.9 mA
VCC = 15V 1.7 2.6 mA
IIN(1) Logical 1 Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA
at Output Enable
IIN(0) Logical 0 Input Current VCC = 15V, VIN = 0V 1.0 0.005 µA
at Output Enable
CMOS/LPTTL INTERFACE
VIN(1) Except Osc and KBM Inputs VCC = 4.75V VCC 1.5 V
VIN(0) Except Osc and KBM Inputs VCC = 4.75V 0.8 V
VOUT(1) Logical 1 Output V ol tag e IO = 360 µA
VCC = 4.75V 2.4 V
IO = 360 µA
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MM74C922 MM74C923
DC Electrical Characteristics (Continued)
AC Electrical Characteristics (Note 3)
TA = 25°C, CL = 50 pF, unless otherwise noted
Note 3: AC Paramet ers are guaranteed by DC co rrelated te s tin g.
Note 4: Capacitance is guaranteed by periodic testing.
Symbol Parameter Conditions Min Typ Max Units
VOUT(0) Logical 0 Output Voltage IO = 360 µA
VCC = 4.75V 0.4 V
IO = 360 µA
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE Output Source Current VCC = 5V, VOUT = 0V, 1.75 3.3 mA
(P-Channel) TA = 25°C
ISOURCE Output Source Current VCC = 10V, VOUT = 0V, 815 mA
(P-Channel) TA = 25°C
ISINK Output Sink Current VCC = 5V, VOUT = VCC, 1.75 3.6 mA
(N-Channel) TA = 25°C
ISINK Output Sink Current VCC = 10V, VOUT = VCC, 816 mA
(N-Channel) TA = 25°C
Symbol Parameter Conditions Min Typ Max Units
tpd0, tpd1 Propagation Delay Time to CL = 50 pF (Figure 1)
Logical 0 or Logical 1 V
CC = 5V 60 150 ns
from D.A. VCC = 10V 35 80 ns
VCC = 15V 25 60 ns
t0H, t1H Propagation Delay Time from RL = 10k, CL = 10 pF (Figure 2)
Logical 0 or Logical 1 V
CC = 5V, RL = 10k 80 200 ns
into High Impedance State VCC = 10V, C L = 10 pF 65 150 ns
VCC = 15V 50 110 ns
tH0, tH1 Propagation Delay Time from RL = 10k, CL = 50 pF (Figure 2)
High Impedance State to a VCC = 5V, RL = 10k 100 250 ns
Logical 0 or Logical 1 V
CC = 10V, CL = 50 pF 55 125 ns
VCC = 15V 40 90 ns
CIN Input Capacitance Any Input (Note 4) 5 7.5 pF
COUT 3-STATE Output Capacitance Any Output (Note 4) 10 pF
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MM74C922 MM74C923
Switching Time Waveforms
T1 T2 RC, T3 0.7 RC, where R 10k and C is external capacitor at KBM input.
FIGURE 1.
FIGURE 2.
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MM74C922 MM74C923
Typical Performance Characteristics
Typical Irp vs VIN at Any Y Input Typical Ron vs VOUT at Any X Output
Typical FSCAN vs COSC Typical Debounce Period vs CKBM
Typical Applications
Synchronous Handshake (MM74C922)
The keyboard may be synchronously scanned by omitting the capacitor at
osc. and driving osc. directly if the system clock rate is lower than 10 kHz
Synchronous Data Entry Onto Bus (MM74C922)
Outpu ts are en abled when valid en try is ma de an d go int o 3-STAT E when
key is released.
The keyboard may be synchronously scanned by omitting the capacitor at
osc. and driving osc. directly if the system clock rate is lower than 10 kHz
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MM74C922 MM74C923
Asynchronous Data Entry Onto Bu s (MM74C922)
Outp ut s are in 3-STATE until key is pres s ed, then dat a is placed on bus. W hen key is released, out puts return to 3-S TATE.
Expansion to 32 Key Encoder (MM74C922)
Theory of Operation
The MM74C922/MM74C923 Keyboard Encoders imple-
ment all the logic necessary to interface a 16 or 20 SPST
key switch matrix to a digital syste m. The encod er will con-
vert a key switch closer to a 4(MM74C922) or
5(MM 74C 9 23 ) bit ni bb l e. Th e des i gne r ca n co nt rol bo t h the
keyboar d scan rate and the key deboun ce period by alter -
ing the oscillator capacitor, COSE, and the key bounce
mask capacitor, CMSK. Thu s, the MM74 C922 /MM74C92 3s
perfor man c e can be opt imiz ed for many keyboar ds.
The keyboard encoders connect to a switch matrix that is 4
rows by 4 columns (MM74C922) or 5 rows by 4 columns
(MM74C923). When no keys are depressed, the row inputs
are pul le d h igh b y inte rn al pu l l-up s an d th e co l um n o utpu ts
sequentially output a logic 0. These outputs are open
drai n and are therefor e low fo r 25% of th e time and other -
wise off. The c olumn scan r ate is controlled b y the osci lla-
tor input, which con sists of a Schmitt trigger o scillator, a 2-
bit counter, and a 24-bit dec ode r.
When a ke y is depressed, key 0, for example, nothing will
happen when the X1 input is o ff, since Y1 will remain high.
When the X1 column is scanned, X1 goes low and Y1 will
go low. This disables the counter and keeps X1 low. Y1
going low also initiates the key bounce circuit timing and
locks out the other Y inputs. The key code to be output is a
combination of the frozen counter value and the decoded Y
inputs. Once the key bounce circuit times out, the data is
latched, and the Data Available (DAV) output goes high.
If, during th e key closure the swit ch bounces, Y1 input will
go high again, restarting the scan and resetting the key
bounce circuitry . The key may bounce several times, but as
soon as the switch stays low for a debounce period, the
closur e is a ssumed valid and the data i s lat ched.
A key may also bounce whe n it is released. To ensure that
the encoder does not recognize this bounce as another key
closure, the debou nce ci rcuit mu st time ou t befor e anoth er
closure is recogn ized.
The two-key roll-over feature can be illustrated by assum-
ing a key is depressed, and then a second key is
depressed. Since all scanning has stopped, and all other Y
inputs are d isabled, th e second key is n ot recognized until
the first key is lifted and the key bounce circuitry has reset.
The out put latches fe ed 3-STATE, which is enabled when
the Output Enable (OE) input is taken low.
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MM74C922 MM74C923
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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MM74C922 MM74C923
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N18B
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MM74C922 MM74C923 16-Key Encoder 20-Key Encoder
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circu it patent licenses are im plied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
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to perform when properly used in accordance with
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sonably expected to result in a significant injury to the
user.
2. A criti cal com ponen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
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