HARRIS SEMICOND SECTOR } HARRIS WYE D MM 4302271 0037711 3 BMHAS 7 Y3-2] CD40107B Types CMOS Dual 2-Input Features: NAN D B ff | 32 times standard B-Series output current i drive sinking capability 136 mA typ. uffer/Driver eye any . ons High-Voltage Type (20-Volt Rating) = 100% tested for quiescent current at 20 V >t CD401078 is a dual 2-input NAND = Maximum input current of 1 2A at 18 V Vg5 'sa dual -inpu over full package-temperature range; buffer/driver containing two independent 2- 100 nA aig Vand 250C input NAND buffers with open-drain single B 5-V, 10-V, and 15-V parametric ratings Tanne a aOR cabal by d nigh Noise margin, full package temperature b Ede output sink current capability (136 mA typ. range, FL wy ee > ply at Vpp = 10 V, Vpg = 1 V), The CD401078 at Vpp = 5 gs is supplied in the 8-lead dual-in-line plastic 2VatVop= 10V s2ce-20a34m (Mini-DIP) package (E suffix), 14-lead her- 2.5 Vat Vpop = 15 V . metic frit-seal ceramic package (F suffix), Meets ail requirements of JEDEC Tentative FUNCTIONAL DIAGRAM and in chip form (H suffix) Standard No. 13B, Standard Specifications Pp . for Description of 'B Series CMOS Devices Yoo Applications Driving relays, lamps, LEDs : Line driver \ oe-mt TRUTH TABLE Level shifter (up or down) A Gay) 3,095 o|1* > E 9 0 1? 4 - - o[ifi , wet *Requires external oe Voo* a a - Yoo Yss 80 pull-up resistor Vss*(7].4 (RL) to Vpp. * ALL INPUTS PROTECTED #Without pull-up NOTE NUMBERS IN PROTECTION NETWORK resistor {3-state}. SQUARES FOR CO40W78F, 2 OTHERS FOR CO40:078E gs 928-25435RI Fig. 1 Schematic diagram of CD401078 fone of 2 gates) MAXIMUM RATINGS, Absolute-Maximum Values: DC SUPPLY-VOLTAGE RANGE, (Vpp) Voltages referenced to Vgg Terminal) ... INPUT VOLTAGE RANGE, ALL INPUTS ... ORAIN-TO-SOURCE VOLTAGE (Vps]V : . 9208-29444 OC INPUT CURRENT, ANY ONE INPUT ...... 0. ccc cee e cence erate sneestetece seeee STOMA . oo ae POWER DISSIPATION PER PACKAGE (Pp): * Fig.2 Typical autput low {sink} For Ta = -55C t0 $1009 occ e cece eee e rece e eee ees see e eect eee eees 500mW current characteristics. For TA = +1009 to +1259 woe esc e cece eee Derate Linearity at 12mW/C to 200mW . : DEVICE DISSIPATION PER OUTPUT TRANSISTOR . FOR Ta = FULL PACKAGE-TEMPERATURE RANGE (All Package Types).........- 100mWw OPERATING-TEMPERATURE RANGE (Ta) . STORAGE TEMPERATURE RANGE (Tstg) seen cena cveee nes econnee eeneees 65C to +1509C LEAD TEMPERATURE (DURING SOLDERING): . At distance 1/16 + 1/32 inch (1.59 + 0.79mm) from case for 10s max ..... seenuees +265C RECOMMENDED OPERATING CONDITIONS For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges: LIMITS. CHARACTERISTIC UNITS MIN. MAX. ORAIY-T0-SOURCE VOLTAGE Supply-Voitage Range (For Ta= Szes-294esnt Full Package-Temperature Range) 3 18 Vv Fig.3 ~- Minimum output low (sink) current characteristics. 3-392HARRIS SEMICOND SECTOR 4W4E D im 430e2?) OO377L2 5 MMHAS CD40107B Types 7-Y3-Q1 DYNAMIC ELECTRICAL CHARACTERISTICS at Ta = 25C, C_=50 pF, Input ty. te= 20 ns AMBIENT TEMPERATURE (T4} ali TEST CONDITIONS LIMITS CHARACTERISTIC Vpp UNITS Volts | Typ. | Max. 5 100 200 RL*=1202 | 10 45 90 ns 15 30 60 5 100 200 Propagation Delay: High-to-Low, tpy_ Low-to-High, tpry R_*=120Q2 | 10 60 120 ns 15 50 160 ROAD CAPAGITANCE (6.}0F 9zcs-29437 wos . 5 50 100 Fi ani sete of . : ig.4 Typical transition time as a function of Transition Time: RL*= 1202 | 10 20 40 ns load capacitance, High-to-Low, trp 15 10 20 5 50 100 a) Low-to-High, trey Ri* =1202 | 10 35 70 ns 18 25 50 Average Input Capacitance, Cjjy Any Input 5 76 pF Average Output Capacitance, CQUT Any Output 30 - pF * RL is external pull-up resistor to Vpp. 3 8 oy ze 3 Wi > COAD CAPACITANCE (C.} pF 2x 928-29430Rt Ss Ss STATIC ELECTRICAL CHARACTERISTICS Fig.5 Typical propagation delay time as a ot function of load capacitance. CONDITIONS LIMITS AT INDICATED TEMPERATURES (C) = CHARACTER- r IsTIC UNITS a Vo {| Vin |Voo +25 g g (v) (v) | (vi) | -55 | -40 | +85 [+125 ] Min. Typ. | Max. 5 _ _ 2 Qu; it Device 06] 5 1 1 30 30 0.02 1 e Cu - 0,10] 10 | 2 2 60 60 - |.0.02 |] 2 a rrent HA ee IDp Max. - 015} 15 | 4 4 |120 | 120 - {002 | 4 & - 0,20} 20 | 20 20 | 600 | 600 | 0.04 } 20 8 Output Low o4 | 05 | 5 | 21 7 20 [14 [ 12 | ie] 32 | 5 (Sink) Current |__! O5 | 5 | 44 | 42 | 30 | 25 | 34] oa [| 5 TS Poo IOL Min. 0.5 0,10 | 10 | 49 46 32 28 37 74 - < 1 O10] 10 | 89 [85 feo [ 51 | 68 | i367 mA (tg) ate 0.5 0,15 | 15 | 66 63 | 44 38 50 | 100 - . ; s2c$-2s4sani ~ Fig.6 Typical power dissipation as a Cigna ion function of input frequency. Current No Internal Pull-Up Device : {OH Min. Input Low 4.5 - 5 1.6 - - 1.5 Voltage 9 | 10 3 ~_ - 3 cot Vit Max.* 135 | | 15 4 =|. 14 OnE v laput High 0.5,4.5 | 5 3.5 35] - - Voltage 19 | [10 7 7{ {| ceneaaton | Vin Min.* TTei3st | 15 11 wl - fe Input Current 2 li Max. - 0,18] 18 } 4011404] 41 | 31 [4105] 401 | ya oUF Output Leakage ~ Current 18 [0,18] 18] 2 | 2 | 20 | 20 | - | 104] 2 BA s2es-29435 loz Max. : Fig. 7 Powar-dissipation test circuit * Measured with external pull-up resistor, RL = 10kQ to Vop. * for c04010786. . 3-393HARRIS SEMICOND SECTOR WUE D MM 4302271 00357713 7 BMHAS CD40107B Types T-43 Al Yoo Inputs ! Yes 55-63 ha (!.397-1.600) azea-274cat Fig.8 Quiescent-device -~ current test circuit. MEASURE INPUTS SEQUENTIALLY, TO GOTH Vp ANO Veg- CONNECT ALL UNUSED urs | Yoo ~ NOTE: ~~ 92C$-29410R2 Vs _ ~ NOTE: NOS. IN PADS FOR CD401078E NOS. OUTSIOE CHIP FOR CD401078F von Otay Vss it ie fe D40107BH. Dimensions and Pad Layaut for CD401078: sace-artoz Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as in- Fig. 9 input-current test dicated. Grid graduations are in mits {10-3 inch). i pu cireuit. Yeo (aPuts | | gutputs vin wv Lam _- beam vit _ Lee = pee Vss MOTE: a Yoo Ne Ineiy SoMs nario 92s-za4it NC . i, Fig.10 ~ input-voltage ox ons -- test circuit, Ne Vss FOE Ves TOP view stes-s000 Special Considerations for CD40107B S2CS-2FBI9RT . tae. 1. Limiting Capacitive Currents for CL > cn401078e cp4o107BF ~~" 600 pF, Vpp > 15 V. / TERMINAL ASSIGNMENTS - For Vpp > 15 V, and load capacitance (CL) from output to ground > 500 pF, an external 25 22 series limiting resistor - should be inserted between the output terminal and Cz. No external resistor is necessary if CL < 500 pF or Vpp < 18 Vi . 7 2. Driving Inductive Loads When using the CD40107B to drive In- ductive loads, the load should be shunted - with a diode to prevent high voltages from developing across the CD401078 : output, 3-394