74LCX244MTCX_NL - Fairchild Semiconductor

Februa ry 199 4

Revised March 2005

74LCX244 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs

74LCX244

Low Voltage Buffer/Line Driver

with 5V Tolerant Inputs and Outputs

General Descript ion

The LCX244 contains eight non-inverting buffers with

3-S TA TE out p uts. The dev i ce may be em pl oy ed as a me m-

ory address driver, clock driver and bus-oriented transmit-

ter/recei ver. The LCX244 is desi gne d for low voltage (2.5V

or 3.3V) V CC applications with capability of interfacing to a

5V signal environment.

The LCX244 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■5V tolerant inputs and outputs

■2.3V to 3.6V VCC specifications provided

■6.5 ns tPD max (VCC

3.3V), 10

A ICC max

■Power down high impedance inputs and outputs

■Supports live insertion/withdrawal (Note 1)

■

24 mA output drive ( VCC

3.0V)

■Implements patented noise/EMI reduction circuitry

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human bod y mode l

2000V

Machine model

200V

■Leadless DQFN Pb-Free package

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to VCC throug h a pull-up re sistor: the minim um value or the

resisto r is det ermin ed by the current-so urc ing capa bility of the driv er.

Ordering Code:

Pb-Free package per JEDEC J-STD-020B.

Note 2: Devices also availab le in Tape and Re el. Sp ec if y by appending the su ffix let te r “X” to the or dering code.

Note 3: DQFN packag e av ailable in Tape and Reel only.

Note 4: “_NL” indicat es Pb-Fre e pac k age (per JE D EC J -STD-020B). Please us e order number as i ndicated .

Order Number Package

Number Package Description

74LCX244WM

(Note 2) M2 0B 20- L ead Small Outline Integrated Circuit (S OIC), JEDEC MS-013, 0 .300" W ide

74LCX244WMX_NL

(Note 4) M20B Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LCX244SJ

(Note 2) M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX244BQX

(Note 3) MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 4.5mm

74LCX244MSA

(Note 2) MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LCX244MTC

(Note 2) MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LCX244MTC_NL

(Note 4) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74LCX244MTCX_NL

(Note 4) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

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74LCX244

Logic Symbol

IEEE/IEC

Connection Diagrams

Pin Assignments for

SOIC, SOP, SSOP, and TSSO P

Pad Assignments for DQFN

(Top Through View)

Pin Descriptions

Tr uth Tables

HIGH Voltage Level

LOW Voltage Level

Immaterial

High Impedance

Pin Names Description

OE1, OE23-STATE Output Enable Inputs

I0 – I7Inputs

O0 – O7Outputs

Inputs Outputs

OE1In(Pins 12, 14, 16, 18)

LL L

LH H

HX Z

Inputs Outputs

OE2In(Pins 3, 5, 7, 9)

LL L

LH H

HX Z

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74LCX244

Absolute Maximum Ratings(Note 5)

Recommended Operating Conditions (Note 7)

Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be oper at ed

at these limits. The para metric value s defined in the Elec trical Cha racteristic s tables are n ot guarantee d at the A bsolute Ma ximum R atings . The “Recom-

mended Operating Conditions” table will def ine the con dit ions for act ual dev ic e operation.

Note 6: IO Absolu te Maximu m Rating must be observed.

Note 7: Unused input s o r I/Os must b e held HIGH or LOW. They m ay not f loat.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



7.0 V

VIDC Input Voltage



0.5 to



7.0 V

VODC Output Voltage



0.5 to



7.0 Output in 3-STATE V



0.5 to VCC



0.5 Output in H IGH or LOW State (Note 6)

IIK DC Input Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA



50 VO

VCC

IODC Output Source/Sink Current

50 mA

ICC DC Supply Current per Supply Pin

100 mA

IGND DC Ground Current per Ground Pin

100 mA

TSTG Storage Temperature



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Volt age 0 5.5 V

VOOutput Volt age HIGH or LOW State 0 VCC V

3-STATE 0 5.5

IOH/IOL Output Current VCC

3.0V to 3.6V

24 mAVCC

2.7V to 3.0V

VCC

2.3V to 2.7V

TAFree-Ai r Ope rat ing Temperatu re



40 85

V Input Edge Rate, VIN

0.8V to 2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

VIH HIGH Level Input Voltage 2.3 to 2.7 1.7 V

2.7 to 3.6 2.0

VIL LOW Level Input Voltage 2.3 to 2.7 0.7 V

2.7 to 3.6 0.8

VOH HIGH Level Output Voltage IOH



100

A 2.3 to 3.6 VCC



0.2

IOH



8 mA 2.3 1.8

IOH



12 mA 2.7 2.2

IOH



18 mA 3.0 2.4

IOH



24 mA 3.0 2.2

VOL LOW Level Output Voltage IOL

100

A 2.3 to 3.6 0.2

IOL

8 mA 2.3 0.6

IOL

12 mA 2.7 0.4

IOL

16 mA 3.0 0.4

IOL

24 mA 3.0 0.55

IIInput Leakage Current 0

5.5V 2.3 to 3.6

5.0

IOZ 3-STATE Output Leakage 0

5.5V 2.3 to 3.6

5.0

VIH or VIL

IOFF Power-Off Leakage Current VI or VO

5.5V 0 10

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74LCX244

DC Electrical Characteristics (Continued)

Note 8: Outputs disabled or 3-STATE only.

AC Electrical Characteristics

Note 9: Skew is de fi ned as th e absolut e valu e of the difference betwee n t he ac tu al propaga t ion delay f or any t w o separa t e outputs of t he same device. The

specif ic ation ap plies to an y o ut puts switch ing in the same direc t ion, either HIGH-to- LOW (tOSHL) or LO W-to-HIGH (t OSLH).

Dynamic Switching Characteristics

Capacitance

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

ICC Quiescent Supply Current VI

VCC or GND 2.3



3.6 10

3.6V

VI, VO

5.5V (Note 8) 2.3



3.6

ICC Increase in ICC per Input VIH

VCC



0.6V 2.3



3.6 500

Symbol Parameter



C to



C, RL

500

Units

VCC

3.3V

0.3V VCC

2.7V VCC

2.5V

0.2

50 pF CL

30 pF

Min Max Min Max Min Max

tPHL Propagation Delay 1.5 6.5 1.5 7.5 1.5 7.8 ns

tPLH Data to Output 1.5 6.5 1.5 7.5 1.5 7.8

tPZL Output Enable Time 1.5 8.0 1.5 9.0 1.5 10.0 ns

tPZH 1.5 8.0 1.5 9.0 1.5 10.0

tPLZ Output Disable Time 1.5 7.0 1.5 8.0 1.5 8.4 ns

tPHZ 1.57.01.58.01.58.4

tOSHL Output to Output Skew

(Note 9) 1.0 ns

tOSLH 1.0

Symbol Parameter Conditions VCC TA

CUnits

(V) Typical

VOLP Quiet Output Dynamic Peak VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3 0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5 0.6

VOLV Quiet Output Dynamic Valley VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3



0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5



0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC

Open, VI

0V or VCC 7.0 pF

COUT Output Capacitance VCC

3.3V, VI

0V or VCC 8.0 pF

CPD Power Dissipation Capacitance VCC

3.3V, VI

0V or VCC, f

10 MHz 25.0 pF

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74LCX244

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and trec Waveforms

3-STATE Output Low Enable and

Disable Times for L o gic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

trise and tfall

FIGURE 2. Waveform s

(Input Characteristics; f =1MHz, tr = tf = 3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC

3.3V

0.3V

VCC x 2 at VCC

2.5V

0.2V

tPZH, tPHZ GND

Symbol VCC

3.3V

0.3V 2.7V 2.5V

0.2V

Vmi 1.5V 1.5V VCC/2

Vmo 1.5V 1.5V VCC/2

VxVOL



0.3V VOL



0.3V VOL



0.15V

VyVOH



0.3V VOH



0.3V VOH



0.15V

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74LCX244

Schematic Diagram Generic for LCX Family

FIGURE 3.

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74LCX244

Tape and Reel Specification

Tape Format for DQFN

TAPE DIMENSIONS inches (millimeters)

REEL DIMENSIONS inches (millimeters)

Packa ge Tap e Number Cavit y Cove r Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

BQX Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Tape SizeABCDNW1W2

12 mm 13.0 0.059 0.512 0.795 2.165 0.488 0.724

(330.0) (1.50) (13.00) (20.20) (55.00) (12.4) (18.4)

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74LCX244

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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74LCX244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

www.fairchildsemi.com 10

74LCX244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm

Packag e Num b er MLP02 0B

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74LCX244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Package Numb er MSA20

www.fairchildsemi.com 12

74LCX244 Low Voltage Buffer /Line Driver with 5V Tolerant Inputs and Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLI CY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.