ANALOG DEVICES Low Cost, 14-Bit, Dual Channel Synchro/Resolver-to-Digital Converter AD2S44 FEATURES Low Cost/Channe! 32-Pin DL Hybrid Package 2.6 Are Minute Accuracy 14-Bit Resolution Built-In Test independent Reference Inputs High Tracking Rates APPLICATIONS Gimbat/Gyro Control Systems Robotics Engine Controllers Coordinate Conversion Miltary Servo Control Systems Fise Control Systems Avionic Systems Antenne Monitoring CNC Machine Tooling GENERAL DESCRIPTION The AD2S44 series are 14-bit dual channel, continuous tracking synchro/resolver-to-digital converters. They have been designed specifically for applications where space, weight and cost are at 8 premium. Each 32-pin hybrid device contains two independent Type 11 servo loop tracking converters. The ratiometric conver- sion technique employed provides excellent noise immunity and tolerance of long lead lengths. The core of each conversion is performed by state-of-the-art monolithic integrated circuits manufactured in Analog Devices proprietary BiMOS IT process which combines the advantages of low power CMOS digital logic with bipolar linear circuits. The use of these JCs keeps the internal component count low and ensures high reliability. The built-in test (BIT) faciliry can be used in failsafe systems to provide an indication of whether the converter is urucking accurately. Each channel incorporates a high accuracy differential condition- ing circuit for signal inputs providing more than 74 dB of com- mon mode rejection. Options are available for both synchro and resolver format inputs. The converter output is via a tristate transparent latch allowing data to be read without interruption of converter operation. The A/B and OE control lines select the REV. A information furnished by Analog Devices is believed to be accurate and reliable, However, no reeponsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result {rom its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM n't] ip tl Geena sv sai an a aD2Su4 ose La Led oor i) wade cca channel and present the digital position to the common data outputs. The AD2S44 also features independent reference inputs. Conse- quently, different reference frequencies may be used for each channel. MODELS AVAILABLE The AD2S44 series is available in three accuracy grades: AD2S44UM 14-Bits 4.0 Arc Mins -55C to +125C (+2.6 Arc Mins 28C to +85C ) +4.0 Are Mins 55C to +125C *5,2 Arc Mins 55C to +125C 14-Bits 14-Bits AD2S44TM AD2S44SM Each grade has options available which will interface to synchros and resolvers of standard voltage and frequency. All components are 100% tested at 55C, +25C, and + 125C. Devices processed to high reliability screening standards (Suffix B) receive further levels of testing and screening to ensure high levels of reliability. Full ordering information is given on the back page of this data sheet. One Technology Way; P. 0. Box 9106; Norwood, MA 02062-9106 U.S.A. Tel: 617/929-4700 Twn: 210/394-6577 Telex: 324491 Cables: ANALOG NORWOODMASS neAD2S44SPECIFICATIONS , ical @ +25C unless specified otherwise) 2844 Units Parameter AD Commeats PERFORMANCE Accuracy) AD2S44UM 4.0 (max) Arc Min 55C to +125C +2.6 (max) Arc Min -28C to +85C AD2S4TM 4.0 (max) Are Min 8C to +125C AD28445M +5.2 (max) Arc Min -55C to + 125C Tracking Rate 20 revis Resolution 14 Bits Outpur Coding Parallel (1 LSB = 1.3 arc mins) Natural Binary Repeatability 1 LSB Signal/Reference Frequency 400-2600 Hz Bandwidth 100 Hz SIGNAL INPUTS Signal Voltage 2, 11.8, 26, 90 V rms See Ordering Information Input Impedance 50 V Signal 200 ko Resistive, Tolerance +2% 26 V Signal 58 kQ 11.8 V Signal 26 kn 2 V Signal 44 kn Common Mode Rejection 74 (min) dB Common Mode Range 90 V Signal 2250 Vide 26 V Signal +120 Vide 11.8 V Signal +60 V de 2 V Signal +12 V de REFERENCE INPUTS Reference Voltage 2, 11.8, 26, 115 Vrms See Ordering Information Input Impedance HS V Reference 270 kn Resistive, Tolerance +5% 26 V Reference 270 kn 11.8 V Reference 25 kh 2 V Reference 25 kn Common Mode Range LIS V Reference +210 Vde 26 V Reference +210 Vide 11.8 V Reference +35 Vde 2 V Reference 235 Vide ACCELERATION CONSTANT 62000 sec? -2- REV.A1 perp AD2S44 Parameter AD2S4 Units Comments STEP RESPONSE Large Step' 63 (typ), 75 (max) ms 17% to 1 LSB of Exror Small Step 25 (typ), 30 (max) ms 2 to 1 LSB of Error POWER LINES +V, = + 15V! $5 (cyp), 100 (max) mA Quiescent Condition ~V, = ~-15V' 55 (typ), 70 (max) mA Quiescent Condition Power Dissipation 2.1 (typ), 2.6 (max) W Quiescent Condition DIGITAL INPUTS Va 0.7 (max) Vide 1, = SpA Vue 2.0 (min) V de In: = SpA AB OV. 0.7 (max) Vide ly = 1.2mA DIGITAL OUTPUTS (DBI-DB14) Vou! 0.4 (max) Vde In = 1L2mA Von 2.4 (mia) Vide lon = WyA Tristate Leakage Current + pA Drive Capebility 3 (max) LSTTL Loads DATA TRANSFER See Figure 3 Time to Data Stable (After Negative Edge of OF or Change of Level of A/B) 640 (max) ns ls Time to Dats in High Impedance State (After Positive Edge of OF) 200 (max) ns te Time for Repetitive Strobing of Selected Channel 200 (min) ns lp BUILT-IN TEST OUTPUT (BIT) Sense Active Low Low = Error Condition Vo. 0.4 (max) Vde lo, = 3.2 mA on 2.4 (min) Vde lon = 160 uA Drive Capability 8 (max) LSTTL Loads Error Condition Set 55 (max) LSB Error Condition Cleared 45 (min) LSB DIMENSIONS 1,75 x 1.08 x 0.228 inch See Package Information 44.45 X 28.07 x $.72) | mm WEIGHT 0.65 (max) oz 18.2 (max) grams NOTES Specified over temperacure range, 55C to +125C, and for: (8) + 10% signal and reference amplitude variation; (b) + 10% signal and reference harmonic distortion; (c)} 25% power supply variation; (d) = 10% variation in reference frequency. Bold face type indicates parameters which are 100% tested at nominal values of power supplies, input signal voltages and operating frequency. All other para- mavers are guaranteed by design, not tested. Specifications subject to change without notice. REV.AAD2S44 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION +Vgt0GND ... 22. c eee e eee iveeeeeee +17.25 V de VstoGND 2c. pcre cece ee ee eer nee -17,25 V de Any Logic Input to GND (max) .....--.----- +6.0 V de ome} (0) @)p Any Logic Input to GND (min) ........6-00- 0.4 V de EO) @ om Maximum Junction Temperature ...........--- +150C pevo| (2) | os $1, $2, $3, S4 (Line to Line)' @ HOV Option 6... cece e cece eee ees 600 V de men om WV Option oo. eee ec cece reece eee ee +160 V de vata! (@) @ jon 11.8 V Option ..........00% bee eeneene + 80 V de ven! () @ | pez ZV Option... 0.2. eee eee 2h4 Vide pers! @) 3) | oe: mse $1, $2, $3, $4 1 GND 810 eae Ol GOV Option 2.0... . eee eee eee +600 V de atl @) iNet to Beam Gy y 26V Option ......-..0005: cece eres +160 V de * LBV Option... 2. cece cece eee ee eens +80 V de a! @ | oo ZV Option... see cece cree eee eens +14 V de row! @ @ |nom Ruz t0 Rig Pan Al @ jn 26V, MSV Options .......... cee eee 600 V de unl @luw 2V, 11.8 V Options ..........---.---65- +50 V de as @ Runt, Ryo to GND se 26 V, 115 V Options... 0.6... cece eee ees +600 V de aaj @ |om 2V, U8 V Options .....-. 0. eee eee +50 V de sical G6) @ |sw Storage Temperature Range ........5-5 ~65C to + 150C Operating Temperature Range ........-. 5C to +125C NOTE On synchro input options, line-to-linc voltagc refers to the 2-S1, $1-$3 and S3-S2 differential voltages. On resolver input options line-to-line levels FUNCTIONAL DESCRIPTION refer to the $1-S3 and S2-S4 voltages. Pin Mnemonic Description AN ; ; ne limits beyond which 1-7 |DB8-DB14 | Parallel Ourput Data Bits . Maximum ratings are ts damage to the iemeot 26-32 |DBI-DB7 [Parallel Output Data Bits 2. Correct polarity voltages must be maintained on the +V; and 8 OF Output Enable Input Vg pins. 9 AB Channel! A or B Select Input 3. The +15 V power supply must never go below GND. 10 BIT Built-In Test Error Output Table |. Bit Weight Table i Rzo (A) Input Pin for Channel A Reference Low 12 Ray (A) Input Pin for Channel A Reference High Bit Number Weight (Degrees) 13-16 |S4S1(A) Channel A Input Signal 1 (MSB) 180.0000 17-20 |S$1-S4 (B) Channe] B Input Signal 3 ood 2) [Ray B) Input Pin for Channel B Reference High 4 22.5000 2 Rio (B) Input Pin for Channel B Reference Low 5 11.2500 23 GND Power Supply Ground (Note: This Pin Is 6 5.6250 Electrically Connected to the Case.) ; ioe 24 -Vs Negative Power Supply 9 0.7031 25 +V5 Positive Power Supply 10 0.3516 11 0.1758 12 0.0879 13 0.0439 14 (LSB for 2844) 0.0220 ESD SENSITIVITY The AD2$44 features input protection circuitry consisting of large distributed diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low cnergy pulses (Charged Device Model). WARNING! ae a nT Proper ESD precautions are strongly recommended to avoid functional damage or perfor- mance degradation. For further information on ESD precautions, refer to Analog Devices ESD Prevention Manual.AD2S44 Mie (A) REFERENCE Pola CONDITIONER j +V, Stial Vs] WiGH RESOLVER! [-*] SPEED ERROR PHASE urroown| @ GND 621A) SENGITIVE ba) INTEGRATOR SYNCHRO sicOs INTER $3 (a) Oe} conpiniorsen | _] MULTIOLIER DETECTOR sou iA v, yy ) ET aft TRGTATE rd euNLT OUTPUT AD2S44 ww Test LATCHES DETECTION Q oss rt t 8 pss stim $2 (0) G-o RESOLVER! 7 ecu muase 231m O-elconomonsal_.! sevens SENSITIVE ol WVTEGRATOR verpown 18) WUATIOLIER DETECTOR Ae _ &,, CONDITIONER Figure 1. Functional Block Diagram of AD2S44 PRINCIPLES OF OPERATION The AD2S44 series operate on a tracking principle. The output digital word continually tracks the position of the resolver/syn- chro shaft without the need for external convert commands and status wait loops. As the transducer moves through a position equivalent to the least significant bit weighting, the output digi- tal word is updated. A functional diagram of the AD2S44 is shown in Figure 1. Each channel is identical in operation, sharing power supply and outpat pins. Both channels operate continuously and indepen- dently of each other-the digital output from either channel is available after switching the channel select and output enable inputs. If the device is a synchro-to-digital converter, the 3-wire synchro output will be connected to $1, $2 and S3 oo the unit, and a solid-state Scon-T input conditioner will convert these signals into resolver format, i.e., V,=K Eo an wt nn 0 V,=K Ey sin wr cos 6 Where @ is the angle of the synchro shaft, E, sin wr is the refer- ence signal and K is the transformation ratio of the input signal conditioner. If the unit is a resolver-to digital converter, the 4-wire resolver ourput will be connected directly to $1, $2, $3 and $4 on the unit. To understand the conversion process, assume that the current word state of the up-down counter is >. V, is multiplied by cot and V, is multiplied by sind to give: K Eg sin wot sin 8 cos K Ey sin wr cos 8 sin $. These signals are subtracted by the error amplifier to give: REV. A K Ey sin wr (sin 8 cos - cos 8 sin d) or K Eg sin wr sin (6-4). A phase sensitive detector, integrator and voltage controlled oscillator (VCO) form a closed loop system which secks to null sin (6-45). When this is accomplished, the word state of the up-down counter, @, equals, to within the rated accuracy of the converter, the synchro-resolver shaft angle, 4. CONNECTING THE CONVERTER The power supply voltages connected to -V, and + Vs pins should be +15 V and must not be reversed. It is suggested that a parallel combination of a 100 nF (ceramic) and a 6.8 pF (tantalum) capacitor be placed from each of the supply pins to GND. The pin marked GND is connected electrically to the case and should be taken to the zero volt potential in the system. The digital output is taken from Pins 26-32 and Pins 1-7. Pin 26 is the MSB, Pin 7 the LSB. The reference connections are made to REF HI and REF LO. In the case of a synchro, the signals are connected to S1, $2 and $3 according to the following convention: Es.ss = Exzro-rnr sm wt sin 0 Ess.sz = Erco-rny in wt sin (0-120") E525) = Erco-rni st wt sin (6-240). For a resolver, the signals are connected to $1, $2, S3 and S4 according to the following convention: E5153 = Exzo-rar sit wt sin @ Esse = Epto-rni sm wt cos 8 5.AD2S44 CHANNEL SELECT (AB) AJB is the channel select input. A logic high selects channel A and a logic low sclocts channel B. Data becomes valid 640 ns after A/B is toggled. Timing information is shown in Figure 2. OUTPUT ENABLE (OB) OE is the output enable input; the signal is active low. When set to a logic high, DB1 to DB14 are in the hugh impedance state, When OE is set to logic low, DB) to DB14 represent the angle of the transducer shaft (see bit weights in Table 1) to within the stated accuracy of the converter. Deta becomes valid 640 ns after the OE is switched. Timing information is shown in Figure 2 and detailed in the Dats Transfer section of SPECIFICATIONS. e\ te a>| alt i l } EEN AE "NOTE CONVERTER DATA OLITPUT IS INHIBITED FROM UPDATES DURING DATA VALID. a. Repetitive Reading of One Channel *NOTE CONVERTER DATA OUTPUT IS INHIBITED FROM UPOATES DURING CHANNEL VALID b. Alternate Reading of Each Channel Figura 2. AD2S44 Timing Diagrams BUILT-IN TEST (BIT) BIT is the built-in rest error output. This provides an over velocity or fault indication signal for the channel selected via AJB. The error voltage of each channel is continuously moni- tored; and when the error exceeds +50 bits for the currently error greater than approximately 1 angular degree exists and that the data is therefore invalid. The BIT signal has a built-in hystcrisis, i.c., the error required to set BIT is greater than that required for it to be cleared. BIT is set when the error exceeds $5 LSBs and is cleared when the error goes below 45 LSBs. This mode of operation guarantees that BIT will not flicker when the error threshold is crossed. BIT is valid for the selected channel approximately 50 ns after the change in state of A/B. In most instances, the error condi- tion which sets BIT must persist for at least 1 period of the ref- erence signal prior to BIT responding to the condition. Conditions which cause the BIT output to show a fault are: 1. Power-Up Transient Response BIT will return to a logic high state after the AD2S44 posi- tion output synchronizes with the angle input to within 1 degree. Normally, BIT will be low at power-up for a period less than or equal to the large signal step response set- ding time of the AD2S44 after the + V, supplies have stabi- lized to within 5% of their final values. 2. Step Input > | Degrec BIT will return to a logic high state after the selected channel of the AD2S44 has settled to with 1 degree of the input angle resulting from an instantaneous step. 3. Excessive Velocity BIT will be driven to a logic iow if the maximum tracking rate of the AD2S44 is exceeded (20 RPS typical). 4. Signal Failure BIT may be driven to a logic Jow state if all signal voltages to the selected channel are lost. 5. Convertes/System Failure Any failure which causes the AD2544 to fail to track the input synchro/resalver angles will drive BIT to a logic low. This may include, but is not necessarily limited to, accelera- tion conditions, poor supply voltage regulation or excessive noise on the signal connections. SCALING FOR NONSTANDARD SIGNALS A feature of these converters is that the signal and reference inputs can be resistively scaled to accommodate nonstandard input signal and reference voltages which are outside the nomi- nal + 10% limits of the converter. Using this technique, it is possible to use a standard converter with a personality card in systems where a wide range of input and reference voltages are encountered. NOTE: The accuracy of the converter will be affected by the matching accuracies of resistors used for external scaling. For resolver format options, it is critical that the value of the resis- tors on the $1-S3 signal input pair be precisely matched to the $4-S2 input pair. For synchro options, the three resistors an $1, $2, $3 must be matched. In general, a 0.1% mismatch between resistor values will contribute an additional 1.7 arc minutes of error to the conversion. In addition, imbalances in resistor val- ues can greatly reduce the common mode rejection ratio of the signal inputs. . To calculate the values of the external scaling resistors add 2.222 kM extra per volt of signal in series with $i, S2, $3 and $4 (no resistor required on S4 for synchro options), and 3 kQ in extra per volt of reference in series with Ryo and Rug. DYNAMIC PERFORMANCE The transfer function of the converter is given below. 8 K 1+8Ty Your se [|] rst, Figure 3. Transfer Function of AD2S44 REV. AAD2S44 Qpen loop transfer function: four | Ke 1+ 8% On 2 1+ sT, Closed loop transfcr function: Bour _ 1 +57; 8m T+ sT, + PK, +s TYK, where K, = 62000 sec~ T, = 0.0061 sec T, = 0.001 sec. The gain and phase diagrams are shown in Figures 4 and 5. + +3 +12 WS w 200 PREQUENCY - iz Figure 8. AD2S44 Gain Plot wv 100 PRBQUENCY ~ He Figure 5. AD2S44 Phase Plot REV. A ACCELERATION ERROR A wacking converter employing a Type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant K, of the converter. Input Acceleration Error in Output Angle The numerator and denominator must have consistant angular units. For example, if K, is in sec?, then the input acceleration may be specified in degrees/sec? and the error in output angle in degrees. Alternatively, the angular unit of measure may be in radians, minutes of arc, LSBs, etc. K, does not define maximum acceleration, only the error duc to acceleration. The maximum acceleration for which the AD2S44 will not lose track is on the order of 5 x K, = 310,000 /sec or about 800 revalutionsec. K, can be used to predict the output position error due to input acceleration. For eaxample, for an acceleration of 50 revolutions/ sec with K, = 62000, Ky Input Acceleration [LSB/sec*] K, [sec"} 50 [rev/sec?] - 2! [LSByrev] , - = 13. ; 2000 (e077) 13.2 LSBs Error in LSBs - RELIABILITY The reliability of these products is very high duc to the exten- sive use of custom chip circuits that decrease the active compo- nent count. Calculations of the MTBF figure under various environmental conditions are available on request. Figure 6 shows the MTBF in years vs. case temperature for Naval Sheltered conditions calculated in accordance with MIL- HDBE-217E. 3 Lo] 6 108 Zs TEMPERATURE C Figure 6. 2544 MTBF vs. TemperatureORDERING INFORMATION When ordering, the converter part numbers should be suffixed by a twa lerter code defining the accuracy grade, and a rwo digit numeric code defining the signal/reference vokage and frequency. All the standard options and their option codes are shown below. For nonstandard configurations, pleese contact Analog Devices. For example, the correct part number for a component to oper- ate with 90 V signal, 115 V reference syachro farmst inputs and yield a +5.2 arc minmee accuracy over the 53C wo + 125 tem- perature range would be AD2S44$M12. The seme part, pro- cessed to high reliability mandards would carry the designator apie ID Y z &5 Le esureie 7 = 6, Signed 2V, Refeence | 2 V Rewer Z = 1, Signal 11.8, Raheeence HV Spachre 2 2, Signed OV, Refeomse 115 V Synchro 2 = 5, Sigel 11.8, Reference 11.8 V Renter 2 = 4, Signal WV, Dalewrce = 26 V Resolver Bene Part Z = &, Signa, 111 V, Refwance 26 VReeiver Y 3 400 His we 2.6 hits Reference Prequancy X = VU 55C we +129C Opsracing Termporetuce Ranga 4.8 Ane Min Accuracy 22.6 Acc Min Accusecy (~25C +89C) X = -T - SHC wo +125C Cperating Temperntare Range Many other products concerned with the conversion of synchro/ resolver dats are manufactured by Analog Devices, some of which are listed below. The SDC/RDC 1740/41/42 are hybrid synchro/resolver to digital The SDC/RDC1767468 are identical wo the SDC/RDC1740 series bur with the additional festures of analog velocity output and de error output. The 08C1758 ie a hybrid sine/cosine power cscillstor which can provide a maximum power output of 1.5 watts. The device opersees over 2 frequency renge of 1 kHz to 10 kHz. The DRC174S and DIRC1746 are 14- and 16-bit natural binary The accuracies sveileble arc +2 and +4 arc minutes, and the outputs can sapply 2.VA a 7 V rms. Transformers are available to convert the output 10 synchro or resolver format at high voli- age leveis. The AD2S6S/66 are similar to the DRC1745/46 but do not include the power curput stage. These devices arc available in accuracy gtades to | arc minute. The 2890 series are recnolithic ICs performing resolver to digital conversion with accuracies up to +2 arc minutes and 16-bit resolution. 2 4.6 Ace Min Accumny X = " ~$9C w +129C Opensting Tempersarc Range = 5.2 Are Mim Acverecy OUTLINE DIMENSION Dimeasions shown in inches and (mm). - REV. A 1361-24-10/89 PRINTED IN U.S.A.