Dual/Quad Low Power, High Speed
JFET Operational Amplifiers
OP282/OP482
Rev. F
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
High slew rate: 9 V/µs
Wide bandwidth: 4 MHz
Low supply current: 250 µA/amplifier max
Low offset voltage: 3 mV max
Low bias current: 100 pA max
Fast settling time
Common-mode range includes V+
Unity-gain stable
APPLICATIONS
Active filters
Fast amplifiers
Integrators
Supply current monitoring
GENERAL DESCRIPTION
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. The slew
rate is typically 9 V/µs with a supply current under 250 µA per
amplifier. These unity-gain stable amplifiers have a typical gain
bandwidth of 4 MHz.
The JFET input stage of the OP282/OP482 ensures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 V of each supply, low
power consumption, and high slew rate, the OP282/OP482
are ideal for battery-powered systems or power restricted
applications. An input common-mode range that includes the
positive supply makes the OP282/OP482 an excellent choice for
high-side signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. The OP282 is available in the standard
8-lead narrow SOIC and MSOP packages. The OP482 is
available in PDIP and narrow SOIC packages.
PIN CONNECTIONS
1
2
3
45
6
7
8
O
UT
A
–IN A
+IN A
V– OP-482
V+
OUT B
–IN B
+IN B
OP282
00301-001
Figure 1. 8-Lead Narrow-Body SOIC (S-Suffix) [R-8]
00301-002
OUT
A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
OP282
TOP VIEW
(Not to Scale)
Figure 2. 8-Lead MSOP [RM-8]
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP482
– + +–
– + +–
00301-003
Figure 3. 14-Lead PDIP (P-Suffix) [N-14]
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP482
00301-004
Figure 4. 14-Lead Narrow-Body SOIC (S-Suffix) [R-14]
OP282/OP482
Rev. F | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Typical Performance Characteristics ............................................. 5
Applications Information .............................................................. 12
High-Side Signal Conditioning ................................................ 12
Phase Inversion........................................................................... 12
Active Filters ............................................................................... 12
Programmable State-Variable Filter......................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 16
REVISION HISTORY
10/04—Data Sheet Changed from Rev. E to Rev. F
Deleted 8-Lead PDIP .........................................................Universal
Added 8-Lead MSOP .........................................................Universal
Changes to Format and Layout.........................................Universal
Changes to Features.......................................................................... 1
Changes to Pin Configurations....................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 4
Changes to Table 3............................................................................ 4
Added Figure 5 through Figure 20; Renumbered
Successive Figures............................................................................. 5
Updated Figure 21 and Figure 22 ................................................... 7
Updated Figure 23 and Figure 27 ................................................... 8
Updated Figure 29 ............................................................................ 9
Updated Figure 35 and Figure 36 ................................................. 10
Updated Figure 43 .......................................................................... 11
Changes to Applications Information.......................................... 12
Changes to Figure 44...................................................................... 12
Deleted OP282/OP482 Spice Macro Model Section.................... 9
Deleted Figure 4................................................................................ 9
Deleted OP282 Spice Marco Model ............................................. 10
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide .......................................................... 14
10/02—Data Sheet Changed from Rev. D to Rev. E
Edits to 8-Lead Epoxy DIP (P-Suffix) Pin......................................1
Edits to Ordering Guide ...................................................................3
Edits to Outline Dimensions......................................................... 11
9/02—Data Sheet Changed from Rev. C to Rev. D
Edits to 14-Lead SOIC (S-Suffix) Pin .............................................1
Replaced 8-Lead SOIC (S-Suffix)................................................. 11
4/02—Data Sheet changed from Rev. B to Rev. C
Wafer Test Limits Deleted ................................................................2
Edits to Absolute Maximum Ratings ..............................................3
Dice Characteristics Deleted............................................................3
Edits to Ordering Guide ...................................................................3
Edits to Figure 1.................................................................................7
Edits to Figure 3.................................................................................8
20-Position Chip Carrier (RC Suffix) Deleted ........................... 11
OP282/OP482
Rev. F | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VS = ±15.0 V, TA = 25°C, unless otherwise noted; applies to both A and G grade.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS OP282 0.2 3 mV
OP282, −40°C ≤ TA ≤ +85°C 4.5 mV
V
OS OP482 0.2 4 mV
OP482, −40°C ≤ TA ≤ +85°C 6 mV
Input Bias Current IBVCM = 0 V 3 100 pA
V
CM = 0 V1 500 pA
Input Offset Current IOS VCM = 0 V 1 50 pA
V
CM = 0 V1 250 pA
Input Voltage Range −11 +15 V
Common-Mode Rejection Ratio CMRR −11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C 70 90 dB
Large Signal Voltage Gain AVO RL = 10 kΩ 20 V/mV
R
L = 10 kΩ, −40°C ≤ TA ≤ +85°C 15 V/mV
Offset Voltage Drift ∆VOS/∆T 10 µV/°C
Bias Current Drift ∆IB/∆T 8 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ +13.5 +13.9 V
Output Voltage Low VOL RL = 10 kΩ −13.9 −13.5 V
Short-Circuit Limit ISC Source 3 10 mA
Sink −12 −8 mA
Open-Loop Output Impedance ZOUT f = 1 MHz 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V, −40°C ≤ TA ≤ +85°C 25 316 µV/V
Supply Current/Amplifier ISY VO = 0 V, −40°C ≤ TA ≤ 85°C 210 250 µA
Supply Voltage Range VS ±4.5 ±18 V
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 7 9 V/µs
Full-Power Bandwidth BWP1% distortion 125 kHz
Settling Time tSTo 0.01% 1.6 µs
Gain Bandwidth Product GBP 4 MHz
Phase Margin ØO 55 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 1.3 µV p-p
Voltage Noise Density enf = 1 kHz 36 nV/√Hz
Current Noise Density in 0.01
pA/√Hz
1 The input bias and offset currents are characterized at TA = TJ = 85°C. Bias and offset currents are guaranteed but not tested at −40°C.
OP282/OP482
Rev. F | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters Ratings
Supply Voltage ±18 V
Input Voltage ±18 V
Differential Input Voltage136 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range
P-Suffix (N), S-Suffix (R), RM Packages −65°C to +150°C
Operating Temperature Range
OP282G, OP282A, OP482G −40°C to +85°C
Junction Temperature Range
P-Suffix (N), S-Suffix (R), RM Packages −65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C
1 For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Package Type θJA1θJC Unit
8-Lead MSOP [RM] 206 44 °C/W
8-Lead SOIC (S-Suffix) [R] 157 56 °C/W
14-Lead PDIP (P-Suffix) [N] 83 39 °C/W
14-Lead SOIC (S-Suffix) [R] 104 36 °C/W
1 θJA is specified for the worst-case conditions; i.e., θJA is specified for device in
socket for CERDIP, PDIP; θJA is specified for device soldered in circuit board
for SOIC or MSOP package.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
OP282/OP482
Rev. F | Page 5 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
1k
–40
–20
60
80
10k 1M 10M
00301-005
100k
20
40
0
V
S
= ±15V
T
A
= 25°C
PHASE (Degree)
–45
135
45
90
0
–90
180
Figure 5. OP282 Open-Loop Gain and Phase vs. Frequency
TEMPERATURE (°C)
OPEN-LOOP GAIN (V/mV)
–75
0
5
35
45
–25 100 125
00301-006
25
15
25
10
V
S
= ±15V
R
L
= 10kΩ
20
30
40
75500–50
Figure 6. OP282 Open-Loop Gain vs. Temperature
LOAD CAPACITANCE (pF)
OVERSHOOT (%)
0
0
10
70
80
200 400 500
00301-007
30
50
20
40
60
300100
V
S
= ±15V
R
L
= 2kΩ
V
IN
= 100mV p-p
A
VCL
= 1
T
A
= 25°C
+OS
–OS
Figure 7. OP282 Small Signal Overshoot vs. Load Capacitance
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
1k
–30
–20
60
70
10k 1M 10M
00301-008
100k
20
40
0
V
S
= ±15V
T
A
= 25°C
–10
50
10
30
A
VCL
= 1
00
A
VCL
= 1
0
A
VCL
= 1
Figure 8. OP282 Closed-Loop Gain vs. Frequency
TEMPERATURE (°C)
SLEW RATE (V/µs)
–75
0
5
30
–25 100 125
00301-009
25
15
25
10
V
S
= ±15V
R
L
= 10kΩ
C
L
= 50pF
20
75500–50
–SR
+SR
Figure 9. OP282 Slew Rate vs. Temperature
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
–75
0.1
1000
–25 100 125
00301-010
25
1
100
10
75500–50
V
S
= ±15V
V
CM
= 0V
Figure 10. OP282 Input Bias Current vs. Temperature
OP282/OP482
Rev. F | Page 6 of 16
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/ Hz)
10
1
1000
100 10k
00301-011
1k
100
10
V
S
= ±15V
T
A
= 25°C
Figure 11. OP282 Voltage Noise Density vs. Frequency
COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (pA)
–15
0.1
1000
10 15
00301-012
–5
1
100
10
50–10
V
S
= ±15V
T
A
= 25°C
Figure 12. OP282 Input Bias Current vs. Common-Mode Voltage
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
µ
A)
0
450
480
±20
00301-013
±10
455
465
460
±15±5
T
A
= 25°C
470
475
Figure 13. OP282 Supply Current vs. Supply Voltage
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE SWING (V)
0
–20
20
±20
00301-014
±10
–15
–5
–10
±15±5
T
A
= 25°C
R
L
= 10kΩ
0
15 V
OH
V
OL
5
10
Figure 14. OP282 Output Voltage Swing vs. Supply Voltage
FREQUENCY (Hz)
OUTPUT IMPEDANCE (
Ω
)
1k
0.1
100
1000
10k 1M100
00301-015
100k
1
10
V
S
= ±15V
T
A
= 25°C
A
VCL
= 100
A
VCL
= 10
A
VCL
= 1
Figure 15. OP282 Closed-Loop Output Impedance vs. Frequency
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
–50
450
480
125
00301-016
25
455
750
460
475
465
470
–25 50 100
Figure 16. OP282 Supply Current vs. Temperature
OP282/OP482
Rev. F | Page 7 of 16
LOAD RESISTANCE (
Ω
)
ABSOLUTE OUTPUT VOLTAGE (V)
0
6
16
1k 10k100
00301-017
2
4
V
S
= ±15V
T
A
= 25°C
V
OL
V
OH
12
8
10
14
Figure 17. OP282 Absolute Output Voltage vs. Load Resistance
FREQUENCY (Hz)
PSRR (dB)
1k
–60
40
140
10k 1M100
00301-018
100k
0
20
–40
–20
60
100
120
80
–PSRR
+PSRR
V
S
= ±15V
T
A
= 25°C
Figure 18. OP282 PSRR vs. Frequency
TEMPERATURE (°C)
SHORT-CIRCUIT CURRENT (mA)
–50
0
14
125
00301-019
25
4
750
6
12
8
10
–25 50 100
2
V
S
= ±15V
SINK
SOURCE
Figure 19. OP282 Short-Circuit Current vs. Temperature
FREQUENCY (Hz)
MAXIMUM OUTPUT SWING (V p-p)
100
0
5
25
30
1k 100k 1M
00301-020
10k
15
20
10
V
S
= ±15V
T
A
= 25°C
R
L
= 10kΩ
A
VCL
= 1
Figure 20. OP282 Maximum Output Swing vs. Frequency
FREQUENCY (Hz)
CMRR (dB)
1k
–60
40
140
10k 1M100
00301-021
100k
0
20
–40
–20
60
100
120
80
V
S
= ±15V
T
A
= 25°C
Figure 21. OP282 CMRR vs. Frequency
V
OS
(µV)
UNITS
–2000
0
200
00301-022
–400
80
–1200
120
160
40
400 1200 2000
V
S
= ±15V
T
A
= 25°C
300 × OP282
(600 OP AMPS)
0
Figure 22. OP282 VOS Distribution SOIC Package
OP282/OP482
Rev. F | Page 8 of 16
TCV
OS
(µV/°C)
UNITS
0
0
400
00301-023
20
80
16
120
160
40
28 32 3624
200
280
320
360
240
4128
V
S
= ±15V
300 × OP282
(600 OP AMPS)
Figure 23. OP282 TCVOS Distribution SOIC Package
FREQUENCY (Hz)
1k 10k 100k 1M 100M10M
80
OPEN-LOOP GAIN (dB)
PHASE (Degrees)
90
135
0
45
180
60
40
20
0
V
S
= ±15V
T
A
= 25°C
00301-024
Figure 24. OP482 Open-Loop Gain, Phase vs. Frequency
12510050 75250–75 –50 –25
TEMPERATURE (°C)
OPEN-LOOP GAIN (V/mV)
30
35
25
20
15
10
5
V
S
= ±15V
R
L
= 10kΩ
00301-025
0
Figure 25. OP482 Open-Loop Gain (V/mV)
OVERSHOOT (%)
5000 300
100 200 400
70
10
0
60
50
40
30
20
LOAD CAPACITANCE (pF)
A
VCL
= 1
NEGATIVE EDGE
V
S
= ±15V
R
L
= 2k
Ω
V
IN
= 100mV p-p
00301-026
A
VCL
= 1
POSITIVE EDGE
Figure 26. OP482 Small Signal Overshoot vs. Load Capacitance
FREQUENCY (Hz)
1k 10k 100k 1M 100M10M
60
CLOSED-LOOP GAIN (dB)
40
20
10
0
50
30
–10
–20
00301-027
A
VCL
= 10
A
VCL
= 1
A
VCL
= 100
V
S
= ±15V
T
A
= 25°C
Figure 27. OP482 Closed-Loop Gain vs. Frequency
–SR
–75
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
5
10
25
15
20
+SR
SLEW RATE (V/µs)
00301-028
VS = ±15V
RL = 10kΩ
CL = 50pF
0
Figure 28. OP482 Slew Rate vs. Temperature
OP282/OP482
Rev. F | Page 9 of 16
1000
1.0
0.1
100
10
INPUT BIAS CURRENT (pA)
TEMPERATURE (°C)
125–25–50 250 75 100
00301-029
V
S
= ±15V
V
CM
= 0V
050
Figure 29. OP482 Input Bias Current vs. Temperature
60
55
PHASE MARGIN (Degrees)
–75 TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
V
S
= ±15V
R
L
= 10kΩ
GBW
GAIN BANDWIDTH PRODUCT (MHz)
50
45
40
5.0
4.5
4.0
3.5
3.0
00301-030
Figure 30. OP482 Phase Margin and Gain Bandwidth Product vs. Temperature
FREQUENCY (Hz)
10 100 1k 10k
80
0
20
10
40
30
50
60
70
VOLTA
GE NOISE DENSITY (nV/ Hz)
00301-031
V
S
= ±15V
T
A
= 25°C
Figure 31. OP482 Voltage Noise Density vs. Frequency
COMMON-MODE VOLTAGE (V)
15–15 0 5 10–10 –5
INPUT BIAS CURRENT (pA)
100
1
1000
0.1
10
00301-032
V
S
= ±15V
T
A
= 25°C
Figure 32. OP482 Input Bias Current vs. Common-Mode Voltage
SUPPLY VOLTAGE (V)
±150±±10±5
RELATIVE SUPPLY CURRENT (ISY)
1.10
0.90
1.15
0.85
1.00
1.05
0.95
20
00301-033
TA = 25°C
Figure 33. OP482 Relative Supply Current vs. Supply Voltage
SUPPLY VOLTAGE (V) ±150±10±5 ±20
–5
OUTPUT VOLTAGE SWING (V)
0
15
5
10
20
–10
–20
–15
00301-034
R
L
= 10k
Ω
T
A
= 25°C
Figure 34. OP482 Output Voltage Swing vs. Supply Voltage
OP282/OP482
Rev. F | Page 10 of 16
IMPEDANCE (
Ω
)
600
0
300
100
200
500
400
1M1k100 100k10k
FREQUENCY (Hz)
A
VCL
= 10
00301-035
V
S
= ±15V
T
A
= 25°C
A
VCL
= 1
A
VCL
= 100
Figure 35. OP482 Closed-Loop Output Impedance vs. Frequency
RELATIVE SUPPLY CURRENT (ISY)
TEMPERATURE (°C)
1.20
0.80
0.90
0.85
1.00
0.95
1.05
1.10
1.15
–50–75 1251007550250–25
00301-036
V
S
= ±15V
Figure 36. OP482 Relative Supply Current vs. Temperature
LOAD RESISTANCE (Ω)
10k1k100
ABSOLUTE OUTPUT VOLTAGE (V)
16
0
2
8
6
10
12
14
4
POSITIVE
SWING
NEGATIVE
SWING
00301-037
V
S
= ±15V
T
A
= 25°C
Figure 37. OP482 Maximum Output Voltage vs. Load Resistance
PSRR (dB)
100
20
40
0
20
80
60
1M1k100 100k10k
FREQUENCY (Hz)
+PSRR
00301-038
V
S
= ±15V
∆
V = 100mV
T
A
= 25°C
–PSRR
Figure 38. OP482 Power Supply Rejection Ratio (PSRR) vs. Frequency
SHORT-CIRCUIT CURRENT (mA)
20
15
5
10
SINK
SOURCE
TEMPERATURE (°C)
75–75 0 25 50–50 –25 100 125
00301-039
V
S
= ±15V
0
Figure 39. OP482 Short-Circuit Current vs. Temperature
MAXIMUM OUTPUT SWING (V)
30
0
15
5
10
25
20
100K10K
1K 1M
FREQUENCY (Hz)
00301-040
V
S
= ±15V
T
A
= 25°C
A
VCL
= 1
R
L
= 10kΩ
Figure 40. OP482 Maximum Output Swing vs. Frequency
OP282/OP482
Rev. F | Page 11 of 16
CMRR (dB)
100
–20
40
0
20
80
60
1M1k100 100k10k
FREQUENCY (Hz)
00301-041
V
S
= ±15V
T
A
= 25°C
V
CM
= 100mV
Figure 41. OP482 Common-Mode Rejection Ratio (CMRR) vs. Frequency
UNITS
0
600
700
300
100
200
400
500
2000
–1600–2000 160012008004000
–400–800–1200 V
OS
(µV)
00301-045
V
S
= ±15V
T
A
= 25°C
300 × OP482
(1200 OP AMPS)
Figure 42. OP482 VOS Distribution P Package
UNITS
320
0
80
40
160
120
200
240
280
0
00301-043
32282412 201684
TCV
OS
(µV/°C)
Figure 43. OP482 TCVOS Distribution P Package
OP282/OP482
Rev. F | Page 12 of 16
APPLICATIONS INFORMATION
The OP282 and OP482 are dual and quad JFET op amps that
are optimized for high speed at low power. This combination
makes these amplifiers excellent choices for battery-powered or
low power applications that require above average performance.
Applications benefiting from this performance combination
include telecommunications, geophysical exploration, portable
medical equipment, and navigational instrumentation.
HIGH-SIDE SIGNAL CONDITIONING
There are many applications that require the sensing of signals
near the positive rail. OP282s and OP482s were tested and are
guaranteed over a common-mode range (−11 V ≤ VCM ≤ +15 V)
that includes the positive supply.
One application where this is commonly used is in the sensing
of power supply currents. This enables it to be used in current
sensing applications, such as the partial circuit shown in Figure 44.
In this circuit, the voltage drop across a low value resistor, such
as the 0.1 Ω shown here, is amplified and compared to 7.5 V.
The output can then be used for current limiting.
15V
100k
Ω
500k
Ω
0.1
Ω
500k
Ω
100k
Ω
R
L
1/2
OP282
00301-046
Figure 44. High-Side Signal Conditioning
PHASE INVERSION
Most JFET-input amplifiers invert the phase of the input signal
if either input exceeds the input common-mode range. For the
OP282/OP482, negative signals in excess of approximately 14 V
cause phase inversion. The cause of this effect is saturation of
the input stage leading to the forward-biasing of a drain-gate
diode. A simple fix for this in noninverting applications is to
place a resistor in series with the noninverting input. This limits
the amount of current through the forward-biased diode and
prevents the shutting down of the output stage. For the
OP282/OP482, a value of 200 kΩ has been found to work;
however, this adds a significant amount of noise.
–15 –10 –5 5 10 15
15
10
5
0
–
5
–
10
–
15
V
IN
V
OUT
00301-047
0
Figure 45. OP282 Phase Reversal
ACTIVE FILTERS
The wide bandwidth and high slew rates of the OP282/OP482
make either an excellent choice for many filter applications.
There are many active filter configurations, but the four most
popular configurations are Butterworth, Elliptical, Bessel, and
Chebyshev. Each type has a response that is optimized for a
given characteristic as shown in Table 4.
Table 4.
Type Selectivity Overshoot Phase Amplitude (Pass Band) Amplitude (Stop Band)
Butterworth Moderate Good Maximum Flat
Chebyshev Good Moderate Nonlinear Equal Ripple
Elliptical Best Poor Equal Ripple Equal Ripple
Bessel (Thompson) Poor Best Linear
OP282/OP482
Rev. F | Page 13 of 16
PROGRAMMABLE STATE-VARIABLE FILTER
The circuit shown in Figure 46 can be used to accurately
program the Q, the cutoff frequency fC, and gain of a 2-pole
state variable filter. OP482s have been used in this design
because of their high bandwidths, low power, and low noise.
This circuit takes only three packages to build because of the
quad configuration of the op amps and DACs.
The DACs shown are used in the voltage mode; therefore, many
values are dependent on the accuracy of the DAC only and not
on the absolute values of the DAC’s resistive ladders. This makes
this circuit unusually accurate for a programmable filter.
Adjusting DAC 1 changes the signal amplitude across R1;
therefore, the DAC attenuation times R1 determines the amount
of signal current that charges the integrating capacitor, C1. This
cutoff frequency can now be expressed as
⎟
⎠
⎞
⎜
⎝
⎛
=2562π
1D1
R1C1
fc
where D1 is the digital code for the DAC.
The gain of this circuit is set by adjusting D3. The gain equation is
⎟
⎠
⎞
⎜
⎝
⎛
=256
D3
R5
R4
Gain
DAC 2 is used to set the Q of the circuit. Adjusting this DAC
controls the amount of feedback from the band-pass node to
the input summing node. Note that the digital value of the
DAC is in the numerator; therefore, zero code is not a valid
operating point.
⎟
⎠
⎞
⎜
⎝
⎛
=D2R3
R2
Q256
R5
2kΩ
1/4
OP482
V
IN
1/4
DAC8408
HIGH PASS
C1
1000pF
R4
2kΩ
R6
2kΩ
R7
2kΩ
1/4
OP482
R1
2kΩ
1/4
OP482
1/4
DAC8408
1/4
OP482
R1
2kΩ
1/4
OP482
1/4
DAC8408
1/4
OP482
C1
1000pF
LOW
PASS
1/4
OP482
1/4
OP482
1/4
DAC8408
BAND PASS
R2
2kΩ
R3
2kΩ
00301-048
Figure 46.
OP282/OP482
Rev. F | Page 14 of 16
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)× 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 47. 8-Lead Standard Small Outline Package [SOIC]
Narrow-Body S-Suffix (R-8)
Dimensions shown in millimeters and (inches)
0.80
0.60
0.40
8°
0°
4
8
1
5
4.90
BSC
PIN 1 0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 48. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
OP282/OP482
Rev. F | Page 15 of 16
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COPLANARIT
Y
0.10
14 8
7
16.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
8°
0°
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AB
× 45°
Figure 49. 14-Lead Standard Small Outline Package [SOIC]
Narrow-Body S-Suffix (R-14)
Dimensions shown in millimeters and (inches)
14
17
8
0.685 (17.40)
0.665 (16.89)
0.645 (16.38) 0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.100 (2.54)
BSC
SEATING
PLANE
0.180 (4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
MIN 0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095-AB
Figure 50. 14-Lead Plastic Dual-in-Line Package [PDIP]
P-Suffix (N-14)
Dimension shown in inches and (millimeters)
OP282/OP482
Rev. F | Page 16 of 16
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
OP282ARMZ-R21−40°C to +85°C 8-Lead MSOP RM-8 A0B
OP282ARMZ-REEL1 −40°C to +85°C 8-Lead MSOP RM-8 A0B
OP282GS −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GS-REEL −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GS-REEL7 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GSZ1 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GSZ-REEL1 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GSZ-REEL71 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP482GP −40°C to +85°C 14-Lead PDIP P-Suffix (N-14)
OP482GS −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GS-REEL −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GS-REEL7 −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GSZ1 −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GSZ-REEL1 −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GSZ-REEL71 −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
1 Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00301–0–10/04(F)
