74AHCU04BQ,115 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74AHCU04 is high-speed Si-gate CMOS devices and is pin compatible with low

power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard No. 7A.

The 74AHCU04 is a general purpose hex inverter. Each of the six inverters is a single

stage.

2. Features

■Low power dissipation

■Balanced propagation delays

■Inputs accepts voltages higher than VCC

■ESD protection:

◆HBM JESD22-A114E: exceeds 2000 V

◆MM JESD22-A115-A: exceeds 200 V

◆CDM JESD22-C101C: exceeds 1000 V

■Multiple package options

■Speciﬁed from −40 °C to +125 °C

3. Ordering information

74AHCU04

Hex inverter

Rev. 03 — 14 November 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature

range Name Description Version

74AHCU04D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

74AHCU04PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

74AHCU04BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin

quad ﬂat package; no leads; 14 terminals;

body 2.5 ×3×0.85 mm

SOT762-1

Product data sheet Rev. 03 — 14 November 2007 2 of 14

NXP Semiconductors 74AHCU04

Hex inverter

4. Functional diagram

5. Pinning information

5.1 Pin description

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one inverter)

mna342

1A 1Y

2A 2Y

3A 3Y

4A 4Y

5A 5Y

11 10

6A 6Y

13 12

112

mna343

314

516

918

11 110

13 112

mna045

(1) The die substrate is attached to the exposed die pad

using conductive die attach material. It can not be

used as a supply pin or input.

Fig 4. Pin conﬁguration SO14 and TSSOP14 Fig 5. Pin conﬁguration DHVQFN14

1A VCC

1Y 6A

2A 6Y

2Y 5A

3A 5Y

3Y 4A

GND 4Y

001aac441

001aac442

GND(1)

Transparent top view

3Y 4A

3A 5Y

2Y 5A

2A 6Y

1Y 6A

GND

VCC

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

Table 2. Pin description

Symbol Pin Description

1A 1 data input

1Y 2 data output

2A 3 data input

2Y 4 data output

Product data sheet Rev. 03 — 14 November 2007 3 of 14

NXP Semiconductors 74AHCU04

Hex inverter

6. Functional description

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.

For TSSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.

For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.

3A 5 data input

3Y 6 data output

GND 7 ground (0 V)

4Y 8 data output

4A 9 data input

5Y 10 data output

5A 11 data input

6Y 12 data output

6A 13 data input

VCC 14 supply voltage

Table 2. Pin description

…continued

Symbol Pin Description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level

Input Output

nA nY

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7.0 V

IIK input clamping current VI<−0.5 V −20 - mA

VIinput voltage [1] −0.5 +7.0 V

IOK output clamping current VO < −0.5 V or VO>V

CC + 0.5 V - ±20 mA

IOoutput current −0.5 V < VO < VCC + 0.5 V - ±25 mA

ICC supply current - 75 mA

IGND ground current −75 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb = −40 °C to +125 °C[2] - 500 mW

Product data sheet Rev. 03 — 14 November 2007 4 of 14

NXP Semiconductors 74AHCU04

Hex inverter

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 2.0 5.0 5.5 V

VIinput voltage 0 - 5.5 V

VOoutput voltage 0 - VCC V

Tamb ambient temperature −40 +25 +125 °C

∆t/∆V input transition rise and fall rate VCC = 3.3 V ± 0.3 V - - 100 ns/V

VCC = 5.0 V ± 0.5 V - - 20 ns/V

Table 6. Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

VIH HIGH-level

input voltage VCC = 2.0 V 1.7 - - 1.7 - 1.7 - V

VCC = 3.0 V 2.4 - - 2.4 - 2.4 - V

VCC = 5.5 V 4.4 - - 4.4 - 4.4 - V

VIL LOW-level

input voltage VCC = 2.0 V - - 0.3 - 0.3 - 0.3 V

VCC = 3.0 V - - 0.6 - 0.6 - 0.6 V

VCC = 5.5 V - - 1.1 - 1.1 - 1.1 V

VOH HIGH-level

output voltage VI= VIH or VIL

IO=−50 µA; VCC = 2.0 V 1.8 2.0 - 1.8 - 1.8 - V

IO=−50 µA; VCC = 3.0 V 2.7 3.0 - 2.7 - 2.7 - V

IO=−50 µA; VCC = 4.5 V 4.0 4.5 - 4.0 - 4.0 - V

IO=−4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.4 - V

IO=−8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.7 - V

VOL LOW-level

output voltage VI= VIH or VIL

IO= 50 µA; VCC = 2.0 V - 0 0.2 - 0.2 - 0.2 V

IO= 50 µA; VCC = 3.0 V - 0 0.3 - 0.3 - 0.3 V

IO= 50 µA; VCC = 4.5 V - 0 0.5 - 0.5 - 0.5 V

IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V

IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V

IIinput leakage

current VI= 5.5 Vor GND;

VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 µA

ICC supply current VI=V

CC or GND; IO=0A;

VCC = 5.5 V - - 2.0 - 20 - 40 µA

CIinput

capacitance - 3 10 - 10 - 10 pF

Product data sheet Rev. 03 — 14 November 2007 5 of 14

NXP Semiconductors 74AHCU04

Hex inverter

10. Dynamic characteristics

[1] tpd is the same as tPLH and tPHL.

[2] Typical values are measured at VCC = 3.3 V.

[3] Typical values are measured at VCC = 5.0 V.

[4] CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL×VCC2×fo) = sum of outputs.

11. Waveforms

Table 7. Dynamic characteristics

GND = 0 V; For test circuit see Figure 7.

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

tpd propagation

delay nA to nY; see Figure 6 [1]

VCC = 3.0 V to 3.6 V [2]

CL= 15 pF - 3.0 7.1 1.0 8.5 1.0 9.0 ns

CL= 50 pF - 3.4 10.6 1.0 12.0 1.0 13.5 ns

VCC = 4.5 V to 5.5 V [3]

CL= 15 pF - 2.4 5.5 1.0 6.5 1.0 7.0 ns

CL= 50 pF - 3.5 7.0 1.0 8.0 1.0 9.0 ns

CPD power

dissipation

capacitance

CL= 50 pF; fi= 1 MHz;

VI= GND to VCC

[4] - 9.1 - - - - - pF

VM = 0.5 ×VCC; VI = GND to VCC. Test data is given in Table 7.

Deﬁnitions for test circuit:

CL = Load capacitance including jig and probe

capacitance.

RT = Termination resistance should be equal to

output impedance Zo of the pulse generator.

Fig 6. The input (nA) to output (nY) propagation delay

times Fig 7. Load circuit for switching times

mna344

tPHL tPLH

nA input

nY output

GND

VOH

VOL

VCC

VIVO

mna034

DUT

50 pF

PULSE

GENERATOR

Product data sheet Rev. 03 — 14 November 2007 6 of 14

NXP Semiconductors 74AHCU04

Hex inverter

12. Typical transfer characteristics

Tamb = 25 °C. Tamb = 25 °C.

Fig 8. VCC = 2.0 V; IO= 0 A Fig 9. VCC = 3.0 V; IO=0 A

0 0.5 1 2

1.5

0.5

700

500

100

−100

300

mna353

1.5

ICC

(µA)

ICC

(V)

Vi (V) 01 3

−2

mna352

ICC

(mA)

ICC

(V) VO

Vi (V)

Tamb = 25 °C.

fi = 1 kHz at VO is constant

Fig 10. VCC = 5.5 V; IO= 0 A Fig 11. Test set-up for measuring forward

transconductance

02 6

−10

mna351

ICC

(mA)

ICC

(V)

Vi (V)

mna050

VCC

Rbias = 560 kΩ

input

0.47 µF100 µF

output

GND

(f = 1 kHz)

gfs ∆Io

∆Vi

---------

Product data sheet Rev. 03 — 14 November 2007 7 of 14

NXP Semiconductors 74AHCU04

Hex inverter

13. Application information

Some applications are:

•Linear ampliﬁer (see Figure 13)

•In crystal oscillator design (see Figure 14)

Remark: All values given are typical unless otherwise speciﬁed.

Tamb = 25 °C.

Fig 12. Typical forward transconductance as a function of the supply voltage

0246

mna355

VCC (V)

gfs

(mA/V)

Maximum Vo(p-p) =V

CC −1.5 V centered at

0.5 ×VCC.

Gol = open loop gain

Gv= voltage gain

R1 ≥3kΩ,R2≤1MΩ

ZL>10kΩ; Gol = 12 (typical)

Typical unity gain bandwidth product is 5 MHz.

C1 = 47 pF (typical)

C2 = 33 pF (typical)

R1 = 1 MΩ to 10 MΩ (typical

R2 optimum value depends on the frequency and

required stability against changes in VCC or average

minimum ICC (ICC is typically 5 mA at VCC = 5 V and

fi= 10 MHz).

Fig 13. Used as a linear ampliﬁer Fig 14. Crystal oscillator conﬁguration

U04

VCC

mna052

1 µF

mna053

U04

out

C1 C2

GvGol

1R1

-------1G

+()+

---------------------------------------

–=

Product data sheet Rev. 03 — 14 November 2007 8 of 14

NXP Semiconductors 74AHCU04

Hex inverter

Table 8. External components for resonator (f < 1 MHz)

All values given are typical and must be used as an initial set-up.

Frequency R1 R2 C1 C2

10 kHz to 15.9 kHz 22 MΩ220 kΩ56 pF 20 pF

16 kHz to 24.9 kHz 22 MΩ220 kΩ56 pF 10 pF

25 kHz to 54.9 kHz 22 MΩ100 kΩ56 pF 10 pF

55 kHz to 129.9 kHz 22 MΩ100 kΩ47 pF 5 pF

130 kHz to 199.9 kHz 22 MΩ47 kΩ47 pF 5 pF

200 kHz to 349.9 kHz 10 MΩ47 kΩ47 pF 5 pF

350 kHz to 600 kHz 10 MΩ47 kΩ47 pF 5 pF

Table 9. Optimum value for R2

Frequency R2 Optimum for

3 kHz 2.0 kΩminimum required ICC

8.0 kΩminimum inﬂuence due to change in VCC

6 kHz 1.0 kΩminimum required ICC

4.7 kΩminimum inﬂuence by VCC

10 kHz 0.5 kΩminimum required ICC

2.0 kΩminimum inﬂuence by VCC

14 kHz 0.5 kΩminimum required ICC

1.0 kΩminimum inﬂuence by VCC

>14 kHz - replace R2 by C3 with a typical value of 35 pF

Product data sheet Rev. 03 — 14 November 2007 9 of 14

NXP Semiconductors 74AHCU04

Hex inverter

14. Package outline

Fig 15. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 03 — 14 November 2007 10 of 14

NXP Semiconductors 74AHCU04

Hex inverter

Fig 16. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 03 — 14 November 2007 11 of 14

NXP Semiconductors 74AHCU04

Hex inverter

Fig 17. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 03 — 14 November 2007 12 of 14

NXP Semiconductors 74AHCU04

Hex inverter

15. Abbreviations

16. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

LSTTL Low-power Schottky Transistor-Transistor Logic

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

CDM Charge Device Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74AHCU04_3 20071114 Product data sheet - 74AHCU04_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 3: DHVQFN14 package added.

•Section 8: derating values added for DHVQFN14 package.

•Section 14: outline drawing added for DHVQFN14 package.

74AHCU04_2 19990927 Product speciﬁcation - 74AHCU04_1

74AHCU04_1 19990226 Product speciﬁcation - -

Product data sheet Rev. 03 — 14 November 2007 13 of 14

NXP Semiconductors 74AHCU04

Hex inverter

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

18. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74AHCU04
Hex inverter
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 November 2007
Document identifier: 74AHCU04_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
Contents
General description. . . . . . . . . . . . . . . . . . . . . .  1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
Ordering information. . . . . . . . . . . . . . . . . . . . .  1
Functional diagram . . . . . . . . . . . . . . . . . . . . . .  2
Pinning information. . . . . . . . . . . . . . . . . . . . . .  2
1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  2
Functional description  . . . . . . . . . . . . . . . . . . .  3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . .  3
Recommended operating conditions. . . . . . . .  4
Static characteristics. . . . . . . . . . . . . . . . . . . . .  4
Dynamic characteristics . . . . . . . . . . . . . . . . . .  5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
Typical transfer characteristics . . . . . . . . . . . .  6
Application information. . . . . . . . . . . . . . . . . . .  7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .  9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . .  12
Revision history. . . . . . . . . . . . . . . . . . . . . . . .  12
Legal information. . . . . . . . . . . . . . . . . . . . . . .  13
1 Data sheet status . . . . . . . . . . . . . . . . . . . . . .  13
2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .  13
4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .  13
Contact information. . . . . . . . . . . . . . . . . . . . .  13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14