CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
FullFlex™ Synchronous SDR
Dual Port SRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-06082 Rev. *M Revised October 28, 2011
FullFlex™ Synchronous SDR Dual Port SRAM
Features
■True dual port memory enables simultaneous access the
shared array from each port
■Synchronous pipel ined operation with single d ata rate (SDR)
operation on each port
❐SDR interface at 200 MHz
❐Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)
■Selectable pipelined or flow-through mode
■1.5 V or 1.8 V core power supply
■Commercial and Industrial te mperature
■IEEE 1149.1 JTAG boundary scan
■Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36
and × 18) packages
■FullFlex72 family
❐36-Mbit: 512 K × 72 (CYD36S72V18)
❐18-Mbit: 256 K × 72 (CYD18S72V18)
❐9-Mbit: 128 K × 72 (CYD09S72V18)
■FullFlex36 family
❐36-Mbit: 1 M × 36 (CYD36S36V18)
❐18-Mbit: 512 K × 36 (CYD18S36V18)
❐9-Mbit: 256 K × 36 (CYD09S36V18)
❐2-Mbit: 64 K × 36 (CYD02S36V18)
■FullFlex18 family
❐36-Mbit: 2 M × 18 (CYD36S18V18)
❐18-Mbit: 1 M × 18 (CYD18S18V18)
❐9-Mbit: 512 K × 18 (CYD09S18V18)
■Built in deterministic access control to manage address
collisions
❐Deterministic flag output upon collision detection
❐Collision detection on back-to-back clock cycles
❐First busy address readback
■Advanced features for improved high speed data transfer and
flexibility
❐Variable impedance matching (VIM)
❐Echo clocks
❐Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V),
1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port
❐Burst counters for sequential memory access
❐Mailbox with interrupt flags for message passing
❐Dual chip enables for easy depth expansion
Functional Description
The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit,
18-Mbit, and 36-Mbit synchronous, true dual port static RAMs
that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports
are provided, enabling simultaneous access to the array.
Simultaneous access to a location trigge rs deterministic access
control. For FullFlex72 these ports operate independently with
72-bit bus widths and each port i s independently configured for
two pipelined stages. Each port is also configured to operate in
pipelined or flow through mode.
The advanced features include the following:
■Built in deterministic access control to manage address
collisions during simultaneous access to the same memory
location
■Variable impedance matching (VIM) to improve data
transmission by matchin g the output driver impedance to the
line impedance
■Echo clocks to improve data transfer
To reduce the static power consumption, chip enables power
down the internal circuitry. The number of latency cycles before
a change in CE0 or CE1 enables or disables the databus
matches the number of cycles of read latency selected for the
device. For a valid write or read to occur, activate both chip
enable inputs on a port.
Each port contains an optional burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally.
Additional device feature s include a mask register and a mirror
register to control counter increments and wrap around. The
counter interrupt (CNTINT) flags notify the host that the counter
reaches maximum count value on the next clock cycle. The host
reads the burst counter internal address, mask register address,
and busy address on the address lines. The host also loads the
counter with the address stored in the mirror register by using the
retransmit functionality. Mailbox interrupt flags are used for
message passing, and JTAG boundary scan and asynchronous
Master Reset (MRST) are also available. The Logic Block
Diagram on page 2 shows these features.
The FullFlex72 is offered in a 484-ball plastic BGA package. The
FullFlex36 and FullFlex18 are available in 256-ball fine pitch
BGA package except the 36-Mbit devices which are offered in
484-ball plastic BGA package.
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 2 of 53
Logic Block Diagram
The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows: [1, 2, 3]
FTSEL
L
PORTSTD[1:0]
L
DQ[71:0]
L
BE
[7:0]L
R/
WL
FTSEL
R
PORTSTD[1:0]
R
DQ [71:0]
R
BE
[7:0]R
CE
0
R
CE1
R
OE
R
R/
WR
A [20:0]
L
CNT/
MSKL
ADS
L
CNTEN
L
CNTRST
L
RET
L
CNTINT
L
C
L
WRP
L
A [20:0]
R
CNT/
MSKR
ADS
R
CNTEN
R
CNTRST
R
RET
R
CNTINT
R
C
R
WRP
R
CONFIG Block CONFIG Block
IO
Control IO
Control
Address &
Counter Logic Address &
Counter Logic
INT
L
TRST
TMS
TDI
TDO
TCK
JTAG
MRST
READY
R
LowSPD
R
READY
L
LowSPD
L
RESET
LOGIC
INT
R
BUSY
L
BUSY
R
Mailboxes
Collision Detection Logic
Dual Port Array
CQEN
L
CQEN
R
CE
0
L
CE1
L
OE
L
CQ1
R
CQ1
R
CQ0
R
CQ0
R
CQ0
L
CQ0
L
CQ1
L
CQ1
L
ZQ0
R
ZQ1
R
ZQ0
L
ZQ1
L
Notes
1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
CYD09S18V18 devices have 19 address bits. The CYD18S 72V18 and CY D09S36V18 d evices have 18 address bits. The CYD09S72V 18 devi ce has 1 7 address bit s.
The CYD02S36V18 has 16 address bits.
2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.
3. The FullFlex72 family of devices has eigh t byte enables. The FullFlex36 family of de vices has four byte enables. The FullFlex18 family of devices has two byte enable s.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 3 of 53
Contents
Selection Guide ................................................................9
Pin Definitions ..................................................................9
Selectable IO Standard ............. ... .............................11
Clocking .....................................................................11
Selectable Pipelined or Flow through Mode ..............11
DLL ............................................................................11
Echo Clocking ........................ ...................................11
Deterministic Access Control ....................................11
Variable Impedance Matching .......................................12
Address Counter and Mask Register Operations ......13
Counter Load Operation ............................................13
Mask Load Operation ................................................13
Counter Readback Operation ....................................13
Mask Readback Operation ........................................13
Counter Reset Operation ..........................................13
Mask Reset Operation ...............................................13
Increment Operation ..................................................15
Hold Operation ..........................................................1 5
Retransmit ................................................................. 15
Counter Interrupt .......................................................15
Counting by Two ...... .................................................15
Counting by Four .................... ...................................15
Mailbox Interrupts ......................................................15
Master Reset .............................................................1 8
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................18
Maximum Ratings ...........................................................19
Operating Range ....................... ......................................19
Power Supply Requirements .........................................19
Electrical Characteristics ...............................................19
Electrical Characteristics ...............................................21
Electrical Characteristics ...............................................24
Capacitance ....................................................................24
Thermal Resistance ........................................................24
AC Test Load and Waveforms .......................................25
Switching Characteristics ..............................................26
Switching Waveforms ....................................................29
Ordering Information ......................................................43
512 K × 72 (36-Mbit) 1.8 V/1.5 V Synchronous
CYD36S72V18 Dual Port SRAM ......................................43
256 K × 72 (18-Mbit) 1.8 V/1.5 V Synchronous
CYD18S72V18 Dual Port SRAM ......................................43
128 K × 72 (9-Mbit) 1.8 V/1.5 V Synchronous
CYD09S72V18 Dual Port SRAM ......................................43
1024 K × 36 (36- Mbit) 1.8 V/1.5 V Synchronous
CYD36S36V18 Dual Port SRAM ......................................43
512 K × 36 (18-Mbit) 1.8 V/1.5 V Synchronous
CYD18S36V18 Dual Port SRAM ......................................43
256 K × 36 (9-Mbit) 1.8 V/1.5 V Synchronous
CYD09S36V18 Dual Port SRAM ......................................44
64 K × 36 (2-Mbit) 1.8 V or 1.5 V Synchronous
CYD02S36V18 Dual Port SRAM ......................................44
2048 K × 18 (36- Mbit) 1.8 V/1.5 V Synchronous
CYD36S18V18 Dual Port SRAM ......................................45
1024 K × 18 (18-Mbit) 1.8 V/1.5 V Synchronous
CYD18S18V18 Dual Port SRAM ......................................45
512 K × 18 (9-Mbit) 1.8 V/1.5 V Synchronous
CYD09S18V18 Dual Port SRAM ......................................45
Ordering Code Definitions .........................................45
Package Diagrams ..........................................................46
Acronyms ........................................................................ 49
Document Conventions ............. .. ..................................49
Units of Measure ..................... ... ...............................49
Document History Page ........................ ... ......................50
Sales, Solutions, and Legal Information ......................53
Worldwide Sales and Design Support .......................53
Products ....................................................................53
PSoC Solutions ..................... ....................................53
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Document Number: 38-06082 Rev. *M Page 4 of 53
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Figure 1. FullFlex72 SDR 484-ball BGA Pinout (Top View)
12 3 4 5 6 7 8 9 10111213 14 1516171819202122
ADNU DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R DNU
BDQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R
CDQ65L DQ64L VSS VSS DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R VSS VSS DQ64R DQ65R
DDQ67L DQ66L VSS VSS VSS CQ1L CQ1L VSS LOWSPDL PORTSTD0L ZQ0L[4] BUSYL CNTINTL PORTSTD1L DNU CQ1R CQ1R VSS VSS VSS DQ66R DQ67R
EDQ69L DQ68L VDDIOL VSS VSS VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VTTL VTTL VTTL VDDIOR VDDIOR VDDIOR VDDIOR DNU VSS VDDIOR DQ68R DQ69R
FDQ71L DQ70L CE1L CE0L VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VCORE VCORE VCORE VCORE VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR CE0R CE1R DQ70R DQ71R
GA0L A1L RETL BE4L VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR BE4R RETR A1R A0R
HA2L A3L WRPL BE5L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE5R WRPR A3R A2R
JA4L A5L READYL BE6L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE6R READYR A5R A4R
KA6L A7L ZQ1L[4, 5] BE7L VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VDDIOR BE7R ZQ1R[4, 5] A7R A6R
LA8L A9L CL OEL VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL OER CR A9R A8R
MA10L A11L VSS BE3L VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL BE3R VSS A11R A10R
NA12L A13L ADSL BE2L VDDIOL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL BE2R ADSR A13R A12R
PA14L A15L CNT/MSKL BE1L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE1R CNT/MSKR A15R A14R
RA16L[8] A17L[7] CNTENL BE0L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE0R CNTENR A17R[7] A16R[8]
TA18L[6] DNU CNTRSTL INTL VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR INTR CNTRSTR DNU A18R[6]
UDQ35L DQ34L R/WL CQENL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VCORE VCORE VCORE VCORE VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR CQENR R/WR DQ34R DQ35R
VDQ33L DQ32L FTSELL VDDIOL DNU VDDIOL VDDIOL VDDIOL VDDIOL VTTL VTTL VTTL VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR TRST VDDIOR FTSELR DQ32R DQ33R
WDQ31L DQ30L VSS MRST VSS CQ0L CQ0L DNU PORTSTD1R CNTINTR BUSYR ZQ0R[4] PORTSTD0R LOWSPDR VSS CQ0R CQ0R VSS TDI TDO DQ30R DQ31R
YDQ29L DQ28L VSS VSS DQ20L DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11R DQ14R DQ17R DQ20R TMS TCK DQ28R DQ29R
AA DQ27L DQ26L DQ24L DQ22L DQ19L DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10R DQ13R DQ16R DQ19R DQ22R DQ24R DQ26R DQ27R
AB DNU DQ25L DQ23L DQ21L DQ18L DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12R DQ15R DQ18R DQ21R DQ23R DQ25R DNU
Notes
4. Leave this ball unconnected to disable VIM.
5. This ball is applicable only for 36-Mbit and DNU for 18-Mbit and lower densities.
6. Leave this Ball unconnected for CYD18S72V18 and CYD09S72V18.
7. Leave this Ball unconnected for CYD09S72V18.
8. Leave this Ball unconnected for CYD04S72V18.
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Document Number: 38-06082 Rev. *M Page 5 of 53
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Figure 2. FullFlex36 SDR 484-ball BGA Pinout (Top View)[9]
12345678 9 10111213141516171819202122
ADNU DNU DNU DNU DNU DQ33L DQ30L DQ27L DQ24L DQ21L DQ18L DQ18R DQ21R DQ24R DQ27R DQ30R DQ33R DNU DNU DNU DNU DNU
BDNU DNU DNU DNU DNU DQ34L DQ31L DQ28L DQ25L DQ22L DQ19L DQ19R DQ22R DQ25R DQ28R DQ31R DQ34R DNU DNU DNU DNU DNU
CDNU DNU VSS VSS DNU DQ35L DQ32L DQ29L DQ26L DQ23L DQ20L DQ20R DQ23R DQ26R DQ29R DQ32R DQ35R DNU VSS VSS DNU DNU
DDNU DNU VSS VSS VSS CQ1L CQ1L VSS LOWSPDL PORTSTD0L ZQ0L[10] BUSYL CNTINTL PORTSTD1L DNU CQ1R CQ1R VSS VSS VSS DNU DNU
EDNU DNU VDDIOL VSS VSS VDDIOL VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL DNU VSS VDDIOR DNU DNU
FDNU DNU CE1L CE0L VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CE0R CE1R DNU DNU
GA0L A1L RETL BE2L VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR BE2R RETR A1R A0R
HA2L A3L WRPL BE3L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE3R WRPR A3R A2R
JA4L A5L READYL DNU VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR DNU READYR A5R A4R
KA6L A7L ZQ1L[10] DNU VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VDDIOR DNU ZQ1R[10] A7R A6R
LA8L A9L CL OEL VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL OER CR A9R A8R
MA10L A11L VSS DNU VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL DNU VSS A11R A10R
NA12L A13L ADSL DNU VDDIOL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL DNU ADSR A13R A12R
PA14L A15L CNT/MSKL BE1L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE1R CNT/MSKR A15R A14R
RA16L A17L CNTENL BE0L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE0R CNTENR A17R A16R
TA18L A19L CNTRSTL INTL VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR INTR CNTRSTR A19R A18R
UDNU DNU R/WL CQENL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CQENR R/WR DNU DNU
VDNU DNU FTSELL VDDIOL DNU VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOR TRST VDDIOR FTSELR DNU DNU
WDNU DNU VSS MRST VSS CQ0L CQ0L DNU PORTSTD1R CNTINTR BUSYR ZQ0R[10] PORTSTD0R LOWSPDR VSS CQ0R CQ0R VSS TDI TDO DNU DNU
YDNU DNU VSS VSS DNU DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11R DQ14R DQ17R DNU TMS TCK DNU DNU
AA DNU DNU DNU DNU DNU DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10R DQ13R DQ16R DNU DNU DNU DNU DNU
AB DNU DNU DNU DNU DNU DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12R DQ15R DNU DNU DNU DNU DNU
Notes
9. Use this pinout only for device CYD36S36V18 of the FullFlex36 family.
10.Leave this ball unconnected to disable VIM.
[+] Feedback
Document Number: 38-06082 Rev. *M Page 6 of 53
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Figure 3. FullFlex18 SDR 484-ball BGA Pinout (To p View)[11]
123 45678 9 10111213141516171819202122
ADNU DNU DNU DNU DNU DNU DNU DNU DQ15L DQ12L DQ9L DQ9R DQ12R DQ15R DNU DNU DNU DNU DNU DNU DNU DNU
BDNU DNU DNU DNU DNU DNU DNU DNU DQ16L DQ13L DQ10L DQ10R DQ13R DQ16R DNU DNU DNU DNU DNU DNU DNU DNU
CDNU DNU VSS VSS DNU DNU DNU DNU DQ17L DQ14L DQ11L DQ11R DQ14R DQ17R DNU DNU DNU DNU VSS VSS DNU DNU
DDNU DNU VSS VSS VSS CQ1L CQ1L VSS LOWSPDL PORTSTD0L ZQ0L[12] BUSYL CNTINTL PORTSTD1L DNU CQ1R CQ1R VSS VSS VSS DNU DNU
EDNU DNU VDDIOL VSS VSS VDDIOL VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL DNU VSS VDDIOR DNU DNU
FDNU DNU CE1L CE0L VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CE0R CE1R DNU DNU
GA0L A1L RETL BE1L VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR BE1R RETR A1R A0R
HA2L A3L WRPL DNU VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR DNU WRPR A3R A2R
JA4L A5L READYL DNU VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR DNU READYR A5R A4R
KA6L A7L ZQ1L[12] DNU VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VDDIOR DNU ZQ1R[12] A7R A6R
LA8L A9L CL OEL VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL OER CR A9R A8R
MA10L A11L VSS DNU VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL DNU VSS A11R A10R
NA12L A13L ADSL DNU VDDIOL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL DNU ADSR A13R A12R
PA14L A15L CNT/MSKL DNU VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR DNU CNT/MSKR A15R A14R
RA16L A17L CNTENL BE0L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE0R CNTENR A17R A16R
TA18L A19L CNTRSTL INTL VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR INTR CNTRSTR A19R A18R
UA20L DNU R/WL CQENL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CQENR R/WR DNU A20R
VDNU DNU FTSELL VDDIOL DNU VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOR TRST VDDIOR FTSELR DNU DNU
WDNU DNU VSS MRST VSS CQ0L CQ0L DNU PORTSTD1R CNTINTR BUSYR ZQ0R[12] PORTSTD0R LOWSPDR VSS CQ0R CQ0R VSS TDI TDO DNU DNU
YDNU DNU VSS VSS DNU DNU DNU DNU DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DNU DNU DNU DNU TMS TCK DNU DNU
AA DNU DNU DNU DNU DNU DNU DNU DNU DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DNU DNU DNU DNU DNU DNU DNU DNU
AB DNU DNU DNU DNU DNU DNU DNU DNU DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DNU DNU DNU DNU DNU DNU DNU DNU
Notes
11. Use this pinout only for device CYD36S18V18 of the FullFlex18 family.
12.Leave this ball unconnected to disable VIM.
[+] Feedback
Document Number: 38-06082 Rev. *M Page 7 of 53
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Figure 4. FullFlex36 SDR 256-ball BGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ADQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R
BDQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R
CDQ34L DQ35L RETL INTL CQ1L CQ1L DNU TRST MRST ZQ0R[13] CQ1R CQ1R INTR RETR DQ35R DQ34R
DA0L A1L WRPL VREFL FTSELL LOWSPDL VSS VTTL VTTL VSS LOWSPDR FTSELR VREFR WRPR A1R A0R
EA2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R CE0R A3R A2R
FA4L A5L CNTINTL BE3L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE3R CNTINTR A5R A4R
GA6L A7L BUSYL BE2L ZQ0L[13] VSS VSS VSS VSS VSS VSS VDDIOR BE2R BUSYR A7R A6R
HA8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CR A9R A8R
JA10L A11L VSS PORTSTD1L VCORE VSS VSS VSS VSS VSS VSS VCORE PORTSTD1R VSS A11R A10R
KA12L A13L OEL BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE1R OER A13R A12R
LA14L A15L ADSL BE0L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE0R ADSR A15R A14R
MA16L[16] A17L[15] R/WL CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR R/WR A17R[15] A16R[16]
NA18L[14] DNU CNT/MSKL VREFL PORTSTD0L READYL DNU VTTL VTTL DNU READYR PORTSTD0R VREFR CNT/MSKR DNU A18R[14]
PDQ16L DQ17L CNTENL CNTRSTL CQ0L CQ0L TCK TMS TDO TDI CQ0R CQ0R CNTRSTR CNTENR DQ17R DQ16R
RDQ15L DQ13L DQ11L DQ9L DQ7L DQ5L DQ3L DQ1L DQ1R DQ3R DQ5R DQ7R DQ9R DQ11R DQ13R DQ15R
TDQ14L DQ12L DQ10L DQ8L DQ6L DQ4L DQ2L DQ0L DQ0R DQ2R DQ4R DQ6R DQ8R DQ10R DQ12R DQ14R
Notes
13.Leave this ball unconnected to disable VIM.
14.Leave this ball unconnected for CYD09S36V18 and CYD02S36V18 .
15.Leave this ball unconnected for CYD02S36V18.
16.Leave this ball unconnected for CYD02S36V18.
[+] Feedback
Document Number: 38-06082 Rev. *M Page 8 of 53
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Figure 5. FullFlex18 SDR 256-ball BGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ADNU DNU DNU DQ17L DQ16L DQ13L DQ12L DQ9L DQ9R DQ12R DQ13R DQ16R DQ17R DNU DNU DNU
BDNU DNU DNU DNU DQ15L DQ14L DQ11L DQ10L DQ10R DQ11R DQ14R DQ15R DNU DNU DNU DNU
CDNU DNU RETL INTL CQ1L CQ1L DNU TRST MRST ZQ0R[17] CQ1R CQ1R INTR RETR DNU DNU
DA0L A1L WRPL VREFL FTSELL LOWSPDL VSS VTTL VTTL VSS LOWSPDR FTSELR VREFR WRPR A1R A0R
EA2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R CE0R A3R A2R
FA4L A5L CNTINTL DNU VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR DNU CNTINTR A5R A4R
GA6L A7L BUSYL DNU ZQ0L[17] VSS VSS VSS VSS VSS VSS VDDIOR DNU BUSYR A7R A6R
HA8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CR A9R A8R
JA10L A11L VSS PORTSTD1L VCORE VSS VSS VSS VSS VSS VSS VCORE PORTSTD1R VSS A11R A10R
KA12L A13L OEL BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE1R OER A13R A12R
LA14L A15L ADSL BE0L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE0R ADSR A15R A14R
MA16L A17L R/WL CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR R/WR A17R A16R
NA18L[19] A19L[18] CNT/MSKL VREFL PORTSTD0L READYL DNU VTTL VTTL DNU READYR PORTSTD0R VREFR CNT/MSKR A19R[18] A18R[19]
PDNU DNU CNTENL CNTRSTL CQ0L CQ0L TCK TMS TDO TDI CQ0R CQ0R CNTRSTR CNTENR DNU DNU
RDNU DNU DNU DNU DQ6L DQ5L DQ2L DQ1L DQ1R DQ2R DQ5R DQ6R DNU DNU DNU DNU
TDNU DNU DNU DQ8L DQ7L DQ4L DQ3L DQ0L DQ0R DQ3R DQ4R DQ7R DQ8R DNU DNU DNU
Notes
17.Leave this ball unconnected to disable VIM.
18.Leave this ball unconnected for CYD09S18V18.
19.Leave this ball unconnected for CYD04S18V18.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 9 of 53
Selection Guide
Parameter -200 -167 Unit
fMAX[21] 200 167 MHz
Maximum access time (clock to data) 3.3 4.0 ns
Typical operating current ICC 800[20] 700[20] mA
Typical standby current for ISB3 (both ports CMOS level) 210[20] 210[20] mA
Pin Definitions
Left Port Right Port Description
A[20:0]LA[20:0]RAddress in puts.[22]
DQ[71:0]LDQ[71:0]RData bus input and output.[23]
BE[7:0]LBE[7:0]RByte select inputs.[24] Asserting these signals enables read and write operations to the
corresponding bytes of the memory array.
BUSYLBUSYRPort busy output. When there is an address match and both chip enables are a ctive for both
ports, an external BUSY signal is asserted on the fifth clock cycles from when the collision occurs.
CLCRClock si gnal. Maximum clock input rate is fMAX.
CE0LCE0RActive LOW chip enable input.
CE1LCE1RActive HIGH chip enable input.
CQENLCQENREcho clock enable input. Assert HIGH to enable echo clocking on respective port.
CQ0LCQ0REcho clock signal output for DQ[35:0] for FullFlex72 de vices. Echo clock sign al output for
DQ[17:0] for FullFlex36 devi ces . Echo clock signal output for DQ[8:0] for FullFlex18 devices.
CQ0LCQ0RInverted echo clock signal output for DQ[35:0] for FullFlex72 devices. Inverted echo clock
signal output for DQ[17:0] for FullFle x36 devi ces . Inverted echo clock signal output for DQ[8 :0]
for FullFlex18 devices.
CQ1LCQ1REcho clock signal output for DQ[71:36] for FullFlex72 devices. Echo clock signal output for
DQ[35:18 ] fo r FullF lex3 6 de vice s. Echo clock signal output for DQ[17:9] for FullFlex18 devices.
CQ1LCQ1RInverted echo clock signal output for DQ[71:36] for FullFlex72 devices. Inverted echo clock
signal output for DQ[35:18] for FullFlex36 devices. Inverted echo clock signal output for DQ[17:9]
for FullFlex18 devices.
ZQ[1:0]LZQ[1:0]RVIM output impedance matching input.[25] To use, connect a calibrating resistor between ZQ
and ground. The resistor must be five times larger than the intende d line imped ance driven by
the dual port. Assert HIGH or leave DNU to disable VIM.
OELOEROutput enable input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during read operations.
INTLINTRMailbox interrupt flag output. The mailbox permits communications between ports. The upper
two memory locations are used for message passing. INTL is asserted LOW when the right port
writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted
HIGH when it reads the contents of its mailbox.
Notes
20.For 18 Mbit x72 commercial configuration only, refer to Electrical Characteristics on page 19 for complete information.
21.SDR mode with two pipelined stages.
22.The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address
bits. The CYD02S36V18 has 16 address bits.
23.The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFle x18 family of devices has 18 data lines.
24.The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables.
25.The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 10 of 53
LowSPDLLowSPDRPort low speed select input. Assert this pin LOW to disable the DLL. In flow through mode, this
pin needs to be asserted low.
PORTSTD[1:0]L[26] PORTSTD[1:0]R[26] Port clock/Address/Control/Data/Echo clock/I/O standard select input. Assert these pins
LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5 V LVCMOS, and HIGH/HIGH
for 1.8 V LVCMOS, respectively. These pins are driven by VTTL referenced levels.
R/WLR/WRRead/Write enable input. Assert this pin LOW to write to, or HIGH to read from the dual port
memory array.
READYLREADYRPort DLL ready output. This signal is asserted LOW when the DLL and variable impedance
matching circuits complete calibration. This is a wired OR capable output.
CNT/MSKLCNT/MSKRPort counter/Mask select input. Counter control input.
ADSLADSRPort counter address load stro be input. Counter control input.
CNTENLCNTENRPort counter enable input. C ounter control input.
CNTRSTLCNTRSTRPort counter reset input. Counter control input.
CNTINTLCNTINTRPort counter interrupt output. This pin is asserted LOW one cycle before the unmasked portion
of the counter is incremented to all “1s”.
WRPLWRPRPort counter wrap input. When the burst counter reaches the maximum count, on the next
counter increment WRP is set LOW to load the unmasked counter bits to 0. It is set HIGH to load
the counter with the value stor ed in the mirror register.
RETLRETRPort counter retransmit input. Assert this pin LOW to reload the initial address for repeated
access to the same segment of memory.
VREFLVREFRPort external HSTL IO reference input. This pin is left DNU when HSTL is not used.
VDDIOLVDDIORPort data IO power supply.
FTSELLFTSELRPort flow through mode select in put. Assert this pin LOW to select flow through mode. Assert
this pin HIGH to select Pipelined mode.
MRST Master reset input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up. This pin is driven by a VDDIOL referenced signal.
TMS JTAG test mode select input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5 V LVCMOS.
TDI JTAG test data input. Data on the TDI input is shifted serially into selected registers. Operation
for LVTTL or 2.5 V LVCMOS.
TRST JTAG reset input. Operation for LVTTL or 2.5 V LVCMOS.
TCK JTAG test clock input. Operation for LVTTL or 2.5 V LVCMOS.
TDO JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is normally
tri-stated except when captured data is shifted out of the JT AG T AP. Operation for L VTTL or 2.5 V
LVCMOS.
VSS Ground inputs.
VCORE Device core power supply.
VTTL LVTTL power supply.
Pin Definitions (continued)
Left Port Right Port Description
Note
26.PORTSTD[1:0]L and PORTSTD[1:0]R have internal pull-down resistors.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 11 of 53
Selectable IO Standard
The FullFlex device families offer the option to choose one of the
four port standards for the device. Each port independently
selects standards from single ended HSTL class I, single ended
LVTTL, 2.5 V LVCMOS, or 1.8 V LVCMOS. The selection of the
standard is determined by the PORTSTD pins for each port.
These pins must be connected to an LVTTL power suppy. This
determines the input clock, address, control, data, and Echo
clock standard for each port as shown in Table 1.
Clocking
Separate clocks synchronize the operations on each port. Each
port has one clock input C. In th is mode, all the transactions on
the address, control, and data are on the C rising edge. All
transactions on the address, control, data input, output, and byte
enables occur on the C rising edge.
Selectable Pipelined or Flow through Mode
To meet data rate and throughput requirements, the FullFlex
families offer selectable pipelined or flow through mode. Echo
clocks are not supported in flow through mode and the DLL must
be disable d .
Flow through mode is selected by the FTSEL pin. Strapping this
pin HIGH selects pipelined mode. Strapping this pin LOW selects
flow through mode.
DLL
The FullFlex familes of devices have an on-chip DLL. Enabling
the DLL reduces the clock to data valid (tCD) time enabling more
setup time for the receiving device. In flow through mode, the
DLL must be disabled. This is sele ctable by strapping LowSPD
low.
Whenever the operating frequency is altered beyond the Clock
Input Cycle to Cycle Jitter specif ication, reset the DLL, followed
by 1024 clocks before any valid operation.
LowSPD pins are used to reset the DLLs for a single port
independent of all other circuitry. MRST is used to reset all DLLs
on the chip. For more information on DLL lock and reset time,
see Master Reset on page 18.
Echo Clocking
As the speed of data increases, on-board delays caused by
parasitics make it extremely difficult to provide accurate clock
trees. To counter this problem, the FullFlex families i ncorporate
Echo Clocks. Echo Clocks are enabled on a per port basis. The
dual port receives input clocks that are used to clock in the
address and control signals for a read operati on. The dual port
retransmits the input clocks relative to the data output. The
buffered clocks are provided on the CQ1/CQ1 and CQ0/CQ0
outputs. Each port has a pair of Echo clocks. Each clock is
associated with half the data bits. The output clock matches the
corresponding ports IO configuration.
To enable echo clock outputs, tie CQEN HIGH. To disabl e echo
clock outputs, tie CQEN LOW.
Deterministic Access Control
Deterministic Access Control is provided for ease of design. The
circuitry detects when both ports access the same l ocation and
provides an external BUSY flag to the port on which data is
corrupted. The collision detection logic saves the address in
conflict (Busy Address) to a readable register. In the case of
multiple collisions, the first busy address is written to the busy
address register.
If both ports access the same location at the same time and only
one port is doing a write, if tCCS is met, then the data written to
and read from the address is valid data. For example, if the right
port is reading and the left port is writing and the left ports clock
meets tCCS, then the data read from the address by the right port
is the old data. In the same case, if the right ports clock meets
tCCS, then the data read out of the address from the right port is
the new data. In the above case, if tCCS is violated by the either
ports clock with respect to the other port and the right port gets
the external BUSY flag, the data from the right port is corrupted.
Table 3 on page 12 shows the tCCS timing that must be met to
guarantee the data.
Table 4 on p age 12 shows that, in the case of the left port writing
and the right port reading, when an external BUSY flag is
asserted on the right port, th e data read out of the device i s not
guaranteed.
The value in the busy address register is read back to the
address lines. The required input control signals for this function
are shown in Table 7 on page 14. The value in the busy address
register is read out to the address lines tCA after the same
amount of latency as a data read operation. After an initial
address match, the BUSY flag is asserted and the address under
contention is saved in the busy address register . All the following
Table 1. Port Standard Selection
PORTSTD1 PORTSTD0 I/O Standard
VSS VSS LVTTL
VSS VTTL HSTL
VTTL VSS 2.5 V LVCMOS
VTTL VTTL 1.8 V LVCMOS
Table 2. Data Pin Assignment
BE Pin Name Data Pin Name
BE[7] DQ[71:63]
BE[6] DQ[62:54]
BE[5] DQ[53:45]
BE[4] DQ[44:36]
BE[3] DQ[35:27]
BE[2] DQ[26:18]
BE[1] DQ[17:9]
BE[0] DQ[8:0]
Figure 6. SDR Echo Clock Delay
Input Clock
Echo Clock
Data Out
Echo Clock
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 12 of 53
address matches enable to generate the BUSY flag. However,
none of the addresses are saved into the busy address register .
When a busy readback is performed, the address of the first
match that happens at least two clocks cycles after the busy
readback is saved into the busy address register.
Variable Impedance Matching
Each port contains a variable impedance matching circuit to set
the impedance of the IO driver to match the impedance of the
on-board traces. The impedance is set for all outputs except
JTAG and is done by port. To take advantage of the VIM feature,
connect a calibrating resistor (RQ) that is five times the value of
the intended line impeda nce fro m the ZQ [1:0][27] pi n to VSS. The
output impedance is then adjusted to account for drifts in supply
voltage and temperature every 1024 clock cycles. If a port’s clock
is suspended, the VIM circuit retains its last setting until the clock
is restarted. On restart, it then resumes periodic adjustment. In
the case of a significant change in device temperature or supply
voltage, recalibration happens every 1024 clock cycles. A master
reset initializes the VIM circuitry. Table 5 shows the VIM
parameters and Table 6 describes the VIM operation modes.
To disable VIM, connect the ZQ pin to VDDIO of the relative
supply for the IOs before a Master Reset.
Table 3. tCCS Timing for All Operating Modes
Port A—Early Arriving Port Port B—Late Arriving Port tCCS
C Rise to Opposite C Rise Setup Time for Non Corrupt Data Unit
Mode Active Edge Mode Active Edge
SDRCSDR Ct
CYC(min) – 0.5 ns
Table 4. Deterministic Access Control Logic
Lef t Port Right Port Left Clock Right Clock BUSYLBUSYRDescription
Read Read X X H H No collision
Write Read > tCCS 0 H H Read OLD data
0> t
CCS H H Read NEW data
< tCCS 0 H H Read OLD data
H L Data not guaranteed
0< t
CCS H H Read NEW data
H L Data Not guaranteed
Read Write > tCCS 0 H H Read NEW data
0> t
CCS HHRead OLD data
< tCCS 0 H H Read NEW data
L H Data Not guaranteed
0< t
CCS HHRead OLD data
L H Data not guaranteed
Write Write 0 > –tCCS & < tCCS L L Array data corrupted
0> t
CCS L H Array stores right port data
> tCCS 0 H L Array stores left port data
Table 5. Variable Impedance Matching Parameters
Parameter Min Max Unit Tolerance
RQ value 100 275 ±2%
Output impedan ce 20 55 ±15%
Reset time – 1024 Cycles –
Update time – 1024 Cycles –
Table 6. Variable Impedance Matching Operation
RQ Connection Output Configuration
100 –275 to VSS Output driver impedance = RQ/5 ± 15%
at Vout = VDDIO/2
ZQto VDDIO VIM disabled. Rout < 20 at Vout =
VDDIO/2
Note
27.The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 13 of 53
Address Counter and Mask Register Operations [28]
Each port of the FullFlex family contains a prog rammable burst
address counter. The burst counter contains four registers: a
counter register, a mask register, a mirror register, and a busy
address register.
The counter register contains the address used to access the
RAM array. It is changed only by the master reset (MRST),
counter reset, counter load, retransmit, and counter increment
operations.
The mask register value affects the counter increment and
counter reset operations by preventing the corresponding bits of
the counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is only changed by
mask reset, mask load, and MRST. The mask load operation
loads the value of the address bus into the mask register. The
mask register defines the counting range of the counter register .
The mask register is divided into two or three consecutive
regions. Zero or more 0s define the masked region and one or
more 1s define the unmasked portion of the counter register. The
counter register may be divided up to three regi ons. The region
containing the least significant bits must be no more than two 0s.
Bits one and zero may be 10 respectively, masking the least
significant counter bit and causing the counter to increment by
two instead of one. If bits one and zero are 00, the two least
significant bits are masked and the counter increments by four
instead of one. For example, in the case of a 256 K × 72
configuration, a mask register value of 003 FC divides the mask
register into three regions. With bit 0 being the least significant
bit and bit 17 being the most significant bit, the two least
significant bits are masked, the next eight bits are unmasked,
and the remaining bits are masked.
The mirror register reloads a counter register on retransmit
operations (see Retransmit on page 15) and wrap functions (see
Counter Interrupt on page 15 below). The last value loaded into
the counter register is stored in the mirror register. The mirror
register is only changed by master reset (MRST), counter reset,
and counter load.
Table 7 on page 14 summarizes the operations of these registers
and the required input control signals. All signals except MRST
are synchronized to the ports clock.
Counter Load Operation [28]
For both non-burst and burst read or write accesses, the external
address is loaded through counter load operation as shown in
Table 7 on page 14. The address counter and mirror registers are
loaded with the address value presented on the address lines.
This value ranges from 0 to 1FFFFF.
Mask Load Operation [28]
The mask register is loaded with the address value presented on
the address bus. This value ranges from 0 to 1FFFFF though not
all values pe rmit corr ect in crement opera tions. Permitted values
are in the form of 2n–1, 2n–2, or 2n–4. The counter register is only
segmented up to thre e regions. From the most significant bit to
the least significant bit, permitted values have zero or more 0s,
one or more 1s, and the least significant two bits are 11, 10, or
00. Thus 1FFFFE, 07FFFF, and 003FFC are permitted values
but 02FFFF, 003FFA, and 07FFE4 are not.
Counter Readback Operation
The internal value of the counter register is read out on the
address lines. The address is valid tCA after the selected number
of latency cycles configured by FTSEL. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 7 on page 16 shows a block diagram of this
logic.
Mask Readback Operation
The internal value of the mask register is read out on the address
lines. The address is valid tCA after the selected number of
latency cycles configured by FTSEL. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 7 on page 16 shows a block diagram of the
operation.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset to
‘0’. All masked bits remain unchanged. A mask reset followed by
a counter reset resets the counter and mirror registers to 00000.
Mask Reset Operation
The mask register is reset to all 1s, that unmasks every bit of the
burst counter.
Note
28.The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
CYD09S18V18 devices have 19 address bits. The CYD18S 72V18 and CY D09S36V18 d evices have 18 address bits. The CYD09S72V 18 devi ce has 1 7 address bit s.
The CYD02S36V18 has 16 address bits.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 14 of 53
Table 7. Burst Counter and Mask Register Control Operations
The burst counter and mask register control operation for any port follows. [29, 30]
CMRST CNTRST CNT/MSK CNTEN ADS RET Operation Description
X L X X X X X Master reset Reset address counter to all 0s, mask
register to all 1s, and busy address to all 0s.
H L H X X X Counter reset Reset counter and mirror unmasked portion
to all 0s.
H L L X X X Mask reset Reset mask register to all 1s.
H H H L L X Counter load for
burst/external address
load for non-burst
Load burst counter and mirror with external
address value presented on address lines.
H H L L L X Mask load Load mask register with value presented on
the address lines.
H H H L H L Retransmit Load counter with value in the mirror register .
H H H L H H Counter incre ment Internally increment address counter value.
H H H H H H Counter hold Constantly hold the address value for
multiple clock cycles.
H H H H L H Counter readback Read out counter internal value on address
lines.
H H L H L H Mask readback Read out mask register value on address
lines.
H H L H H L Busy address readback Read out first busy address after last busy
address readback.
HH LLHXReserved
HH LHLLReserved
HH LHHHReserved
HH HHLLReserved
HH HHHLReserved
Notes
29.“X” = Don’t Care, “H” = HIGH, “L” = LOW.
30.Counter operation and mask register operation is independent of chip enables.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 15 of 53
Increment Operation[31]
After the address counter is initially loaded with an external
address, the counter can internally increment the address value
and address the entire memory array . Only the unmasked bits of
the counter register are incremented. For a counter bit to
change, the corresponding bit in the mask register must be 1. If
the two least significant bits of the mask register are 1 1, the burst
counter increments by one. If the two least significant bits are 10,
the burst counter increments by two, and if they are 00, the burst
counter increments by four. If all unmasked counter bits are
incremented to 1 and WRP is deasserted, the next increment l
wraps the counter back to the initially loaded value. The cycle
before the increment that results in all unmasked counter bits to
become 1s, a counter interrupt flag (CNTINT) is asserted if the
counter is incremented again. This increment causes the counter
to reach its maximum value and the next increment returns the
counter register to its initial value that was stored in the mirror
register if WRP is deasserted. If WRP is assert ed, the unmasked
portion of the counter is filled with 0 instead. The example shown
in Figure 8 on page 17 shows an example of the
CYDD36S18V18 device with the mask register loaded with a
mask value of 00007F unmasking the seven least significant bits.
Setting the mask register to this value enables the counter to
access the entire memory space. The address counter is then
loaded with an initial value of 000005 assuming WRP is
deasserted. The masked bi ts, the seventh address through the
twenty-first address, do not increment in an increment operation.
The counter address starts at address 000005 and increments
its internal address value until it reaches the mask register value
of 00007F. The counter wraps around the memory block to
location 000005 at the next count. CNTINT is issued when the
counter reaches the maximum –1 count.
Hold Operation
The value of all three registers is constantly maintained
unchanged for an unlimited number of clock cycles. This
operation is useful in applications where wait states are needed
or when address is available a few cycles ahead of data in a
shared bus interface.
Retransmit
Retransmit enables repeated access to the same block of
memory without the need to reload the initial address. An internal
mirror register stores the address counter value last loaded.
While RET is asserted low, the counter continues to wrap b ack
to the value in the mirror register independent of the state of
WRP.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW one clock cycle
before an increment operation that results in the unmasked
portion of the counter register being all 1s. It is deasserted by
counter reset, counter load, counter increment, mask reset,
mask load, and MRST.
Counting by Two
When the two least si gnificant bits of the mask register are 10,
the counter increments by two.
Counting by Four
When the two least si gnificant bits of the mask register are 00,
the counter increments by four.
Mailbox Interrupts
Use the upper two me mory locations for message passing and
permit communications between ports. Table 8 on page 17
shows the interrupt operation for both ports. The highest memory
location is the mailbox for the right port and the maximum
address – 1 is the mailbox for the left port.
When one port writes to the other port’s mailbox, the INT flag of
the port that th e mailbox belongs to is asserted LOW. The INT
flag remains asserted until the mailbox location is read by the
other port. When a port reads its mailbox, the INT flag is
deasserted high after one cycle of latency with respect to the
input clock of the port to which the mailbox belongs and is
independent of OE.
As shown in Table 8 on page 17, to set the INTR flag, a write
operation by the left port to address 1FFFFF asserts INTR LOW.
A valid read of the 1FFFFF location by the right port resets INTR
HIGH after one cycle of latency with respect to the right port’s
clock. You must activate at least one byte enable to set or reset
the mailbox interrupt.
Note
31.The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
CYD09S18V18 devices have 19 ad dress bits. The CYD18S 72V18 and CYD09S36V18 d evices have 18 address bit s. The CYD09S72V18 devi ce has 17 address bits.
The CYD02S36V18 has 16 address bits.
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Document Number: 38-0608 2 Rev. *M Page 16 of 53
Figure 7. Counter, Mask, and Mirror Logic Block Diagram
Figure 7 shows the counter, mask, and mirror logic block diagram. [32]
From
Mask
Register
Mirror Counter
Address
Decode
RAM
Array
Wrap
1
0
Increment
Logic
1
0
+1
+2
1
0
Wrap
Detect
From
Mask
From
Counter
To Coun-
ter
Bit 0
and 1 Wrap
20 20
20
20
20
1
0
Load/Increment
CNT/MSK
CNTEN
A
CNTRST
C
Decode
Logic
AMask
Register
Counter/
Address
Register
From
Address
Lines To Readback
and Address
Decode
20
20
MRST
RET
+4
Note
32.The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
CYD09S18V18 devices have 19 address bits. The CYD18S 72V18 and CY D09S36V18 d evices have 18 address bits. The CYD09S72V 18 devi ce has 1 7 address bit s.
The CYD02S36V18 has 16 address bits.
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Document Number: 38-0608 2 Rev. *M Page 17 of 53
Figure 8. Programmable Counter-Mask Register Operation with WRP deasserted
Figure 8 shows the programmable counter-mask operation with WRP deasserted. [36, 38]
Table 8. Interrupt Operatio n Example
Table 8 shows the interrupt operation example. [33, 34, 35, 37, 38]
Function Left Port Right Port
R/WLCELA0L–20L INTLR/WRCERA0R–20R INTR
Set Right INTR Flag L L Max Address X X X X L
Reset Right INTR Flag X X X X H L Max Address H
Set Left INTL Flag X X X L L L Max Address–1 X
Reset Left INTL Flag H L Max Address–1 H X X X X
220 219 2621
2522
242320
220 219 2621
2522
242320
220 219 2621
2522
242320
220 219 2621
2522
242320
H
H
L
H
11
0s 1
01
0111
00
Xs 0
X1
X001
11
Xs 1
X1
X111
00
Xs 0
X1
X001
Masked Address Unmasked Address
Mask
Register
LSB
Address
Counter
LSB
CNTINT
Example:
Load
Counter-Mask
Register = 00007F
Load
Address
Counter = 000005
Max
Address
Value
Max + 1
Address
Value
0
27
X
27
X
27
X
27
Notes
33.CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single read operation, CE only needs to be asserted once at the rising edge of the C and is
deasserted after that. Data is out after the following C edge and is tri-stated after the next C edge.
34.OE is “Don’t Care” for mailbox operation.
35.At least one of BE0, BE1 , BE2, BE3, BE4, BE 5 , BE 6 , or BE7 must be LOW.
36.The “X” in this diagram represents the counter’s upper bits.
37.“X” = Don’t Care, “H” = HIGH, “L” = LOW.
38.The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bi ts. The CYD36S72V18, CYD18S36V18, and
CYD09S18V18 devices have 1 9 address bit s. The CYD1 8S72V18 and CYD09S36V18 devices have 18 address bit s. The CYD09S7 2V18 device has 17 address bits.
The CYD02S36V18 has 16 address bits.
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Document Number: 38-0608 2 Rev. *M Page 18 of 53
Master Reset
The FullFlex family of Dual Ports undergoes a complete reset
when MRST is asserted. MRST must be driven by VDDIOL
referenced levels. The MRST is asserted asynchronously to the
clocks and must remain asserted for at least tRS. When asserted
MRST deasserts READY, initializes the internal burst counters,
internal mirror registers, and internal busy addresses to zero . It
also initializes the internal mask register to all 1s. All mailbox
interrupts (INT), busy address outputs (BUSY), and burst
counter interrupts (CNTINT) are deasserted upon master reset.
Additionally, do not release MRST until all power supplies
including VREF are fully ramped and all port clocks and mode
select inputs (LOWSPD, ZQ, CQEN, FTSEL, and PORTSTD)
are valid and stable. This begins calibration of the DLL and VIM
circuits. REA DY is asserted within 1024 clock cycles. READY is
a wired OR capable output with a strong pull up and weak pull
down. Up to four outputs may be connected together. For faster
pull down of the signal, connect a 250 Ohm resistor to VSS. If
the DLL and VIM circuits are disabled for a port, the port is
operational within five clock cycles. However, the READY is
asserted within 160 clock cycles.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The FullFlex families incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP op erates using
JEDEC-standard 3.3 V or 2.5 V IO logic levels depending on the
VTTL power supply . It is composed of four input connections and
one output connection requ ired by the test logic defined by the
standard.
Table 9. JTAG IDCODE Register Definitions
Part Number Configuration Value
CYD36S72V18 512 K × 72 0C026069h (×2)
CYD36S36V18 1024 K × 36 0C023069h
CYD36S18V18 2048 K × 18 0C024069h
CYD18S72V18 256 K × 72 0C025069h
CYD18S36V18 512 K × 36 0C026069h
CYD18S18V18 1024 K × 18 0C027069h
CYD09S72V18 128 K × 72 0C028069h
CYD09S36V18 256 K × 36 0C029069h
CYD09S18V18 512 K × 18 0C02A069h
CYD02S36V18 64 K × 36 0C030069h
Table 10. Scan Registers Sizes
Register Name Bit Size
Instruction 4
Bypass 1
Identification 32
Boundary Scan n[39]
Table 11. Instructio n Iden tification Codes
Instruction Code Description
EXTEST 0000 Captures the input and output ring contents. Places the BSR between the TDI and TDO.
BYPASS 1111 Places the BYR between TDI and TDO.
IDCODE 1011 Loads the IDR with the vendor ID cod e and places the register between TDI and TDO.
HIGHZ 011 1 Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers to a
High Z state.
CLAMP 0100 Controls boundary to 1 or 0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD 1000 Captures the input and output ring contents. Places BSR between TDI and TDO.
RESERVED All other
codes Other combinations are reserved. Do not use other than the mentione d combinations.
Note
39.Details of the boundary scan length is found in the BSDL file for the device.
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Document Number: 38-0608 2 Rev. *M Page 19 of 53
Maximum Rat ings
Exceeding maximum ratings may impair the useful life of the
device. User gui d el i ne s are no t te ste d.
Storage temperature............... ... ............. –65 °C to + 150 °C
Ambient temperature with
power applied..........................................–55 °C to + 125 °C
Supply voltage to ground potential ..............–0.5 V to + 4.1 V
DC voltage applied to
outputs in high Z State............... .. ... ..–0.5 V to VDDIO + 0.5 V
DC input voltage...............................–0.5 V to VDDIO + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage............... ............................> 2200 V
(JEDEC JESD8-6, JESD8-B)
Latch-up current .....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCORE
Commercial 0 °C to +70 °C 1.8 V 100 mV
1.5 V 80 mV
Industrial –40 °C to +85 °C 1.8 V 100 mV
1.5 V 80 mV
Power Supply Requirements
Min Typ Max
LVTTL VDDIO 3.0 V 3.3 V 3.6 V
2.5 V LVCMOS VDDIO 2.3 V 2.5 V 2.7 V
HSTL VDDIO 1.4 V 1.5 V 1.9 V
1.8 V LVCMOS VDDIO 1.7 V 1.8 V 1.9 V
3.3 V VTTL 3.0 V 3.3 V 3.6 V
2.5 V VTTL 2.3 V 2.5 V 2.7 V
HSTL VREF 0.68 V 0.75 V 0.95 V
Electrical Characteristics
Over the Operating Range
Parameter Description Configuration All Speed Bins Unit
Min Typ Max
VOH Output HIGH voltage
(VDDIO = Min, IOH = –8 mA) LVTTL 2.4[40] ––V
(VDDIO = Min, IOH = –4 mA) HSTL (DC)[41] VDDIO – 0.4[40] ––V
(VDDIO = Min, IOH = –4 mA) HSTL (AC)[41] VDDIO – 0.5[40] ––V
(VDDIO = Min, IOH = –6 mA) 2.5 V LVCMOS 1.7[40] ––V
(VDDIO = Min, IOH = –4 mA) 1.8 V LVCMOS VDDIO – 0.45[40] ––V
VOL Output HIGH voltage
(VDDIO = Min, IOL = 8 mA) LVTTL – – 0.4[40] V
(VDDIO = Min, IOL = 4 mA) HSTL(DC)[41] ––0.4
[40] V
(VDDIO = Min, IOL = 4 mA) HSTL (AC)[41] ––0.5
[40] V
(VDDIO = Min, IOL = 6 mA) 2.5 V LVCMOS – – 0.7[40] V
(VDDIO = Min, IOL = 4 mA) 1.8 V LVCMOS – – 0.45[40] V
VIH Input HIGH voltage LVTTL 2 – VDDIO + 0.3 V
HSTL(DC)[41] VREF + 0.1 – VDDIO + 0.3 V
2.5 V LVCMOS 1.7 – V
1.8 V LVCMOS 0.65 × VDDIO – V
VIL Input LOW voltage LVT TL –0.3 – 0.8 V
HSTL(DC)[41] –0.3 – VREF – 0.1 V
2.5 V LVCMOS – – 0.7 V
1.8 V LVCMOS – – 0.35 × VDDIO V
Notes
40.These parameters are met with VIM disabled.
41.The DC specifications are measured under steady state conditions. The AC specifications are measured while switching at speed. AC VIH/VIL in HSTL mode
are measured with 1 V/ns input edge rates.
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READY
VOH
Output HIGH voltage
(VDDIO = Min, IOH = –24 mA) LVTTL 2.7[42] ––V
(VDDIO = Min, IOH = –12 mA) HSTL(DC)[43] VDDIO – 0.4[42] ––V
(VDDIO = Min, IOH = –12 mA) HSTL (AC)[43] VDDIO – 0.5[42] ––V
(VDDIO = Min, IOH = –15 mA) 2.5 V LVCMOS 2.0[42] ––V
(VDDIO = Min, IOH = –12 mA) 1.8 V LVCMOS VDDIO – 0.45[42] ––V
READY
VOL
Output HIGH voltage
(VDDIO = Min, IO = 0.12 mA) LVTTL – – 0.4[42] V
(VDDIO = Min, IOL = 0.12 mA ) HSTL(DC)[43] ––0.4
[42] V
(VDDIO = Min, IOL = 0.12 mA) HSTL (AC)[43] ––0.5
[42] V
(VDDIO = Min, IOL = 0.15 mA) 2.5 V LVCMOS – – 0.7[42] V
(VDDIO = Min, IOL = 0.08 mA) 1.8 V LVCMOS – – 0.45[42] V
IOZ Output leakage current –10 – 10 A
IIX1 Input leakage current except
TDI, TMS, MRST, PORTSTD –10 – 10 A
IIX2 Input leakage current TDI,
TMS, MRST –300 – 10 A
IIX3 Input leakage current
PORTSTD –10 – 300 A
Electrical Characteristics (continued)
Over the Operating Range
Parameter Description Configuration All Speed Bins Unit
Min Typ Max
Notes
42.These parameters are met with VIM disabled.
43.The DC specifications are measured under steady state conditions. The AC specifications are measured while switching at speed. AC VIH/VIL in HSTL mode are
measured with 1 V/ns input edge rates.
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Electrical Characteristics
Over the Operating Range
Parameter Description Configuration -200 -167 Unit
Typ Max Typ Max
ICC Operating current
(VCORE = Max, IOUT = 0 mA)
outputs disabled
512 K × 72 Commercial 1440 1800 1280 1620 mA
Industrial – – 1330 1730 mA
1024 K × 36 Commercial 1180 1500 1050 1350 mA
Industrial – – 1110 1470 mA
2048 K × 18 Commercial 1130 1430 1000 1290 mA
Industrial – – 1060 1410 mA
256 K × 72 Commercial 800 980 700 880 mA
Industrial 820 1030 730 930 mA
512 K × 36 Commercial 640 800 570 720 mA
Industrial 670 860 590 780 mA
1024 K × 18 Commercial 610 770 540 690 mA
Industrial 640 830 570 750 mA
128 K × 72 Commercial 640 790 560 700 mA
Industrial 660 830 580 740 mA
256 K × 36 Commercial 540 640 470 570 mA
Industrial 550 670 490 600 mA
512 K × 18 Commercial 550 660 480 580 mA
Industrial 570 690 500 610 mA
64 K × 36 Commercial – – – – mA
Industrial – – – – mA
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ISB1 Standby current
(both ports TTL Level)
CEL and CER VIH, f = fMAX
512 K × 72 Commercial 1000 1250 920 1160 mA
Industrial – – 970 1260 mA
1024 K × 36 Commercial 910 1140 820 1050 mA
Industrial – – 880 1160 mA
2048 K × 18 Commercial 890 1110 810 1030 mA
Industrial – – 860 1140 mA
256 K × 72 Commercial 500 630 460 580 mA
Industrial 530 680 490 630 mA
512 K × 36 Commercial 460 570 410 530 mA
Industrial 480 630 440 580 mA
1024 K × 18 Commercial 450 560 410 520 mA
Industrial 470 610 430 570 mA
128 K × 72 Commercial 400 490 360 450 mA
Industrial 420 540 380 490 mA
256 K × 36 Commercial 380 440 340 400 mA
Industrial 390 470 360 430 mA
512 K × 18 Commercial 390 460 350 410 mA
Industrial 410 480 370 440 mA
64 K × 36 Commercial – – – – mA
Industrial – – – – mA
Electrical Characteristics (continued)
Over the Operating Range
Parameter Description Configuration -200 -167 Unit
Typ Max Typ Max
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ISB2 Standby current
(one port TTL or CMOS level)
CEL | CER VIH, f = fMAX
512 K × 72 Commercial 1300 1570 1160 1410 mA
Industrial – – 1210 1520 mA
1024 K × 36 Commercial 1090 1330 980 1210 m A
Industrial – – 1030 1330 mA
2048 K × 18 Commercial 1040 1270 930 1160 mA
Industrial – – 980 1270 mA
256 K × 72 Commercial 650 790 580 710 mA
Industrial 680 840 610 760 mA
512 K × 36 Commercial 550 670 490 610 mA
Industrial 570 730 520 670 mA
1024 K × 18 Commercial 520 640 470 580 mA
Industrial 550 690 490 640 mA
128 K × 72 Commercial 520 630 460 560 mA
Industrial 550 670 480 610 mA
256 K × 36 Commercial 460 530 400 470 mA
Industrial 480 560 430 500 mA
512 K × 18 Commercial 460 530 410 480 mA
Industrial 480 560 430 510 mA
64 K × 36 Commercial – – – – mA
Industrial – – – – mA
Electrical Characteristics (continued)
Over the Operating Range
Parameter Description Configuration -200 -167 Unit
Typ Max Typ Max
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Electrical Characteristics
Over the Operating Range
Parameter Description Configuration All Speed Bins Unit
Typ Max
ISB3 Standby current
(both ports CMOS level)
CEL and CER VCORE – 0.2 V, f = 0
512 K × 72 Commer cial 410 590 mA
Industrial 460 700 mA
1024 K × 36 Comm erci a l 410 590 mA
Industrial 460 700 mA
2048 K × 18 Comm erci a l 410 590 mA
Industrial 460 700 mA
256 K × 72 Commer cial 210 300 mA
Industrial 230 350 mA
512 K × 36 Commer cial 210 300 mA
Industrial 230 350 mA
1024 K × 18 Comm erci a l 210 300 mA
Industrial 230 350 mA
128 K × 72 Commer cial 150 200 mA
Industrial 170 220 mA
256 K × 36 Commer cial 150 200 mA
Industrial 170 220 mA
512 K × 18 Commer cial 150 200 mA
Industrial 170 220 mA
Capacitance
Signals Packages
CYD18S72V18
CYD09S72V18
CYD18S36V18
CYD09S36V18
CYD02S36V18
CYD18S18V18
CYD09S18V18 CYD36S72V18
CYD36S36V18 CYD36S18V18
OE 12 pF 12 pF 20 pF 20 pF
BE, DQ 10 pF 18 pF 16 pF 30 pF
All other signals 10 pF 10 pF 16 pF 16 pF
Thermal Resist ance
Parameter Description Test Condition s 48 4-ball BGA 256-ball BGA
(18Mbit only) 256-ball BGA
(9Mbit & 2Mbit) Unit
JA Thermal resistance
(junction to ambient) Still air , soldered on a 3 × 4.5 inch,
four layer printed circuit board
14.92
17.02 18.31 °C/W
JC Thermal resistance
(junction to case)
3.6
1.25 1.68 °C/W
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AC Test Load and W aveforms
Figure 9. Output Test Load for LVTTL/CMOS
Figure 10. Output Test Load for HSTL
Figure 11. HSTL Input Waveform
Output
50 Ohm 50 Ohm
VTH = 1.5
V for LVTT
L
VTH = 50% VDDIO for 2.5
V CMO
S
VTH = 50% VDDIO for 1.8
V CMO
S
ZQ
RQ=250 Ohm
Device under
test
VREF VREF = NC
Test Point
C = 10pF
READY
R=250 Ohm VTH
Output
50 Ohm 50 O hm
VTH = 50% VDDIO
ZQ
RQ=250 Ohm
Device under
test
VREF
VREF = 0.75V
Test Point
C= 10pF for SDR
R=250 Ohm
READY VTH
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Switching Characteristics
Over the Operating Range
Table 12. SDR Mode, Signals Affected by DLL
Parameter
Description DLL ON (LOWSPD=1)[46] DLL OFF (LOWSPD=0)[46]
-200 -167 Unit
Min Max Min Max Min Max
tCD2[49] C rise to DQ valid for pipelined
mode –3.30
[45, 48] –4.00
[45, 48] –6.00
[45, 48] ns
tCCQ[49] C rise to CQ rise 1.00 3.30 [48] 1.00 4.00[48] 1.00 6.00[48] ns
tCKHZ2[44, 49] C rise to DQ output high Z in
pipelined mode 1.00 3.30[45, 48] 1.00 4.00[45, 48] 1.00 6.00[45, 48] ns
tCKLZ2[44, 49] C rise to DQ ou tput low Z in
pipelined mode 1.00 – 1.00 – 1.00 – ns
Table 13. SDR Mode
Parameter Description -200 -167 Unit
Min Max Min Max
fMAX
(PIPELINED)Maximum operating frequency for pipelined mode 100 200 100 167 MHz
fMAX (FLOW
THROUGH)Maximum operating frequency for flow through mode – 77 – 66.7 MHz
tCYC
(PIPELINED)C clock cycle time for pipelined mode 5.00[48] 10.00 6.00[48] 10.00 ns
tCYC (FLOW X
THROUGH)C clock cycle time for flow through mode 13.00[48] –15.00
[48] –ns
tCKD C clock duty time 45 55 45 55 %
tSD Data input setup time to C
rise HSTL
1.8 V LVCMOS 1.50[45, 48] –1.70
[45, 48] –ns
2.5 V LVCMOS
3.3 V LVTTL 1.75[45, 48] –1.95
[45, 48] ns
tHD[47] Data input hold time after C rise 0.5 – 0.5 – ns
tSAC Address and control input
setup time to C rise HSTL
1.8 V L VCMOS 1.50[45, 47, 48] –1.70
[45, 47, 48] –ns
2.5 V LVCMOS
3.3 V LVTTL 1.75[45, 47, 48] –1.95
[45, 47, 48] –ns
tHAC[47] Address and control input hold time after C rise 0.50 – 0.60 – ns
tOE Output enable to data valid – 4.40[45, 48] –5.00
[45, 48] ns
tOLZ[44] OE to low Z 1.00 – 1.00 – ns
Notes
44.Parameters sp ecified with the load capacitance in Figure 9 on page 25 and Figure 10 on page 25.
45.For the x18 devices, add 200 ps to this parameter in Table 13.
46.Test conditions assume a signal transition time of 2 V/ns.
47.Add 300 ps to this timing for 36M devices.
48.Add 15% to this parameter if a VCORE of 1.5 V is used.
49.This paramet er assumes input clock cycle to cycle jitter of ± 0 ps.
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tOHZ[50] OE to high Z 1.00 4.40[51, 52] 1.00 5.00[51, 52] ns
tCD1 C rise to DQ valid for flow through mode
(LowSPD = 0) –9.00
[51, 52] – 11.00[51, 52] ns
tCA1 C rise to address readback valid for flow through mode – 9.00[52] – 11.00[52] ns
tCA2 C rise to address readback valid for pipelined mode – 5.00[52] –6.00
[52] ns
tDC[53] DQ output hold after C rise 1.00 – 1.00 – ns
tJIT Clock input cycle to cycle jitter – +/- 200 – +/- 200 ps
tCQHQV[53] Echo clock (CQ) high to
output valid HSTL
1.8 V LVCMOS –0.70
[51] –0.80
[51] ns
2.5 V LVCMOS
3.3 V LVTTL –0.80
[51] –0.90
[51] ns
tCQHQX[53] Echo clock (CQ) high to
output hold HSTL
1.8 V LVCMOS –0.70 – –0.80 – ns
2.5 V LVCMOS 3.3 V
LVTTL –0.85 – –0.95 – ns
tCKHZ1[50] C rise to DQ output high Z in flow through mode 1.00 9.00[51, 52] 1.00 11.00[51, 52] ns
tCKLZ1[50] C rise to DQ output low Z in flow through mode 1.00 – 1.00 – ns
tAC Address output hold after C rise 1.00 – 1.00 – ns
tCKHZA1[50] C rise to address output high Z for flow through mode 1.00 9.00[52] 1.00 11.00[52] ns
tCKHZA2[50] C rise to address output high Z for pipelined mode 1.00 5.00[52] 1.00 6.00[52] ns
tCKLZA[50] C rise to address output low Z 1.00 – 1.00 – ns
tSCINT C rise to CNTINT low 1.00 3.30[52] 1.00 4.00[52] ns
tRCINT C rise to CNTINT high 1.00 3.30[52] 1.00 4.00[52] ns
tSINT C rise to INT low 0.50 7.00[52] 0.50 8.00[52] ns
tRINT C rise to INT high 0.50 7.00[52] 0.50 8.00[52] ns
tBSY C rise to BUSY valid 1.00 3.30[52] 1.00 4.00[52] ns
Table 13. SDR Mode (continued)
Parameter Description -200 -167 Unit
Min Max Min Max
Notes
50.Parameters sp ecified with the load capacitance in Figure 9 on page 25 and Figure 10 on page 25.
51.For the × 18 devices, add 200 ps to this parameter in Table 13.
52.Add 15% to this parameter if a VCORE of 1.5 V is used.
53.This parameter assumes input clock cycle to cycle jitter of ±0 ps.
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CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 28 of 53
Table 14. Master Reset Timing
Parameter Description -200 -167 Unit
Min Max Min Max
tPUP Power-up time 1–1–ms
tRS Master reset pulse width 5 – 5 – cycles
tRSR Master reset recovery time 5 – 5 – cycles
tRSF Master reset to outputs inactive/Hi Z – 15 – 18 ns
tRDY[54] Master reset release to port ready – 1024 – 1 024 cycles
tCORDY[55] C rise to port ready – 9.5[56] –11
[56] ns
Table 15. JTAG Timing
Parameter Description -200 -167 Unit
Min Max Min Max
fJTAG JTAG TAP controller frequency – 20 – 20 MHz
tTCYC TCK cycle time 50 – 50 – ns
tTH TCK high time 20 – 20 – ns
tTL TCK low time 20 – 20 – ns
tTMSS TMS setup to TCK rise 10 – 10 – ns
tTMSH TMS hold to TCK rise 10 – 10 – ns
tTDIS TDI setup to TCK rise 10 – 10 – ns
tTDIH TDI hold to TCK rise 10 – 10 – ns
tTDOV TCK low to TDO valid – 10 – 10 ns
tTDOX TCK low to TDO invalid 0 – 0 – ns
tJXZ TCK low to TDO high Z – 15 – 1 5 ns
tJZX TCK low to TDO active – 15 – 15 ns
tJZX TCK low to TDO active – 15 – 15 ns
.
Notes
54.READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250- resistor to VSS.
55.Add this propagation delay after tRDY for all Master Reset Operations.
56.Add 15% to this parameter if a VCORE of 1.5 V is used.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 29 of 53
Switching Waveforms
Figure 12. JTA G Timing
Figure 13. Master Reset [57]
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
TDO
tTCYC
tTMSH
tTL
tTH
tTMSS
tTDIS tTDIH
tTDOX tTDOV
tPUP tRS
tRSF
tRSR
VCORE
MRST
C
READY
All Address
& Data
All Other
Inputs
tRDY tCORDY
~
~
~
~
~
~
Note
57.READY is a wired OR capable output with a weak pull-down. For a decreased fall ing delay, connect a 250- resistor to VSS.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 30 of 53
Figure 14. READ Cycle for Pipelined Mode
Figure 15. WRITE Cycl e for Pipelined and Fl ow through Modes
Switching Waveforms (continue d)
C
t
CYC
R/
W
A
2 Pipelined stages
A
n
A
n+1
A
n+2
A
n+3
A
n+4
A
n+5
A
n+6
DQ
x-1
DQ
x
DQ
n
DQ
n+1
DQ
n+2
DQ
n+3
DQ
n+4
t
DC
t
CD2
t
SAC
t
HAC
DQ
CE
OE
tCYC
C
R/W
AAnAn+1 An+2 An+3 An+4 An+5 An+6
DQnDQn+1 DQn+2 DQn+3 DQn+4 DQn+5 DQn+6
2 Pipelined stages
tSD tHD
DQ
CE
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 31 of 53
Figure 16. READ with Address Counter Advance for Pipelined Mode
Figure 17. READ with Address Counter Advance for Flow through Mode
Switching Waveforms (continue d)
C
tCYC
DQx-1 DQxDQnDQn+1 DQn+2
A
Internal
ADS
Address
CNTEN
A
n+1
An
An+2 A
n+3
DQn+3
DQ
An
tCYC
C
tSAC tHAC
tHAC
tDC
tCD1
tSAC
READ EXTERNAL ADDRESS READ WITH COUNT ERCOUNTER HOLDREAD W ITH COUNTER
DQx DQn + 1 DQn + 2 DQn + 3 DQn + 4DQn
An
A
DQ
CNTEN
ADS
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 32 of 53
Figure 18. Port-to-Port WRITE–READ for Pipelined Mode
Figure 19. Chip Enable READ for Pipelined Mode
Switching Waveforms (continue d)
C
L
A
n
DQ
n
Left Port
R/W
L
C
R
Right Port
A
n
R/W
R
DQ
n
t
CD2
t
DC
t
SAC
t
HAC
t
CYC
t
CYC
t
CCS
A
L
DQ
L
A
R
DQ
R
C
R/W
AA
n
A
n+1
A
n+2
A
n+3
A
n+4
A
n+5
A
n+6
t
SAC
t
HAC
t
CYC
CE0
CE1
DQ DQ
n
DQ
n+3
t
CD2
t
DC
t
CKLZ2
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 33 of 53
Figure 20. OE Controlled WRITE for Pipelined Mode
Figure 21. OE Controlled WRITE for Flow through Mode
Switching Waveforms (continue d)
C
R/W
AAx+1 Ax+2 Ax+3 AnAn+1 An+2 An+3
tCYC
DQx-1 DQx
DQx+1 DQnDQn+1 DQn+2 DQn+3
OE
DQ
tOHZ
C
R/W
AAx+1 Ax+2 Ax+3 AnAn+1 An+2 An+3
tCYC
DQxDQx+1
DQx+2 DQnDQn+1 DQn+2 DQn+3
OE
DQ
tOHZ
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 34 of 53
Figure 22. Byte-Enable READ for Pipelined Mode
Switching Waveforms (continue d)
C
R/W
AAnAn+1 An+2 An+3
tCYC
BE7
BE6
BE5
BE4
BE3
BE2
BE1
BE0
DQ63:71
DQ54:62
DQ45:53
DQ36:44
DQ27:35
DQ18:26
DQ9:17
DQ0:8
DQn+1(63:71)
DQn+1(54:62)
DQn+1(27:35)
DQn+2(45:53)
DQn+2(36:44)
DQn+2(18:26)
DQn+3(9:17)
DQn+3(0:8)
tCKLZ2 tCKHZ2
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 36 of 53
Figure 24. Busy Address Readb ack for Pipelined and Flow through Mo des, CNT/MSK = RET = LOW [58]
Figure 25. Read Cycle for Flow thr ough Mode
Switching Waveforms (continue d)
Internal Amatch+2 Amatch+3 Amatch+4
tCYC
C
BUSY
~
~
~
~
~
~
CNTEN
ADS
External Amatch
tCA2 tAC
Address
Pipelined
~Amatch
tCA1 tAC
Flow through
Address
External
Address
tCYC
tSAC tHAC
tCKHZ1
tDC
tOE
tOLZ
tOHZ
tDCtCD1
tCKLZ1
An
tHACtSAC
CE1
CE0
C
An + 1 An + 3An + 2
DQn DQn + 1 DQn + 2
R/W
OE
BEn
A
DQ
Note
58.Amatch is the matching address that is reported on the address bus of the losing port. The count er operation selected for reporting the address is “Busy Address
Readback.”
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 37 of 53
Figure 26. READ-to-WRITE for Pipelined Mode (OE = VIL) [59, 60, 61]
Figure 27. READ-to-WRITE for Pipelined Mode (OE Controlled) [62, 63]
Switching Waveforms (continue d)
C
AAxAnAn+1 An+2
tCYC
DQx-2 DQx-1 DQxDQnDQn+1 DQn+2
tCH
tCL
tSAC tHAC tSAC tHAC
tDC
tCD2 tCKHZ2 tSD tHD
R/W
DQ
tCKLZ2
C
R/W
AAxAx+1 Ax+2 AnAn+1 An+2 An+3
tCYC
DQx-2 DQx-1 DQxDQnDQn+1 DQn+2 DQn+3
tSAC tHAC
tOHZ tSD tHD
OE
DQ
Notes
59.When OE = VIL, the last read operation is enabled to complete before the DQ bus is tri-stated and the user is enabled to drive writ e data.
60.Two dummy writes are issued to accomplish bus turnaround. The third instruction is the first valid write.
61.Chip enable or all byte enables are held inactive during the two dummy writes to avoid data corruption.
62.OE is deasserted and tOHZ enabled to elapse before the first write operation is issued.
63.Any write scheduled to complete after OE is deassert ed is pre-empted.
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 38 of 53
Figure 28. Read-to-Write-to-Read for Flow through Mode (OE = LOW)
Switching Waveforms (continue d)
tHDtSD
tSAC
tCKHZ1
tDC
tCD1
tCD1
tSAC
tCYC
tHAC
tDC
tCD1tCD1
tCKLZ1
READ READWRITENOP
An An + 1 A n + 2 An + 2 An + 3 An + 4
DQn + 2
DQn DQn + 1 DQn + 3
C
R/W
BEn
CE1
DQOUT
DQIN
A
tHAC
CE0
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 39 of 53
Figure 29. Read-to-Write-to-Read for Flow through Mode (OE Controlled)
Switching Waveforms (continue d)
tCD1
tCKLZ1
tHDtSD
tOHZ
tDCtCD1
tHAC
tSAC
tCYC
tDC
tCD1
tOE
READ READWRITE
A n A n + 1 A n + 2 A n + 3 An + 4 A n + 5
DQn + 2 DQ n + 3
DQn DQ n + 4
C
R/W
BEn
CE1
DQOUT
DQIN
A
OE
tHAC
tSAC
CE0
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 40 of 53
Figure 30. BUSY Timing, WRITE-WRITE Collision for Pipelined an d Flow through Modes, Clock Timing Violates tCCS.
(Flag Both Ports)
Switching Waveforms (continue d)
Port A
A
R/W
tBSY tBSY
BUSY
Port B < tCCS
A
R/W
tBSY tBSY
BUSY
C
Losing Port
C
A
R/W
tBSY tBSY
BUSY
Winning Port
A
R/W
C
tccs
Match
C
Figure 31. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow through Modes, Clock Timing Meets tCCS.
(Flag Losing Port)
BUSY
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 43 of 53
Ordering Information
512 K
×
72 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S72V18 Dual Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD36S72V18-200BGXC 001-07825
484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free)
Commercial
167 CYD36S72V18-167BGXI 001-07825
484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free)
Industrial
256 K
×
72 (18-Mbit) 1.8 V/1.5 V Synchronou s CYD18S72V18 Dual Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD18S72V18-200BGXI 51-85218
484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free)
Industrial
200 CYD18S72V18-200BGI 51-85218
484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch
Industrial
167 CYD18S72V18-167BGXC 51-85218
484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free)
Commercial
167 CYD18S72V18-167BGC 51-85218
484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch
Commercial
167 CYD18S72V18-167BGI 51-85218
484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch
Industrial
128 K
×
72 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S72V18 Dual Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD09S72V18-200BGXI 51-85218
484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free)
Industrial
167 CYD09S72V18-167BBXC 51-85218
484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free)
Commercial
1024 K
×
36 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S36V18 Dual Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD36S36V18-200BGXC 001-07825
484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free)
Commercial
167 CYD36S36V18-167BGXC 001-07825
484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free)
Commercial
167 CYD36S36V18-167BGXI 001-07825
484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free)
Industrial
512 K
×
36 (18-Mbit) 1.8 V/1.5 V Synchronou s CYD18S36V18 Dual Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD18S36V18-200BBAXI 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Industrial
167 CYD18S36V18-167BBAI 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch
Industrial
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 44 of 53
256 K
×
36 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S36V18 Dual Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD09S36V18-200BBXC 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Commercial
200 CYD09S36V18-200BBXI 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Industrial
167 CYD09S36V18-167BBXC 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Commercial
64 K
×
36 (2-Mbit) 1.8 V or 1.5 V Synchronous CYD02S36V18 Dual Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD02S36V18-200BBC 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch
Commercial
Ordering Information (continued)
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 45 of 53
2048 K
×
18 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S18V18 Dual Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD36S18V18-200BGXC 001-07825
484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free)
Commercial
167 CYD36S18V18-167BGXC 001-07825
484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free)
Commercial
167 CYD36S18V18-167BGXI 001-07825
484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free)
Industrial
1024 K
×
18 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S18V18 Dual Port SRAM
Speed
MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD18S18V18-200BBAXI 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Industrial
200 CYD18S18V18-200BBAXC 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Commercial
167 CYD18S18V18-167BBAXI 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Industrial
512 K
×
18 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S18V18 Dual Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
200 CYD09S18V18-200BBXC 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Commercial
200 CYD09S18V18-200BBXI 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Industrial
167 CYD09S18V18-167BBXI 51-85108
256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free)
Industrial
Ordering Code Definitions
Ordering Information (continued)
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: (XXX = BG or BB or BBA)
BG, BB, BBA = Ball Grid Array
Speed Grade: XXX = 167 MHz or 200 MHz
V18 = 1.8 V
SXX = Data Width
DXX = Density in Mb
CY = Cypress
CY DXX V18 - XXX XXX XSXX X
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 49 of 53
Acronyms Document Conventions
Units of Measure
Acronym Description
BGA ball grid array
CMOS complementary metal oxide semiconductor
DLL delay lock loop
FBGA fine pitch ball gird array
HSTL high speed transceiver logic
I/O input/output
SDR single data rate
SRAM static random access memory
TCK test clock
TDI test data-in
TDO test data-out
TMS test mode select
VIM variable impedance matching
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
ms millisecond
mV millivolt
ns nanosecond
pF picofarad
Vvolt
Wwatt
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 50 of 53
Document History Page
Document Title: CYDXXS72V18/CYDXXS36V18/CYDXXS18V18, FullFlex™ Synchronou s SDR Dual Port SRAM
Document Number: 38-06082
REV. ECN NO. Submission
Date Orig. of
Change Description of Chang e
** 302411 See ECN YDT New data sheet
*A 334036 See ECN Y DT Corrected typo on page 1
Reproduced PDF file to fix formatting errors
*B 395800 See ECN SPN Added statement about no echo clocks for flow through mode
Updated electrical characteristics
Added note 16 and 17 (1.5 V timing)
Added note 33 (timing for x18 devices)
Updated input edge rate (note 34)
Updated table 5 on deterministic acce ss control logic
Added description of busy readback in deterministic access control section
Changed dummy write descriptions
Updated ZQ pins connection details
Updated note 24, B0 to BE0
Added power supply require ments to MRST and VC_SEL
Added note 4 (VIM disable)
Updated supply voltage to ground pote ntial to 4.1 V
Updated parameters on table 15
Updated and added parameters to table 16
Updated x72 pinout to SDR only pinout
Updated 484 PBGA pin diagram
Updated the pin defin ition of MRST
Updated the pin defin ition of VC_SEL
Updated READY description to include Wired OR note
Updated master reset to include wired OR note for READY
Updated minimum VOH value for the 1.8 V LVCMOS configuration
Updated electrical characteristics to include IOH and IOL values
Updated electrical characteristics to include READY
Added IIX3
Updated maximum input capacitance
Added Notes 33 and 34Removed Notes 15 and 17
Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1
Removed -100 Speed bin from Selection Guide
Changed voltage name from VDDQ to VDDIO
Changed voltage name from VDD to VCORE
Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram
Updated the Package Type for the CYD36S18V18 parts
Updated the Package Type for the CYD36S18V18 parts
Updated the Package Type for the CYD18S18V18 parts
Updated the Package Type for the CYD18S36V18 parts
Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256
Included an OE Controlled Write for Flow through Mode Switching Waveform
Included a Read with Echo Clock Switching Waveform
Updated Figure 5 and Figure 6
Updated Electrical Characteristics for READY VOH and READY V
Updated Electrical Characte ristics for VOH and VOL for the -167 and -133
speeds
Included a Unit column for Table 5
Removed Switching Characteristic tCA from chart
Included tOHZ in Switching W aveform OE Controlled Write for Pipelined Mode
Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow through Mode
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 51 of 53
*C 402238 SEE ECN KGH Update d AC Test Load and Waveforms
Included FullFlex36 SDR 484-Ball BGA Pinout (Top View)
Included FullFlex18 SDR 484-Ball BGA Pinout (Top View)
Included Timing Parameter tCORDY
*D 458131 SEE ECN YDT Changed ordering information with
Pb
-free part numbers
Removed VC_SEL
Added IO and core voltage adders
Removed references to bin drop for LVTTL/2.5 V LVCMOS and 1.5 V core
modes
Updated Cin and Cout
Updated ICC, ISB1, ISB2 and ISB3 tables
Updated busy address read back timing diagram
Added HTSL input waveform
Removed HSTL (AC) from DC tables
Added 484-ball 27 mm × 27 mm × 2.33 mm PBGA package
*E 470031 SEE ECN YDT Changed VOL of 1.8 V LVCMOS to 0.45 V
Updated tRSF
VREF is DNU when HSTL is not used
Formatted pin description table
Changed VDDIO pins for 36M × 36 and 36M × 18 pinouts
Changed 36M × 72 JTAG IDCODE
*F 500001 SEE ECN YDT DLL Change, ad ded Clock Input Cycle to Cycle Jitter
Modified DLL description
Changed Input Capacitance Table
Changed tCCS number
Added note 31
*G 627539 SEE ECN QSL change all NC to DNU
corrected switching waveform for (CQEN = High) from both Pipeline and Flow
through mode to only pipeline mode
Modified master reset description
Modified switching characteristics tables, extracted signals effected by the DLL
into one table and combine all other signals into one table
updated package name
Added footnote for tHD, tHAC and tSAC
changed note 26 description
*H 2505003 See ECN VKN /
AESA Modified fo ot note #1
Removed 250 MHz speed bin
Added 2-Mbit part and it’s related information
Changed ball name ZQ1 to DNU for 18M and lesser density devices
Added 256-ball (17 × 17 mm) BGA package for 18M
Made PORTSTD[1:0] left and right pins driven only by LVTTL reference level
For 1.8 V LVCMOS level, Changed VIH(min) from 1.26 V to 0.65 times VDDIO
and changed VIL(max) from 0.36 V to 0.35 times VDDIO
Changed tHD, tHAC specs for 36M from 0.6 ns/0.7 ns to 0.8 ns (See footnote#
32)
Updated Ordering Information table
Document History Page (continued)
Document Title: CYDXXS72V18/CYDXXS36V18/CYDXXS18V18, FullFlex™ Synchronou s SDR Dual Port SRAM
Document Number: 38-06082
REV. ECN NO. Submission
Date Orig. of
Change Description of Chang e
[+] Feedback
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Document Number: 38-0608 2 Rev. *M Page 52 of 53
*I 2898491 07/01/2010 RAME Modified “Counter Load Operation” section on page 12 and in Table7 on page
13.
Corrected typo in Table 14. by making LowSPD = 0 for tCD1 spec in the
description.
Modified figure 16. on page 30.
Removed inactive parts from Ordering Information.
Updated Packaging Information.
Corrected “Counter Interrupt operation” Section in Page 14 of the data sheet
Updated ordering information with the parts, CYD02S36V18-200BBC and
CYD36S72V18-167BGI.
*J 2995098 07/28/2010 RAME Updated Ordering Informati on and added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
*K 3267210 05/26/2011 ADMU Updated Electrical Characteristics on page 21 (Removed 133 MHz speed bin).
Updated Switching Characteristics on page 26 (Removed 133 MHz speed bin).
Removed info rma t io n for 4M b de vi ce s.
Updated Ordering Information.
*L 3357888 08/30/2011 ADMU Added Thermal Resistance .
Updated Pin configurati on Figure 1 through 5.
*M 3349458 10/28/2011 ADMU Minor edits in Figure 5 (removed overbars in balls C5 and C12).
Updated Package Diagrams.
Document History Page (continued)
Document Title: CYDXXS72V18/CYDXXS36V18/CYDXXS18V18, FullFlex™ Synchronou s SDR Dual Port SRAM
Document Number: 38-06082
REV. ECN NO. Submission
Date Orig. of
Change Description of Chang e
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Document Number: 38-06082 Rev. *M Revised October 28, 2011 Page 53 of 53
All products and company names mentioned in this document may be the trademarks of their respective holders.
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
© Cypress Semico nducto r Co rpora tion , 2005 -2011. The infor mation cont ai ned he rein is subj ect to chang e with out no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress produc ts are n ot warranted no r inte nd ed to be used fo r
medical, life supp or t, lif e savi n g, critical control o r saf ety ap pli cations, unless pur suan t to a n express written agre em en t w it h Cy press. Fu rth er mor e, Cypre ss does not auth ori ze i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress p roducts in life -support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent prot ection (Un ited States and foreign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s t o license e a pers onal, no n-excl usive , non-tr ansferab le license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee prod uct to be used only in conju nction with a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this Sour ce Code except a s specified above i s prohibited wi thout
the express written permissi on of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials describ ed herein. Cyp ress does not
assume any liabil ity arisi ng ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts for use as critical compon ent s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive cypress.com/go/automotive
Clocks & Buffers cypress.com/go/clocks
Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
Optical & Image Sensing cypress.com/go/image
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
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