ANALOG DEVICES High Speed, Fast Settling Precision Operational Amplifier OP-42 58V/us slew rate and is internally compensated for unity-gain FEATURES Fast operation. OP-42 speedis achieved with a supply current ofless # SleW Rate... escsssssssssessseccccssssesssssssssssesessenssssssees 50V/us Min than 6mA. Unity-gain stability, a wide full-power bandwidth of Settling-Time (0.01%) vcscscsciscscsecesssessesseeessessesessees tus Max 900kHz, anda fast settling-time of 800ns to 0.01% make the OP- * Gain-Bandwidth Product 10MHzTyp 42 anideal output amplifier for fast digital-to-analog converters. Precise Equal attention was given to both speed and precision in the OP- * Common-Mode Rejection .....cccccccssesessesesessen 88dB Min 42 design. Its tight 7504V maximum input offset voltage com- Open-Loop Gaii...........ccssssssessecsesersssesesenees 500V/mV Min bined with well-controlled drift of less than 10uV/C eliminates * Offset Voltage .......cecccssccssecssecsseesssesseessiessesessees 750uV Max the need for external nulling in many circuits. The OP-42's Bias Current .......cscscccccssssssssssseecstseassenssesssaraessees 200pA Max Continued 7 P PIN CONNECTIONS Excellent Radiation Hardness Available in Die Form NC. 8 t ORDERING INFORMATION NULL 1 7+ T, = 25C PACKAGE OPERATING Vog MAX CERDIP PLASTIC SO LCC TEMPERATURE N? four (mV) TO-99 8-PIN &-PIN 8-PIN 20-CONTACT RANGE 1.0 OP42AJ* OPazAz* - OP42ARC/883 MIL vu NULL 0.75 OP42EJ OP42EZ =~ - - IND v- (CASE) 1.5 OP42FJ OP42Fz ~ - - IND 5.0 - - OP42GP OPp42Gs - XIND TO-99 ; : , (J-Suffix) * For devices processed in total compliance to MIL-STD-883, add /883 after part 20-CONTACT LCC number. Consult factory for 883 data sheet. RC-Suffix) t Burn-in is available on commercial and industrial temperature range parts in ( 8-PIN CERDIP cerdip, plastic dip, and TO-can packages. Zz Suffix) GENERAL DESCRIPTION eng -Suffix The OP-42 is a fast precision JFET-input operational amplifier. ( ) Similar in speed to the OP-17, the OP-42 offers a symmetric 8-PINSO (S-Suffix) SIMPLIFIED SCHEMATIC O vt +IN O }++ pW Vout +__~nw$_4 a NULL NULLOP-42 GENERAL DESCRIPTION Continued common-mode rejection of 88dB minimum over a +11V input voltage range is exceptional for a high-speed amplifier. High CMR combined with a minimum 500V/mV gain into 10kQ load ensure excellentlinearity in both noninverting and inverting gain configurations. The low input bias and offset currents provided by the JFET input stage suit the OP-42 for use in high-speed sample and hold circuits, peak detectors, and log amplifiers. Excellent radiation hardness characteristics make the OP-42 ideal for military and aerospace applications. The OP-42 conforms to the standard 741 pinout with nulling to V. The OP-42 upgrades the performance of circuits using the AD544, AD611, AD711, and LF400 by direct replacement. In circuits without nulling, the OP-42 offers an upgrade for designs using the OP-16, OP-17, LT1022, LT1056, and HA2510. ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage 0.0.0... eee eee eee eee cere eree ee ee eeenieenaeee +20V Input Voltage (Note 2) oo... eee ee errr rretnareniee +20V Differential Input Voltage (Note 2) oo. ieeeseeeteeereteetees 40V Output Short-Circuit Duration Indefined Storage Temperature Range... 65C to +175C Operating Temperature Range OP42A (J, Z) voc ciesecsseeseeeeeeeereneneesearserenesees 55C to +125C OP42E, F (J, Z) cceeeeeeeeeereeteerecneeeseseeteeenee ~25C to +86C OP4QG oot ceceee cee senseeeeeecaeetaeaeeenanena 40C to +85C Junction Temperature 65C to +176C Lead Temperature Range (Soldering, 60 sec.) ........... 4+300C PACKAGE TYPE , ,(NOTE 3) 8.5 UNITS TO-99 (J) 150 18 C/W 8-Pin Hermetic DIP (Z) 148 16 C 8-Pin Plastic DIP (P) 103 43 C 20-Contact LCC (RC,TC) 98 38 Chw 8-Pin SO (8) 158 43 C/W NOTES: 1. Absolute maximum ratings apply to both DICE and packaged parts, uniess otherwise noted. 2. For supply voltages less than +20V, the absolute maximum input voltage is equal to the supply voltage. 3. @, is specified for worst case mounting conditions, i.e., @,, is specified for dvice in socket for TO, CERDIP, P-DIP, and LCC packages; Bin is specified for device soldered to printed circuit board for SO package. ELECTRICAL CHARACTERISTICS at V, = +15V, T, = +25C, unless otherwise noted. OP-42E OP-42F OP-42G PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Offset Voltage Vos : - 0.3 0.75 - 0.4 1.5 - 15 5.0 mV Input Bias Current lp Vou = OV Tj = 25C ~ 80 200 - 4130 250 - 130 250 pA Input Offset Current log Vom =0V 7; = 25C - 4 40 - 6 50 - 6 50 pA +12.5 412.5 412.5 Input Voltage Range IVR (Note 1) #11 120 - +11 12.0 - +11 12.0 Vv Gommon-Mode CMR Vay eatl 88 98 - 80 92 - 80 32 - dB Rejection CM Power-Supply V5 =2+10V - 4 - 12 50 - 12 50 VN Rejection Ratio PSAR to +20V 8 0 X R, = 10kQ 500 900 - 500 900 - 500 300 - Si L = Large ional vo Ay = 2ka claraiees 200-260 - 200 260 - 200 260 - vim ontage ain Ro=1kQ 1" 100-170 - 100 170 - 100 170 - Output Voltage 412.5 412.5 412.5 = - +11, - 11.5 ~_ Vv Swing Vo Ry = 18 e158 i419 15 _i19 * -11.9 Short-Circuit Output Shorted +33 +33 +33 + * 20 60 mA Current Limit Isc to Ground #200 pg 780 #200 pg 260 * -28 * No Load = - ~ 1 - 51 6.5 mA Supply Current Isy Vo =0V 5.1 6.0 5 6.5 Slew Rate SR 50 58 - 40 50 - 40 50 - Vius Full-Power 7 900 - 600 800 - 600 800 - kHz Bandwidth BW, (Note 2) 50 Gain-Bandwidth GBW f, = 10kHz - 10 - - 10 - - 10 - MHz Product . 10V Step 0.01% ing - -~ 0. 1.0 ~ 0.9 1.2 - 0.9 1.2 s Settling -Time t, (Note 3) 8 B Overload Recovery - 700 - ~ 700 _ = 700 - ns Time on Phase Margin $5 Odb Gain - 47 - - 47 - - 47 - degrees . . 180 Open-Loop - - - 9 - - 9 - dB Gain Margin Aigo Phase Shift 9 Capacitive Load Unity-Gain Stable 1 300 - 100 300 - 100 300 = F Drive Capability oy (Note 4) 90 pOP-42 ELECTRICAL CHARACTERISTICS at V, = #15V, T, = +25C, unless otherwise noted. Continued OP-42E OP-42F OP-42G PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Differential Input 12 +2 12 impedance Zn 10'7\|6 - - 1076 - - 10'*\|6 - Q||pF Open-Loop Output Resistance ~ 50 ~ ~ 50 ~ ~ so ~ a Voltage Noise e, p-p 0.1Hz to 10Hz - 2 - ~ 2 - - 2 - BV op fy = 10Hz ~ 38 - - 38 - - 38 - Voltage Noise f,, = 100Hz - 16 - - 16 - - 16 - oO W/| Density en fo = 1kHz - 13 ~ - 13 - - 43 _ nVVH2 fy = 10kHz - 12 - - 12 - - 12 - Current Noise i f, = 1kH 0.007 0.007 0.007 AWA Density h 9 = lKi2 ~ * ~ ~ * ~ ~ * - P z External V os = - - - _ - - Trim Range Foot = 20k 4 4 4 mv Long-Term Vog Drift - 5 - - 5 - - 5 - pV/month Supply Voltage Range Vs +8 +15 +20 +8 #15 +20 +8 +15 +20 Vv NOTES: 3. Settling-time is sample tested for A and E grades. Test circuit is shown in 1. Guaranteed by CMR test. Figure 4. Settling-time for F grade is guaranteed but not tested. 2. Guaranteed by slew-rate test and formula BW, = SR/(2n10V5 6a ,)- 4. Guaranteed but not tested. ELECTRICAL CHARACTERISTICS at Vg = #15V, T, = +25C, unless otherwise noted. OP-42A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Offset Voltage Vos - 03 1.0 mv Input Bias Current lp Vom = OV T; = 25C - 80 200 pA Input Offset Current los Vom =0V Tj = 25C = 4 40 pA 12.5 Input Voltage Range IVR (Note 1) #11 * 120 - Vv Common-Mode = 96 - dB Rejection CMR Vom = 2t1V 86 Power-Supply Vg = #10V _ 9 40 NV, Rejection Ratio PSAR to +20V uN R, = 10kQ 500 900 - -Si L = onsge wan AL =tka |) 100 170 - Output Voltage _ 412.5 _ Vv Swing Vo R, = 1k #115 419 Short-Circuit Output Shorted +33 mA Current Limit 's to Ground #20 ~28 +60 No Load Supply Current Ioy Vo =OV - 6.1 6.0 mA Slew Rate SR 45 52 - V/ps Full-Power 700 850 ~ kHz Bandwidth BW, (Note 2) Gain-Bandwidth GBW . = 10kHz _ 10 - MHz Product 9 . . 10V Step 0.01% - - F 1.0 s Settling -Time i, (Note 3) 0.8 Overload Recovery t _ 700 _ ns Time OR Phase Margin %, Odb Gain - 47 ~ degreesOP-42 ELECTRICAL CHARACTERISTICS at V, = #15V, T, = 25C, unless otherwise noted. Continued OP-42A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS : . 180 Open-Loop Gain Margin Aigo Phase Shift - 9 - dB Capacitive Load Unity-Gain Stable . AAA Drive Capability C (Note 4) 100 300 ~ pF Differential Input 12 impedance Zin ~ tor'lls ~ QtIpF Open-Loop Output Resistance Ro ~ 50 ~ 2 Voltage Noise en p-p 0.1Hz to 10Hz - 2 - BV op fo = 10Hz - 38 _ Voltage Noise fg = 100Hz ~ 16 - re Density n fg = 1kHz - 43 - nvivHz fo = 10kHz ~ 12 - Current Noise . % Density i, fy = 1kHz - 0.007 - pAh/Hz External V os - - Trim Range Root = 20kQ 4 mv Long-Term . - 5 - uV/month Vag Drift Supply Voltage Range Vs +8 #15 #20 Vv NOTES: 1. Guaranteed by CMR test. 2. Guaranteed by slew-rate test and formula BW, = SR/(2n10V, PEAK): 3. Settling-time is sample tested for A and E grades. Test circuit is shown in Figure 4. Settling-time for F grade is guaranteed but not tested. 4. Guaranteed but not tested. ELECTRICAL CHARACTERISTICS at Vg = #15V, -25C < T, = 85C for E/F grades, and -40C < T, = +85C for G grade, unless otherwise noted. OP-42E OP.~42F OP-42G PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Offset Voltage Vos - 0.4 1.2 - 0.6 2.5 - 2.0 6.0 mV Offset Voltage Temperature TWVo5 = 4 10 - 8 - - 8 - pve Coefficient Input Bias Current 'n (Note 1) - 0.5 1.2 - 0.6 2.0 - 0.6 2.0 nA Input Offset Current Ig s (Note 1) - 0.05 0.2 - 0.06 0.4 - 0.06 0.4 nA 412.5 412.5 +12.5 Input Voltage Range IVR (Note 2) 211 -120 - #11 -12.0 - +11 12.0 - Vv Common-Made CMA Voy =ettV 86 96 - 80 4 go | 94 - dB Rejection CM Power-Supply Vg =210V Rejection Ratio PSAR tg #20V 2 40 6 50 6 80 wvv Large-Signal A RL = 10kQ (Note 1) 200 500 - 200 500 - 200 500 - VimV Voltage Gain vo RL = 2kQ Vo =+10V 100 160 - 100 160 - 100 160 - Output Voltage 412.3 412.3 412.3 = . - . - . ~ Vv Swing Vo R, 2kg2 211.0 118 114.0 -118 211.0 118 Short-Circuit Output Shorted - - - mA Current Limit Isc to Ground +8 +60 +8 +60 +8 +60 No Load Supply Current Igy Vo = 0V - 5.1 6.0 -~ 5.1 6.5 - 5.1 6.5 mA Slew Rate SR R, = 2kQ 45 57 - 40 50 - 40 50 - V/us Capacitive Load Cc, Unity-Gain Stable 400 250 _ 400 250 _ 100 250 _ pF Drive Capability (Note 3) NOTES: 1. T; = 85C for E/F/G Grades; T, = 125C for Agrade. 2. Guaranteed by CMR test. 3. Guaranteed but not tested.OP-42 ELECTRICAL CHARACTERISTICS at V, = +15V, -55C = T, < 125C for A grade, unless otherwise noted. OP-42A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Offset Voltage Vas - 0.5 2.0 mV Offset Voltage Temperature TCVo5 - 4 10 pvc Coefficient Input Bias Current \5 (Note 1) - 6 20 nA Input Offset Current los (Note 1) - 0.2 1.0 nA Input Voltage Range IVR (Note 2) #11 4 oo - Vv Common-Mode = - dB Rejection CMR Vomettiv 80 94 Power-Supply Vg = +10V - Vv, Rejection Ratio PSRR to 220V 10 50 wVN Large-Signat R, = 10kQ (Note 1) 160 350 - Vimv Voltage Gain vo R,=2k2 Vp =210V 80 110 - im Output Voltage #12.3 = . - Vv Swing Vo R, = 2kQ #11.0 418 Short-Circuit Output Shorted - A Current Limit gc to Ground +8 #60 m No Load Supply Current Igy Vo =0V - 5.1 6.0 mA Slew Rate SR R, = 2k 40 52 - Vius Capacitive Load c Unity-Gain Stable 100 250 _ pF Drive Capability (Note 3) NOTES: 1. T, = 85C for E/F Grades; 7 = 125C for A grade. 2. Guaranteed by CMR test. 3. Guaranteed but not tested.OP-42 DICE CHARACTERISTICS DIE SIZE 0.098 x 0.070 inch, 6860 sq. mils (2.49 < 1.78 mm, 4.43 sq. mm) 1. OFFSET VOLTAGE NULL 2. INVERTING INPUT 3. NONINVERTING INPUT 4. NEGATIVE SUPPLY 5. OFFSET VOLTAGE NULL 6. AMPLIFIER OUTPUT 7, POSITIVE SUPPLY WAFER TEST LIMITS at Vs = +15V, Tj = 25C, unless otherwise noted. OP-42N PARAMETER SYMBOL CONDITIONS LIMIT UNITS Offset Voltage Vos 1.5 mv MAX Input Bias Current i) Vom = OV 250 pA MAX Input Offset Current los Vom = OV 50 pA MAX Input Voltage Range IVR (Note 1) 211 V MIN Common-Mode Rejection CMR Vom = +11V 80 dB MIN P. -S } ower e PRY PSRR Vg = +10V to +20V 50 uV/V MAX Rejection Ratio , RL = 10k 500 Lu = I vols Sere Ayo Ry = 2k 200 V/mV MIN g R, =1k0 100 Output Voltage Swing Vo Rp= 1k +115 V MIN hort-Circui t Short Circuit Isc Output Shorted +20/+60 mA MIN/MAX Current Limit to Ground No Load I} t I 6.5 A MAX Supply Curren SY Vo = OV m Slew Rate SR 40 V/us MIN os ae ai \ Capacitive Load OL Unity-Gain Stable 100 pF MIN Drive Capability (Note 2) NOTES: 1. Guaranteed by CMR test. 2. Guaranteed but not tested. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. BURN-IN CIRCUIT 10k0OP-42 TYPICAL PERFORMANCE CHARACTERIS OPEN-LOOP GAIN, PHASE vs FREQUENCY = & o = y > = o o oy = 47 a o oi ae Ny oS 55 180 (saau5aqd) aSvHd A = 10dB OPEN-LOOP GAIN (dB) 2 s x So COMMON-MODE REJECTION (dB) | a o 1 a Wk 100k 1M FREQUENCY (Hz) 1oM 100M SLEW RATE vs TICS COMMON-MODE REJECTION vs FREQUENCY 120 Ta = 25C 410 | s = 415V ae S oS o o 80 70 60 50 10 100 1k 10k FREQUENCY (Hz) 100k 1M SLEW RATE vs DIFFERENTIAL TEMPERATURE INPUT VOLTAGE 64 60 TT Vg = +15V Ta = 25C 8 R, = 2kO Vg = +18V a 50 Ry =2kn "A 60 | @ 58 @ 40 A 2 s A Ww 56 a 5 E 3a A = 54 x z 52 a 20 7 50 / 7) 7 48 46 0 -75 -50 -25 0 2 50 75 100 125 0 0.2 0.4 0.6 0.8 1.0 TEMPERATURE (C) DIFFERENTIAL INPUT VOLTAGE (VOLTS) SETTLING-TIME DISTORTION vs STEP SIZE vs FREQUENCY 1 Ta = 25C Ta = 25C Vg = 15V Vg = HI5V ~ Ave. =+1 Vo = 0V,p a Ry. = 10ko 3 L = 0.01% eg oo. we z 6 8 & & 2 Ayo = +100 E 4 2 9 0.01 5 0.01% 0.001 0 200 400 600 800 100 1k 10k 100k SETTLING-TIME (ns) FREQUENCY (Hz) POWER-SUPPLY REJECTION (dB) DEVIATION FROM NOMINAL VALUE (%)} CLOSED-LOOP GAIN (dB) POWER-SUPPLY REJECTION vs FREQUENCY 120 a S a a So a o PS s Ny o 10 100 1k 10k FREQUENCY (Hz) 100k 1M SLEW RATE vs CAPACITIVE LOAD Ta= 25C V5 = 15 Ry = 2k0 NEGATIVE 1 n POSITIVE b 1 a l = a 0 100 200 300 CAPACITIVE LOAD (pF) 400 CLOSED-LOOP GAIN vs FREQUENCY st Ta = 26C Vg =+15V D So a Aver = +100 S w& o Aver =+10 nN 3 Avet = +5 = a AvcL=tt I = o I nN i w o 10k 100k 1M FREQUENCY (Hz) 10 100 tk 10M 100NOP-42 TYPICAL PERFORMANCE CHARACTERISTICS IMPEDANCE (0) OUTPUT SWING (Vp, ) NUMBER OF UNITS 30 25 IX] = a = o 0 ~1.0 -0.8 -0.6 -0.4 -0.2 CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY Ta = 25C Vg = +15V Aver = +10 = +100 100 1k 10k 100k IM 10M FREQUENCY (Hz) OUTPUT SWING vs LOAD RESISTANCE T TORT TRIE Tq = 25C Vg = +15V - Ave. = +1 fo = 1kHz 1% DISTORTION MT a (at 10 100 1k 10k LOAD RESISTANCE (2) TYPICAL DISTRIBUTION OF INPUT OFFSET VOLTAGE Ta = 25C Vg = +15V 0 1020 UNITS FROM 3 RUNS 0.2 04 06 0.8 1.0 INPUT OFFSET VOLTAGE (mv) MAXIMUM SWING (V,,_,) SUPPLY CURRENT (mA) NUMBER OF UNITS MAXIMUM OUTPUT SWING vs FREQUENCY % Tm 11M MAXIMUM SWING 25 20 5 \ 1% DISTORTION LEVEL \ 10 \ Ta = 25C \ \ 5 L_Vs = +15V \ Ave. = +1 \ Ms Ry = 10k NAL 0 LL tk 10k 100k 1M 10M FREQUENCY (Hz) SUPPLY CURRENT vs TEMPERATURE 6.0 Vg = 15V 5.8 NO LOAD 5.6 5.4 5.2 5.0 4.8 4.6 44 - -50 -25 0 25 650 TEMPERATURE (C) ris) 10000125 TYPICAL DISTRIBUTION OF TCVo5 Vg = H15V 300 UNITS FROM 3 RUNS 6 8 10 12 14 TCVo5 (uV/C) 6 618 20 OVERSHOOT (%) SUPPLY CURRENT (mA) DEVIATION FROM FINAL VALUE (uV) 90 80 70 60 50 40 30 20 SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE Vg = +15V Rp = 2kn Vin = 100mv,,, | | NEGATIVE EDGE Pat Aver = +1 SAD Le A. =+1 POSITIVE EDGE | | L /) SL Aye. = 15 - _ 2 | Aver =+10-4 400 200 300 400 500 LOAD CAPACITANCE (pF) SUPPLY CURRENT vs SUPPLY VOLTAGE 500 - o oS 300 200 100 +8 +12 SUPPLY VOLTAGE OFFSET VO +20 +16 (VOLTS) LTAGE WARM-UP DRIFT Vg = +15V T INS NSN i eee! 1 2 3 4 5 TIME AFTER POWER APPLIED (MINUTES)OP-42 TYPICAL PERFORMANCE CHARACTERISTICS BIAS CURRENT (pA) OFFSET CURRENT (pA) 10 = S 2 = So 6 a 2 10 BIAS CURRENT vs JUNCTION TEMPERATURE Vg = +15V = Voy = OV ~75 -50 ~-25 0 25 50 75 1000 100 1 -75 JUNCTION TEMPERATURE (C) 100 OFFSET CURRENT vs JUNCTION TEMPERATURE Vg = +15V -50 -25 0 25 50 75 JUNCTION TEMPERATURE (C) 100 125 125 BIAS CURRENT (pA) OPEN-LOOP GAIN (V/mV) Hz ) VOLTAGE NOISE DENSITY (nvV/ 700 600 500 400 300 200 100 BIAS CURRENT vs COMMON-MODE VOLTAGE Vg = H15V Ty= 25C -10 ~5 QO 5 10 15 COMMON-MODE VOLTAGE (VOLTS) OPEN-LOOP GAIN vs JUNCTION TEMPERATURE Vg = ua R,=2ko _| hy NN N ~N\ | Q -75 -50 -25 0 25 50 75 100 125 JUNCTION TEMPERATURE (C) VOLTAGE NOISE DENSITY vs FREQUENCY Ty = 25C Vg = 415 10 100 1k 40k FREQUENCY (Hz) BIAS CURRENT WARM-UP DRIFT Vg = 415V Ty = 25C INPUT BIAS CURRENT (pA) 0 2 4 6 8 10 12 TIME AFTER POWER APPLIED (MINUTES) SHORT CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE Vg=+ SHORT CIRCUIT OUTPUT CURRENT (mA) 5 -7% -50 -25 Q 25 50 75 100 86125 JUNCTION TEMPERATURE (C)OP-42 APPLICATIONS INFORMATION The OP-42 combines speed with a high level of input preci- sion usually found only with slower devices. Weli-behaved AC performance in the form of clean transient response, symmetrical slew-rates and a high degree of forgiveness to supply decoupling are the hallmarks of this amplifier. AC gain and phase response are quite independent of tempera- ture or supply voltage. Figure 1 shows the OP-42s small- signal response. Even with 75pF loads, there is minimal ring- ing in the output waveform. Large-signal response is shown in Figure 2. This figure clearly shows the OP-42s exception- ally close matching between positive and negative slew- rates. Slew-rate symmetry decreases the DC offset a system encounters when processing high-frequency signals, and thus reduces the DC current necessary for load driving. FIGURE 1: Small-Signal Transient Response, Z, = 2kQ||75pF FIGURE 2: Large-Signal Transient Response, Z, = 2k0||75pF As with most JFET-input amplifiers, the output of the OP-42 may undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion will not dam- age the amplifier, nor will it cause an internal latch-up. Supply decoupling should be used to overcome inductance and resistance associated with supply lines to the amplifier. For most applications a 0.1uF to 0.01uF capacitor should be placed between each supply pin and ground. The OP-42 displays excellent resistance to radiation. Radia- tion hardness data is available by contacting the factory. OFFSET VOLTAGE ADJUSTMENT Offset voltage is adjusted with a 10k to 100kN potentiome- ter as shown in Figure 3. The potentiometer should be con- nected between pins 1 and 5 with its wiper connected to the V- supply. Nulling Vagin this manner changes TCVog by no more than 5zV/C per millivolt of Vog change. Alternately, ~Vog may be nulled by attaching the potentiometer wiper -10- through a 1M0QO resistor to the positive supply rail. FIGURE 3: Input Offset Voltage Nuiling v- ALTERNATE METHOD ve STANDARD METHOD NOTE: Vog CAN BE TRIMMED WITH POTENTIOMETER RANGING FROM 10k0 TO 100k0. SETTLING-TIME Guaranteed fast-settling is assured by sample-testing during production. The OP-42 is configured as a unity-gain follower in the test circuit of Figure 4. This test method has advan- tages over false-sum-node techniques in that the actual out- put of the amplifier is measured, instead of an error-voltage at the sum node. Common-mode settling effects are exercised in this circuit, in addition to the slew-rate and bandwidth effects measured by the false-sum-node method. A reason- ably flat-top pulse is required as a stimulus. The output waveform of the OP-42 being tested is clamped by Schottky diodes and buffered by the JFET source- follower. The signal is amplified by a factor of ten by the fast amplifier IC1, then Schottky-clamped before being output. The OP-41 provides overall offset nulling. Analysis of the waveform using a digitizing oscilloscope determines the op amps settling-time.OP-42 FIGURE 4: Settling-Time Test Fixture DAC OUTPUT AMPLIFIER The OP-42 is an excellent choice for a DAC output amplifier, since its high speed and fast settling-time allow quick transi- tions between codes, even for full-scale changes in output level. The DAC output capacitance appears at the opera- tional amplifier inputs, and must be compensated to ensure -11- 16-20V |i- +15V t|-+4 aK OUTPUT 0.41uF (TO SCOPE) N+ + R, DUT 2N4416 _ 4 1kQ, v D1 D2 0.1 nF 1 VT + he | R (INTERNAL) toKo. Ic2 16-20V 1G AD VW vv + +5V "h 2220 Jb 2N2222A 7500 1N4148 S 15k0 vw SCHOTTKY DIODES D1-D4 ARE HEWLETT-PACKARD HP5082-2835 iC1 1S COMLINEAR CLC200A1 1C2 IS PME OP41EU Vv FIGURE 5: OP-42 Settling-Characteristics optimal settling speed. Compensation is achieved with ca- pacitor C in Figure 6. C must be adjusted to account for the TTT TT TTT TTT TTT TTT DACs output capacitance, the op amps input capacitance, LE POSITIVE EDGE 4 and any stray capacitance at the inputs. With a bipolar DAC, E 4 an additional shunt resistor may be used to optimize E 0.01%ERRORBAND 4 response. This technique is described in PMIs application ' note AN-24. Pops Io yo0ne Tosa srs ans rns ses csaas 7 FIGURE 6: DAC Output Amplifier Circuit E 1s q a Cc : 7 _ ' 4 Ag CE : 4 MW pe 0 tus 2us 2.5yus = a E NEGATIVE EDGE 4 E 4 \__ E 0.01% ERROR BAND 7 E PE I 4 ' E | J pO Fe NOTE: R- IS INTERNAL TO MOST CMOS DACs c | tg= 740ns 4 tC | q a | 4 Ei po Highest speed is achieved using bipolar DACs such as PMIs ts Pus 2.5us DAC-08, DAC-10 or DAC-312. The output capacitances of these converters are up to an order of magnitude lower than their CMOS counterparts, resulting in substantially faster settling-times. The high output impedance of bipolar DACs allows the output amplifier to operate in a true current-to- voltage mode, with a noise gain of unity, thereby retaining the amplifiers full bandwidth. Offset voltage has minimal effect on linearity with bipolar converters. CMOS digital-to-analog converters have higher output ca- pacitances and lower output resistances than bipolar DACs.OP-42 This results in slower settling-times, higher sensitivity to offset voltages and a reduction in the output amplifiers bandwidth. These trade-offs must be balanced against the CMOS DACs advantages in terms of interfacing capability, power dissipation, accuracy levels and cost. Using the inter- nal feedback resistor which is present on most CMOS con- verters, the gain applied to offset voltage varies between 4/3 and 2, depending upon output code. Contributions to linear- ity error will be as much as 2/3V gg. In a 10-volt 12-bit system, this may add up to an additional 1/5LSB DNL with the OP-42E. Amplifier bandwidth is reduced by the same gain factor applied to offset voltage, however the OP-42s 10MHz gain- bandwidth product results in no reduction of the CMOS con- verters multiplying bandwidth. Individual DAC data-sheets should be consulted for more complete descriptions of the converters and their circuit applications. FIGURE 7: DAC Output Amplifier Response (PM-7545 DAC) 0.1uF capacitor. Compensation for the OP-42s input capac- itance is provided by Cc. The circuit may be operated at any gain, in the usual op amp configurations. FIGURE 8: High-Current Output Buffer +15V 2N5114 2N4919 AvcL = 1+ Rp/Re R1 AND R2 ARE 1-60, SEE TEXT. DRIVING A HIGH-SPEED ADC The OP-42s open-loop output resistance is approximately 500. When feedback is applied around the amplifier, output resistance decreases in proportion to open-loop gain divided by closed-loop gain (Ayo./Avc.). Output impedance in- creases as open-loop gain roils-off with frequency. High- speed analog-to-digital converters require low source impe- dances at high frequency. Output impedance at 1MHz is typically 50 for an OP-42 operating at unity-gain. If lower output impedances are required, an output buffer may be placed at the output of the OP-42. HIGH-CURRENT OUTPUT BUFFER The circuit in Figure 8 shows a high-current output stage for the OP-42. Output current is limited by R1 and R2. For good tracking between the output transistors Q1, Q2 and their biasing diodes D1 and D2, thermal contact must be main- tained between the transistor and its associated diode. If good thermal contact is not maintained, R1 and R2 must be increased to 5-62 in order to prevent thermal runaway. Using 50, resistors, the circuit easily drives a 750 load (Figure 9). Output resistance is decreased and heavier loads may be driven by decreasing R1 and R2. Base current and biasing for Q1 and Q2 are provided by two current sources, the MAT-02 and the JFET. The 2kQ potenti- ometer in the JFET current source should be trimmed for optimum transient performance. The case of the MAT-02 should be connected to V-, and decoupled to ground with a -12- FIGURE 9: Output Buffer Large-Signal Response DRIVING CAPACITIVE LOADS Best performance wiil always be achieved by minimizing input and load capacitances around any high-speed ampli- fier. However, the OP-42 is guaranteed capable of driving a 100pF capacitive toad over its full operating temperature range while operating at any gain including unity. Typically, an OP-42 will drive more than 250pF at any temperature. Supply decoupling does affect capacitive load driving ability. Extra care should be given to ensure good decoupling when driving capacitive loads, and a larger decoupling capacitor between 1uF and 10uF should be placed in parallel with the usual decoupling capacitor on each supply.OP-42 Large capacitive loads may be driven utilizing the circuit shown in Figure 10. R1 and C1 introduce a small amount of feedforward compensation around the amplifier to counter- act the phase lag induced by the output impedance and load capacitance. At DC and low frequencies, R1 is contained within the feedback loop. At higher frequencies, feedforward compensation becomes increasingly dominant, and R1s effect on output impedance will become more noticeable. When driving very large capacitances, slew-rate will be limited by the short-circuit current limit. Although the un- loaded slew-rate is insensitive to variations in temperature, the output current limit has a negative temperature coeffi- cient, and is asymmetrical with regards to sourcing and sink- ing current. Therefore, slew-rate into excessive capacities will decrease with increasing temperature, and will lose symmetry. COMPUTER SIMULATIONS Many electronic design and analysis programs include mod- els for op amps which calculate AC performance from the location of poles and zeros. As an aid to designers utilizing such a program, major poles and zeros of the OP-42 are listed below. Their location will vary slightly between production lots. Typically, they will be within +15% of the frequency listed. Use of this data will enable the designer to evaluate gross circuit performance quickly, but should not supplant rigorous characterization of a breadboarded circuit. POLES ZEROS 20Hz 1MHz 800kHz 3MHz FIGURE 11: OP-41 Servo Amplifier Provides Offset Correction FIGURE 10: Compensation for Large Capacitive Loads VA4 Vout 100 10nF ZL 2kn AUTOZEROING OFFSET VOLTAGE Figure 11 describes a circuit for automatic offset voltage and drift correction. The OP-41 is used in aservo loop to force the OP-42 output equal to the OP-41s offset voltage. Thus, the OP-42s effective input offset is held below 10unV (1MV/AycL = 100) despite any temperature variations. This circuit will be most advantageous in high-gain applications. Feedback is accomplished using the OP-42s null pins, leav- ing both inputs free for other purposes. In the application Int OJ IN2z O4 Ings O-~ IN4 OJ Ins O IN6 OJ IN7 O-_+ INS MUX-08 ENABLE O! A10 A20 A3O 1N4148 ALL LINES HIGH TO ZERO OFFSETS 2N2907A Vour Jq 2N4118 5000pF 40K0 2N2369OP-42 shown, the OP-42 has seven multiplexed inputs, while the eighth input provides a ground reference. Nulling is accomp- lished by addressing the grounded channel. This address should be held for at least 200us. After this time, the address may be changed to another channel. The MUX-08 ENABLE pin must be high during the entire nulling cycle. During this time, JFET switch J1 turns on, completing feedback around -14- the OP-41 servo amplifier. A charge is developed across Cy to compensate for the OP-42s offset voltage. When another channel is addressed, J1 turns off, and the correction charge is maintained across Cy by the OP-41. Droop is exceptionally low only 1.3uV/s at 25C. A correction range of more than 4mV allows nulling of minor system offsets as well as the OP-42s offset voltage.