Contents
Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide..............................................3
Introduction................................................................................................................ 3
Installing and Licensing Intel FPGA IP Cores........................................................... 4
On-Chip Debugging Tool Suite.............................................................................. 4
Applications of the Virtual JTAG IP Core................................................................. 5
JTAG Protocol..................................................................................................... 6
JTAG Circuitry Architecture...................................................................................7
System-Level Debugging Infrastructure.......................................................................... 9
Transaction Model of the SLD Infrastructure............................................................9
SLD Hub Finite State Machine............................................................................. 11
Virtual JTAG Interface Description.................................................................................12
Input Ports.......................................................................................................14
Output Ports.....................................................................................................14
Parameters.......................................................................................................16
Design Flow of the Virtual JTAG IP Core................................................................16
Simulation Model.............................................................................................. 17
Run-Time Communication...................................................................................18
Running a DR Shift Operation Through a Virtual JTAG Chain....................................19
Run-Time Communication............................................................................................19
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values................. 21
Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values......................22
Reset Considerations when Using a Custom JTAG Controller.................................... 23
Instantiating the Virtual JTAG IP Core........................................................................... 24
IP Catalog and Parameter Editor..........................................................................24
Specifying IP Core Parameters and Options...........................................................26
Instantiating Directly in HDL............................................................................... 27
Simulation Support.....................................................................................................29
Compiling the Design..................................................................................................32
Third-Party Synthesis Support.............................................................................33
SLD_NODE Discovery and Enumeration......................................................................... 33
Issuing the HUB_INFO Instruction....................................................................... 34
HUB IP Configuration Register.............................................................................35
SLD_NODE Info Register.................................................................................... 35
Capturing the Virtual IR Instruction Register.................................................................. 36
AHDL Function Prototype ............................................................................................37
VHDL Component Declaration...................................................................................... 38
VHDL LIBRARY-USE Declaration....................................................................................38
Design Example: TAP Controller State Machine...............................................................39
Design Example: Modifying the DCFIFO Contents at Runtime........................................... 41
Write Logic.......................................................................................................41
Read Logic....................................................................................................... 42
Runtime Communication.................................................................................... 43
Design Example: Offloading Hardwired Revision Information............................................ 44
Configuring the JTAG User Code Setting............................................................... 45
Document Revision History for the Virtual JTAG (altera_virtual_jtag) IP Core User Guide......45
Contents
Virtual JTAG (altera_virtual_jtag) IP Core User Guide
2
Altera Virtual JTAG (altera_virtual_jtag) IP Core User
Guide
The Altera Virtual JTAG (altera_virtual_jtag) IP core provides access to the PLD source
through the JTAG interface. This IP core is optimized for Intel® device architectures.
Using IP cores in place of coding your own logic saves valuable design time, and offers
more efficient logic synthesis and device implementation. You can scale the IP core's
size by setting parameters.
Related Information
Introduction to Intel FPGA IP Cores
Introduction
The Virtual JTAG IP core allows you to create your own software solution for
monitoring, updating, and debugging designs through the JTAG port without using I/O
pins on the device, and is one feature in the On-Chip Debugging Tool Suite. The Intel
Quartus® Prime software or JTAG control host identifies each instance of this IP core
by a unique index. Each IP core instance functions in a flow that resembles the JTAG
operation of a device. The logic that uses this interface must maintain the continuity of
the JTAG chain on behalf the PLD device when this instance becomes active.
With the Virtual JTAG IP core you can build your design for efficient, fast, and
productive debugging solutions. Debugging solutions can be part of an evaluation test
where you use other logic analyzers to debug your design, or as part of a production
test where you do not have a host running an embedded logic analyzer. In addition to
debugging features, you can use the Virtual JTAG IP core to provide a single channel
or multiple serial channels through the JTAG port of the device. You can use serial
channels in applications to capture data or to force data to various parts of your logic.
Each feature in the On-Chip Debugging Tool Suite leverages on-chip resources to
achieve real time visibility to the logic under test. During runtime, each tool shares the
JTAG connection to transmit collected test data to the Intel Quartus Prime software for
analysis. The tool set consists of a set of GUIs, IP core intellectual property (IP) cores,
and Tcl application programming interfaces (APIs). The GUIs provide the configuration
of test signals and the visualization of data captured during debugging. The Tcl
scripting interface provides automation during runtime.
The Virtual JTAG IP core provides you direct access to the JTAG control signals routed
to the FPGA core logic, which gives you a fine granularity of control over the JTAG
resource and opens up the JTAG resource as a general-purpose serial communication
interface. A complete Tcl API is available for sending and receiving transactions into
your device during runtime. Because the JTAG pins are readily accessible during
runtime, this IP core enables an easy way to customize a JTAG scan chain internal to
the device, which you can then use to create debugging applications.
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Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
Examples of debugging applications include induced trigger conditions evaluated by a
Signal Tap logic analyzer by exercising test signals connected to the analyzer instance,
a replacement for a front panel interface during the prototyping phase of the design,
or inserted test vectors for exercising the design under test.
The infrastructure is an extension of the JTAG protocol for use with Intel-specific
applications and user applications, such as the Signal Tap logic analyzer.
Installing and Licensing Intel FPGA IP Cores
The Intel Quartus Prime software installation includes the Intel FPGA IP library. This
library provides many useful IP cores for your production use without the need for an
additional license. Some Intel FPGA IP cores require purchase of a separate license for
production use. The Intel FPGA IP Evaluation Mode allows you to evaluate these
licensed Intel FPGA IP cores in simulation and hardware, before deciding to purchase a
full production IP core license. You only need to purchase a full production license for
licensed Intel IP cores after you complete hardware testing and are ready to use the
IP in production.
The Intel Quartus Prime software installs IP cores in the following locations by default:
Figure 1. IP Core Installation Path
intelFPGA(_pro)
quartus - Contains the Intel Quartus Prime software
ip - Contains the Intel FPGA IP library and third-party IP cores
altera - Contains the Intel FPGA IP library source code
<IP name> - Contains the Intel FPGA IP source files
Table 1. IP Core Installation Locations
Location Software Platform
<drive>:\intelFPGA_pro\quartus\ip\altera Intel Quartus Prime Pro Edition Windows*
<drive>:\intelFPGA\quartus\ip\altera Intel Quartus Prime Standard
Edition
Windows
<home directory>:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition Linux*
<home directory>:/intelFPGA/quartus/ip/altera Intel Quartus Prime Standard
Edition
Linux
On-Chip Debugging Tool Suite
The On-Chip Debugging Tool Suite enables real time verification of a design and
includes the following tools:
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Table 2. On-Chip Debugging Tool Suite
Tool Description Typical Circumstances for Use
Signal Tap Logic
Analyzer
Uses FPGA resources to sample tests nodes
and outputs the information to the Intel
Quartus Prime software for display and
analysis.
You have spare on-chip memory and want functional
verification of your design running in hardware.
Signal Probe Incrementally routes internal signals to I/O
pins while preserving the results from your
last place-and-route.
You have spare I/O pins and want to check the
operation of a small set of control pins using either an
external logic analyzer or an oscilloscope.
Logic Analyzer
Interface (LAI)
Multiplexes a larger set of signals to a
smaller number of spare I/O pins. LAI allows
you to select which signals are switched
onto the I/O pins over a JTAG connection.
You have limited on-chip memory and have a large set
of internal data buses that you want to verify using an
external logic analyzer. Logic analyzer vendors, such as
Tektronics and Agilent, provide integration with the tool
to improve usability.
In-System
Memory
Content Editor
Displays and allows you to edit on-chip
memory.
You want to view and edit the contents of either the
instruction cache or data cache of a Nios® II processor
application.
In-System
Sources and
Probes
Provides a way to drive and sample logic
values to and from internal nodes using the
JTAG interface.
You want to prototype a front panel with virtual
buttons for your FPGA design.
Virtual JTAG
Interface
Opens the JTAG interface so that you can
develop your own custom applications.
You want to generate a large set of test vectors and
send them to your device over the JTAG port to
functionally verify your design running in hardware.
Related Information
System Debugging Tools Overview
Applications of the Virtual JTAG IP Core
You can instantiate single or multiple instances of the Virtual JTAG IP core in your HDL
code. During synthesis, the Intel Quartus Prime software assigns unique IDs to each
instance, so that each instance is accessed individually. You can instantiate up to 128
instances of the Virtual JTAG IP core. The figure below shows a typical application in a
design with multiple instances of the IP core.
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Figure 2. Application Example
Logic
Logic
JTAG
sld_virtual_jtag
sld_virtual_jtag
tck
tms
trst
tdi
tdo
The hub automatically arbitrates between multiple applications that share a single
JTAG resource. Therefore, you can use the IP core in tandem with other on-chip
debugging applications, such as the Signal Tap logic analyzer, to increase debugging
visibility. You can also use the IP core to provide simple stimulus patterns to solicit a
response from the design under test during run-time, including the following
applications:
• To diagnose, sample, and update the values of internal parts of your logic. With
this IP core, you can easily sample and update the values of the internal counters
and state machines in your hardware device.
• To build your own custom software debugging IP using the Tcl commands to debug
your hardware. This IP communicates with the instances of the Virtual JTAG IP
core inside your design.
• To construct your design to achieve virtual inputs and outputs.
• If you are building a debugging solution for a system in which a microprocessor
controls the JTAG chain, you cannot use the Signal Tap logic analyzer because the
JTAG control must be with the microprocessor. You can use low-level controls for
the JTAG port from the Tcl commands to direct microprocessors to communicate
with the Virtual JTAG IP core inside the device core.
JTAG Protocol
The original intent of the JTAG protocol (standardized as IEEE 1149.1) was to simplify
PCB interconnectivity testing during the manufacturing stage. As access to integrated
circuit (IC) pins became more limited due to tighter lead spacing and FPGA packages,
testing through traditional probing techniques, such as “bed-of-nails” test fixtures,
became infeasible. The JTAG protocol alleviates the need for physical access to IC pins
via a shift register chain placed near the I/O ring. This set of registers near the I/O
ring, also known as boundary scan cells (BSCs), samples and forces values out onto
the I/O pins. The BSCs from JTAG-compliant ICs are daisy-chained into a serial-shift
chain and driven via a serial interface.
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During boundary scan testing, software shifts out test data over the serial interface to
the BSCs of select ICs. This test data forces a known pattern to the pins connected to
the affected BSCs. If the adjacent IC at the other end of the PCB trace is
JTAG-compliant, the BSC of the adjacent IC samples the test pattern and feeds the
BSCs back to the software for analysis. The figure below illustrates the boundary-scan
testing concept.
Figure 3. IEEE Std. 1149.1 Boundary-Scan Testing
Serial
Data In
JTAG Device 1 JTAG Device 2
Serial
Data Out
Core
Logic
Core
Logic
Boundary-Scan Cell
IC Pin Signal
Interconnection
to be Tested
Because the JTAG interface shifts in any information to the device, leaves a low
footprint, and is available on all Intel devices, it is considered a general purpose
communication interface. In addition to boundary scan applications, Intel devices use
the JTAG port for other applications, such as device configuration and on-chip
debugging features available in the Intel Quartus Prime software.
Related Information
IEEE 1149.1 JTAG Boundary-Scan Testing
JTAG Circuitry Architecture
The basic architecture of the JTAG circuitry consists of the following components:
•A set of Data Registers (DRs)
•An Instruction Register (IR)
• A state machine to arbitrate data (known as the Test Access Port (TAP) controller)
• A four- or five-pin serial interface, consisting of the following pins:
—Test data in (TDI), used to shift data into the IR and DR shift register chains
—Test data out (TDO), used to shift data out of the IR and DR shift register
chains
—Test mode select (TMS), used as an input into the TAP controller
—TCK, used as the clock source for the JTAG circuitry
—TRST resets the TAP controller. This is an optional input pin defined by the
1149.1 standard.
Note: The TRST pin is not present in the Cyclone device family.
The bank of DRs is the primary data path of the JTAG circuitry. It carries the payload
data for all JTAG transactions. Each DR chain is dedicated to serving a specific
function. Boundary scan cells form the primary DR chain. The other DR chains are
used for identification, bypassing the IC during boundary scan tests, or a custom set
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of register chains with functions defined by the IC vendor. Intel uses two of the DR
chains with user-defined IP that requires the JTAG chain as a communication resource,
such as the on-chip debugging applications. The Virtual JTAG IP core, in particular,
allows you to extend the two DR chains to a user-defined custom application.
You use the instruction register to select the bank of Data Registers to which the TDI
and TDO must connect. It functions as an address register for the bank of Data
Registers. Each IR instruction maps to a specific DR chain.
All shift registers that are a part of the JTAG circuitry (IR and DR register chains) are
composed of two kinds of registers: shift registers, which capture new serial shift
input from the TDI pin, and parallel hold registers, which connect to each shift
register to hold the current input in place when shifting. The parallel hold registers
ensure stability in the output when new data is shifted.
The figure below shows a functional model of the JTAG circuitry. The TRST pin is an
optional pin in the 1149.1 standard and not available in Cyclone devices. The TAP
controller is a hard controller; it is not created using programmable resources. The
major function of the TAP controller is to route test data between the IR and DR
register chains.
Figure 4. Functional Model of the JTAG Circuitry
IR Shift Registers
IR Update Registers
DR Shift Register 1
DR Update Register 1
DR Shift Register 2
DR Update Register 2
DR Shift Register n
DR Update Register n
JTAG TAP
Controller
(2)
TDI TDO
Tap
Controller
Output (3)
Tap
Controller
Output (3)
TRST (1)
TCK
TMS
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System-Level Debugging Infrastructure
On-chip debugging tools that require the JTAG resources share two Data Register
chain paths; USER1 and USER0 instructions select the Data Register chain paths. The
datapaths are an extension of the JTAG circuitry for use with the programmable logic
elements in Intel devices.
Because the JTAG resource is shared among multiple on-chip applications, an
arbitration scheme must define how the USER0 and USER1 scan chains are allocated
between the different applications. The system-level debugging (SLD) infrastructure
defines the signaling convention and the arbitration logic for all programmable logic
applications using a JTAG resource. The figure below shows the SLD infrastructure
architecture.
Figure 5. System Level Debugging Infrastructure Functional Model
JTAG Tap
Controller
TC
TM
TD
TD
FPGA
SLD Node
SLD Node
SLD Node
SLD Node
SLD Hub
User’s Design
(Core Logic)
Transaction Model of the SLD Infrastructure
In the presence of an application that requires the JTAG resource, the Intel Quartus
Prime software automatically implements the SLD infrastructure to handle the
arbitration of the JTAG resource. The communication interface between JTAG and any
IP cores is transparent to the designer. All components of the SLD infrastructure,
except for the JTAG TAP controller, are built using programmable logic resources.
The SLD infrastructure mimics the IR/DR paradigm defined by the JTAG protocol. Each
application implements an Instruction Register, and a set of Data Registers that
operate similarly to the Instruction Register and Data Registers in the JTAG standard.
Note that the Instruction Register and the Data Register banks implemented by each
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application are a subset of the USER1 and USER0 Data Register chains. The SLD
infrastructure consists of three subsystems: the JTAG TAP controller, the SLD hub, and
the SLD nodes.
The SLD hub acts as the arbiter that routes the TDI pin connection between each SLD
node, and is a state machine that mirrors the JTAG TAP controller state machine.
The SLD nodes represent the communication channels for the end applications. Each
instance of IP requiring a JTAG communication resource, such as the Signal Tap logic
analyzer, would have its own communication channel in the form of a SLD node
interface to the SLD hub. Each SLD node instance has its own Instruction Register and
bank of DR chains. Up to 255 SLD nodes can be instantiated, depending on resources
available in your device.
Together, the sld_hub and the SLD nodes form a virtual JTAG scan chain within the
JTAG protocol. It is virtual in the sense that both the Instruction Register and DR
transactions for each SLD node instance are encapsulated within a standard DR scan
shift of the JTAG protocol.
The Instruction Register and Data Registers for the SLD nodes are a subset of the
USER1 and USER0 Data Registers. Because the SLD Node IR/DR register set is not
directly part of the IR/DR register set of the JTAG protocol, the SLD node Instruction
Register and Data Register chains are known as Virtual IR (VIR) and Virtual DR (VDR)
chains. The figure below shows the transaction model of the SLD infrastructure.
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Figure 6. Extension of the JTAG Protocol for PLD Applications
IR Shift Registers
IR Update Registers
DR Shift Register 1
DR Update Register 1
USER 0 Data Registers
USER 1 Data Registers
TDI TDO
TAP
Controller
Output
TAP
Controller
Output
Intel PLD JTAG Extension
Intel PLD JTAG Extension
Node 1
Node N
USER0 / USER1 and
SLD_HUB Control Signals
TDI TDO
VIR
VDR 1
VDR N
VIR
VIR 1
VIR N
SLD Hub Finite State Machine
The SLD hub decodes TMS independently from the hard JTAG TAP controller state
machine and implements an equivalent state machine (called the “SLD hub finite state
machine”) for the internal JTAG path. The SLD hub performs a similar function for the
VIR and VDR chains that the TAP controller performs for the JTAG IR and DR chains. It
enables an SLD node as the active path for the TDI pin, selects the TDI data between
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the VIR and VDR registers, controls the start and stop of any shift transactions, and
controls the data flow between the parallel hold registers and the parallel shift
registers of the VIR and VDR.
Because all shifts to VIR and VDR are encapsulated within a DR shift transaction, an
additional control signal is necessary to select between the VIR and VDR data paths.
The SLD hub uses the USER1 command to select the VIR data path and the USER0
command to select the VDR data path.
This state information, including a bank of enable signals, is forwarded to each of the
SLD nodes. The SLD nodes perform the updates to the VIR and VDR according to the
control states provided by the sld_hub. The SLD nodes are responsible for
maintaining continuity between the TDI and TDO pins.
The figure below shows the SLD hub finite state machine. There is no direct state
signal available to use for application design.
Figure 7. sld_hub Finite State Machine
USR0 USR1
JTAG_Test_Logic_Reset
JTAG_Run_Test_Idle Virtual_Select_DR_Scan (1) Virtual_Select_IR_Scan (1)
Virtual_Capture_DR
Virtual_Shift_DR
Virtual_Exit1_DR
Virtual_Pause_DR
Virtual_Exit2_DR
Virtual_Update_DR
Virtual_Capture_IR
Virtual_Shift_IR (1)
Virtual_Exit1_IR (1)
Virtual_Pause_IR (1)
Virtual_Exit2_IR (1)
Virtual_Update_IR
Virtual JTAG Interface Description
The Virtual JTAG Interface implements an SLD node interface, which provides a
communication interface to the JTAG port. The IP core exposes control signals that are
part of the SLD hub; namely, JTAG port signals, all finite state machine controller
states of the TAP controller, and the SLD hub finite state machine. Additionally, each
instance of the Virtual JTAG IP cores contain the virtual Instruction Register for the
SLD node. Instantiation of this IP core automatically infers the SLD infrastructure, and
one SLD node is added for each instantiation.
The Virtual JTAG IP core provides a port interface that mirrors the actual JTAG ports.
The interface contains the JTAG port pins, a one-hot decoded output of all JTAG states,
and a one-hot decoded output of all the virtual JTAG states. Virtual JTAG states are
the states decoded from the SLD hub finite state machine. The ir_in and ir_out
ports are the parallel input and output to and from the VIR. The VIR ports are used to
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select the active VDR datapath. The JTAG states and TMS output ports are provided for
debugging purposes only. Only the virtual JTAG, TDI, TDO, and the IR signals are
functional elements of the IP core. When configuring this IP core using the parameter
editor, you can hide TMS and the decoded JTAG states.
The figure below shows the input and output ports of the virtual JTAG IP core. The
JTAG TAP controller outputs and TMS signals are used for informational purposes only.
These signals can be exposed using the Create primitive JTAG state signal ports
option in the parameter editor.
Figure 8. Input and Output Ports of the Virtual JTAG IP Core
my_vji
tdo
ir_out[1..0]
tck
tdi
ir_in[1..0]
virtual_state_uir
jtag_state_sdrs
jtag_state_sdr
jtag_state_e1dr
jtag_state_pdr
jtag_state_udr
jtag_state_sirs
jtag_state_cir
jtag_state_sir
jtag_state_e1ir
jtag_state_pir
jtag_state_e2ir
jtag_state_uir
tms
jtag_state_e2dr
jtag_state_cdr
jtag_state_rti
jtag_state_tlr
virtual_state_cir
virtual_state_udr
virtual_state_e2dr
virtual_state_pdr
virtual_state_e1dr
virtual_state_sdr
virtual_state_cdr
Inputs
One-Hot Decoded Outputs
from the SLD Hub FSM
One-Hot Decoded Outputs
from the TAP Controller
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Input Ports
Table 3. Input Ports for the Virtual JTAG IP Core
Port name Required Description Comments
tdo Yes Writes to the TDO pin on the device.
ir_out[] No Virtual JTAG instruction register
output. The value is captured
whenever virtual_state_cir is
high.
Input port [SLD_IR_WIDTH-1..0]
wide. Specify the width of this bus with
the SLD_IR_WIDTH parameter.
Output Ports
Table 4. Output Ports for the Virtual JTAG IP Core
Port Name Required Description Comments
tck Yes JTAG test clock. Connected directly to the TCK device
pin. Shared among all virtual JTAG
instances.
tdi Yes TDI input data on the device. Used
when virtual_state_sdr is high.
Shared among all virtual JTAG
instances.
ir_in[] No Virtual JTAG instruction register data.
The value is available and latched
when virtual_state_uir is high.
Output port [SLD_IR_WIDTH-1..0]
wide. Specify the width of this bus with
the SLD_IR_WIDTH parameter.
Table 5. High-Level Virtual JTAG State Signals
Port Name Required Description Comments
virtual_state_cdr No Indicates that virtual JTAG is in
Capture_DR state.
virtual_state_sdr Yes Indicates that virtual JTAG is in
Shift_DR state.
In this state, this instance is
required to establish the JTAG
chain for this device.
virtual_state_e1dr No Indicates that virtual JTAG is in
Exit1_DR state.
virtual_state pdr No Indicates that virtual JTAG is in
Pause_DR state.
The Intel Quartus Prime software
does not cycle through this state
using the Tcl command.
virtual_state_e2dr No Indicates that virtual JTAG is in
Exit2_DR state.
The Intel Quartus Prime software
does not cycle through this state
using the Tcl command.
virtual_state_udr No Indicates that virtual JTAG is in
Update_DR state.
virtual_state_cir No Indicates that virtual JTAG is in
Capture_IR state.
virtual_state_uir No Indicates that virtual JTAG is in
Update_IR state.
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Table 6. Low-Level Virtual JTAG State Signals
Port Name Required Description Comments
jtag_state_tlr No Indicates that the device JTAG
controller is in the
Test_Logic_Reset state.
Shared among all virtual JTAG
instances.
jtag_state_rti No Indicates that the device JTAG
controller is in the Run_Test/Idle
state.
Shared among all virtual JTAG
instances.
jtag_state_sdrs No Indicates that the device JTAG
controller is in the
Select_DR_Scan state.
Shared among all virtual JTAG
instances.
jtag_state_cdr No Indicates that the device JTAG
controller is in the Capture_DR
state.
Shared among all virtual JTAG
instances.
jtag_state_sdr No Indicates that the device JTAG
controller is in the Shift_DR
state.
Shared among all virtual JTAG
instances.
jtag_state_e1dr No Indicates that the device JTAG
controller is in the Exit1_DR
state.
Shared among all virtual JTAG
instances.
jtag_state_pdr No Indicates that the device JTAG
controller is in the Pause_DR
state.
Shared among all virtual JTAG
instances.
jtag_state_e2dr No Indicates that the device JTAG
controller is in the Exit2_DR
state.
Shared among all virtual JTAG
instances.
jtag_state_udr No Indicates that the device JTAG
controller is in the Update_DR
state.
Shared among all virtual JTAG
instances.
jtag_state_sirs No Indicates that the device JTAG
controller is in the
Select_IR_Scan state.
Shared among all virtual JTAG
instances.
jtag_state_cir No Indicates that the device JTAG
controller is in the Capture_IR
state.
Shared among all virtual JTAG
instances.
jtag_state_sir No Indicates that the device JTAG
controller is in the Shift_IR state.
Shared among all virtual JTAG
instances.
jtag_state_e1ir No Indicates that the device JTAG
controller is in the Exit1_IR
state.
Shared among all virtual JTAG
instances.
jtag_state_pir No Indicates that the device JTAG
controller is in the Pause_IR
state.
Shared among all virtual JTAG
instances.
jtag_state_e2ir No Indicates that the device JTAG
controller is in the Exit2_IR
state.
Shared among all virtual JTAG
instances.
jtag_state_uir Indicates that the device JTAG
controller is in the Update_IR
state.
Shared among all virtual JTAG
instances.
tms TMS input pin on the device. Shared among all virtual JTAG
instances.
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Parameters
Table 7. Virtual JTAG Parameters
Parameter Type Required Description
SLD_AUTO_INSTANCE_INDEX String Yes Specifies whether the Compiler automatically assigns
an index to the Virtual JTAG instance. Values are
YES or NO. When you specify NO, you can find the
auto assigned value of INSTANCE_ID in the
quartus_map file. When you specify NO, you must
define INSTANCE_INDEX. If the index specified is
not unique in a design, the Compiler automatically
reassigns an index to the instance. The default value
is YES.
SLD_INSTANCE_INDEX Integer No Specifies a unique identifier for every instance of
alt_virtual_jtag when AUTO_INSTANCE_ID is
specified to YES. Otherwise, this value is ignored.
SLD_IR_WIDTH Integer Yes Specifies the width of the instruction register
ir_in[] of this virtual JTAG between 1 and 24. If
omitted, the default is 1.
Design Flow of the Virtual JTAG IP Core
Designing with the Virtual JTAG IP core includes the following processes:
• Configuring the Virtual JTAG IP core with the desired Instruction Register length
and instantiating the IP core.
• Building the glue logic for interfacing with your application.
• Communicating with the Virtual JTAG instance during runtime.
In addition to the JTAG datapath and control signals, the Virtual JTAG IP core
encompasses the VIR. The Instruction Register size is configured in the parameter
editor. The Instruction Register port on the Virtual JTAG IP core is the parallel output
of the VIR. Any updated VIR information can be read from this port after the
virtual_state_uir signal is asserted.
After instantiating the IP core, you must create the VDR chains that interface with
your application. To do this, you use the virtual instruction output to determine which
VDR chain is the active datapath, and then create the following:
• Decode logic for the VIR
• VDR chains to which each VIR maps
• Interface logic between your VDR chains and your application logic
Your glue logic uses the decoded one-hot outputs from the IP core to determine when
to shift and when to update the VDR. Your application logic interfaces with the VDR
chains during any one of the non-shift virtual JTAG states.
For example, your application logic can parallel read an updated value that was shifted
in from the JTAG port after the virtual_state_uir signal is asserted. If you load a
value to be shifted out of the JTAG port, you would do so when the
virtual_state_cdr signal is asserted. Finally, if you enable the shift register to
clock out information to TDO, you would do so during the assertion of
virtual_state_sdr.
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Maintaining TDI-to-TDO connectivity is important. Ensure that all possible instruction
codes map to an active register chain to maintain connectivity in the TDI-to-TDO
datapath. Intel recommends including a bypass register as the active register for all
unmapped IR values.
Note that TCK (a maximum 10-MHz clock, if using an Intel programming cable)
provides the clock for the entire SLD infrastructure. Be sure to follow best practices for
proper clock domain crossing between the JTAG clock domain and the rest of your
application logic to avoid metastability issues. The decoded virtual JTAG state signals
can help determine a stable output in the VIR and VDR chains.
After compiling and downloading your design into the device, you can perform shift
operations directly to the VIR and VDR chains using the Tcl commands from the
quartus_stp executable and an Intel programming cable (for example, an Intel
FPGA Download Cable, a MasterBlaster™ cable, or an Intel FPGA Parallel Port Cable).
The quartus_stp executable is a command-line executable that contains Tcl
commands for all on-chip debug features available in the Intel Quartus Prime
software.
The figure below shows the components of a design containing one instance of the
Virtual JTAG IP core. The TDI-to-TDO datapath for the virtual JTAG chain, shown in
red, consists of a bank of DR registers. Input to the application logic is the parallel
output of the VDR chains. Decoded state signals are used to signal start and stop of
shift transactions and signals when the VDR output is ready.
The IR_out port, not shown, is an optional input port you can use to parallel load the
VIR from the FPGA core logic.
Figure 9. Block Diagram of a Design with a Single Virtual JTAG Instantiation
Inferred by Instantiation
of Intel FPGA IP Core
Glue Logic between VJI and User Design
(Created by Designer)
Original Design
Application
Logic
SLD
Hub
VJI Intel FPGA
IP Core Instance
IR
JTAG TAP
Controller
TDI
TDO
TMS
TCK
TRST
TMS & Decoded
State Signals
IR_in
TDI
TDO
Input Vector 1
Input Vector 2
Input Vector n
VDR Chain 1
VDR Chain 2
VDR Chain n
Simulation Model
The virtual JTAG IP core contains a functional simulation model that provides stimuli
that mimic VIR and VDR shifts. You can configure the stimuli using the parameter
editor. You can use this simulation model for functional verification only, and the
operation of the SLD hub and the SLD node-to-hub interface is not provided in this
simulation model.
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Run-Time Communication
The Tcl API for the Virtual JTAG IP core consists of a set of commands for accessing
the VIR and VDR of each virtual JTAG instance.
These commands contain the underlying drivers for accessing an Intel programming
cable and for issuing shift transactions to each VIR and VDR. The table below provides
the Tcl commands in the quartus_stp executable that you can use with the Virtual
JTAG IP core, and are intended for designs that use a custom controller to drive the
JTAG chain.
Each instantiation of the Virtual JTAG IP core includes an instance index. All instances
are sequentially numbered and are automatically provided by the Intel Quartus Prime
software. The instance index starts at instance index 0. The VIR and VDR shift
commands described in the table decode the instance index and provide an address to
the SLD hub for each IP core instance. You can override the default index provided by
the Intel Quartus Prime software during configuration of the IP core.
The table below provides the Tcl commands in the quartus_stp executable that you
can use with the Virtual JTAG IP core, and are intended for designs that use a custom
controller to drive the JTAG chain.
Table 8. Virtual JTAG IP Core Tcl Commands
Command Arguments Description
Device virtual ir shift -instance_index <instance_index>
-ir_value <numeric_ir_value>
-no_captured_ir_value(1)
-show_equivalent_device_ir_dr_shift(1)
Perform an IR shift operation to
the virtual JTAG instance specified
by the instance_index. Note
that ir_value takes a numerical
argument.
Device virtual dr shift -instance_index <instance_index>
-dr_value <dr_value>
-length <data_register_length>
-no_captured_dr_value(1)
-show_equivalent_device_ir_dr_shift
-value_in_hex(1)
Perform a DR shift operation to
the virtual JTAG instance.
Get hardware names NONE Queries for all available
programming cables.
Open device -device_name <device_name>
-hardware_name <hardware_name>
Selects the active device on the
JTAG chain.
Close device NONE Ends communication with the
active JTAG device.
Device lock -timeout <timeout>Obtains exclusive communication
to the JTAG chain.
Device unlock NONE Releases device_lock.
Device ir shift -ir_value <ir_value>
-no_captured_ir_value
Performs a IR shift operation.
Device dr shift -dr_value <dr_value>
-length <data register length>
Performs a DR shift operation.
continued...
(1) This argument is optional.
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Command Arguments Description
-no_captured_dr_value
-value_in_hex
Central to Virtual JTAG IP core are the device_virtual_ir_shift and
device_virtual_dr_shift commands. These commands perform the shift
operation to each VIR/VDR and provide the address to the SLD hub for the active JTAG
datapath.
Each device_virtual_ir_shift command issues a USER1 instruction to the JTAG
Instruction Register followed by a DR shift containing the VIR value provided by the
ir_value argument prepended by address bits to target the correct SLD node
instance.
Note: Use the -no_captured_ir_value argument if you do not care about shifting out the
contents of the current VIR value. Enabling this argument increases the speed of the
VIR shift transaction by eliminating a command cycle within the underlying
transaction.
Similarly, each device_virtual_dr_shift command issues a USER0 instruction to
the JTAG Instruction Register followed by a DR shift containing the VDR value provided
by the dr_value argument. These commands return the underlying JTAG
transactions with the show_equivalent_device_ir_dr_shift option set.
Note: The device_virtual_ir_shift takes the ir_value argument as a numeric value.
The device_virtual_dr_shift takes the dr_value argument by either a binary
string or a hexadecimal string. Do not use numeric values for the
device_virtual_dr_shift.
Running a DR Shift Operation Through a Virtual JTAG Chain
A simple DR shift operation through a virtual JTAG chain using an Intel download cable
consists of the following steps:
1. Query for the Intel programming cable and select the active cable.
2. Target the desired device in the JTAG chain.
3. Obtain a device lock for exclusive communication to the device.
4. Perform a VIR shift.
5. Perform a VDR shift.
6. Release exclusive link with the device with the device_unlock command.
7. Close communication with the device with the close_device command.
Run-Time Communication
The Virtual JTAG IP core Tcl API requires an Intel programming cable. Designs that use
a custom controller to drive the JTAG chain directly must issue the correct JTAG IR/DR
transactions to target the Virtual JTAG IP core instances. The address values and
register length information for each Virtual JTAG IP core instance are provided in the
compilation reports.
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The following figure shows the compilation report for a Virtual JTAG IP core Instance.
The following table describes each column in the Virtual JTAG Settings compilation
report.
Figure 10. Compilation Report
Table 9. Virtual JTAG Settings Description
Setting Description
Instance Index Instance index of the virtual JTAG IP core. Assigned at compile time.
Auto Index Details whether the index was auto-assigned.
Index Re-Assigned Details whether the index was user-assigned.
IR Width Length of the Virtual IR register for this IP core instance; defined in the
parameter editor.
Address The address value assigned to the IP core by the compiler.
USER1 DR Length The length of the USER1 DR register. The USER1 DR register encapsulates the
VIR for all SLD nodes.
VIR Capture Instruction Instruction value to capture the VIR of this IP core instance.
The Tcl API provides a way to return the JTAG IR/DR transactions by using the
show_equivalent_device_ir_dr_shift argument with the
device_virtual_ir_shift and device_virtual_dr_shift commands. The
following examples use returned values of a virtual IR/DR shift to illustrate the format
of the underlying transactions.
To use the Tcl API to query for the bit pattern in your design, use the
show_equivalent_device_ir_dr_shift argument with the
device_virtual_ir_shift and device_virtual_dr_shift commands.
Both examples are from the same design, with a single Virtual JTAG instance. The VIR
length for the reference Virtual JTAG instance is configured to 3 bits in length.
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Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values
VIR shifts consist of a USER1 (0x0E) IR shift followed by a DR shift to the virtual
Instruction Register. The DR Scan shift consists of the value passed by the -
dr_value argument. The length and value of the DR shift is dependent on the
number of SLD nodes in your design. This value consists of address bits to the SLD
node instance concatenated with the desired value of the virtual Instruction Register.
The addressing scheme is determined by the Intel Quartus Prime software during
design compilation.
The Tcl command examples below show a VIR/VDR transaction with the
no_captured_value option set. The commands return the underlying JTAG shift
transactions that occur.
Virtual IR Shift with the no_captured_value Option
device_virtual_ir_shift -instance_index 0 -ir_value 1 \
-no_captured_ir_value -show_equivalent_device_ir_dr_shift ↵
Returns:
Info: Equivalent device ir and dr shift commands
Info: device_ir_shift -ir_value 14
Info: device_dr_shift -length 5 -dr_value 11 -value_in_hex
Virtual DR Shift with the no_captured_value Option
device_virtual_dr_shift -instance_index 0 -length 8 -dr_value \
04 -value_in_hex -no_captured_dr_value \
-show_equivalent_device_ir_dr_shift ↵
Returns:
Info: Equivalent device ir and dr shift commands
Info: device_ir_shift -ir_value 12
Info: device_dr_shift -length 8 -dr_value 04 -value_in_hex
The VIR value field in the figure below is four bits long, even though the VIR length is
configured to be three bits long, and shows the bit values and fields associated with
the VIR/VDR scans. The Instruction Register length for all Intel FPGAs and CPLDs is
10-bits long. The USER1 value is 0x0E and USER0 value is 0x0C for all Intel FPGAs
and CPLDs. The Address bits contained in the DR scan shift of a VIR scan are
determined by the Intel Quartus Prime software.
All USER1 DR chains must be of uniform length. The length of the VIR value field
length is determined by length of the longest VIR register for all SLD nodes
instantiated in the design. Because the SLD hub VIR is four bits long, the minimum
length for the VIR value field for all SLD nodes in the design is at least four bits in
length. The Intel Quartus Prime Tcl API automatically sizes the shift transaction to the
correct length. The length of the VIR register is provided in the Virtual JTAG settings
compilation report. If you are driving the JTAG interface with a custom controller, you
must pay attention to size of the USER1 DR chain.
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Figure 11. Equivalent Bit Pattern Shifted into Device by VIR/VDR Shift Commands
Virtual IR Scan
Virtual DR Scan
IR Scan Shift
IR Scan Shift
DR Scan Shift
DR Scan Shift
USER1
USER0
VIR Value
VDR Value
Addr
000000 000
00000 000000 00
1 1
1 1 0 0
1
1 1 1
0
Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values
The Tcl command examples below show that the no_captured_value option is not
set in the Virtual IR/DR shift commands and the underlying JTAG shift commands
associated with each. In the VIR shift command, the command returns two
device_dr_shift commands.
Virtual IR Shift
device_virtual_ir_shift -instance_index 0 -ir_value 1 \
-no_captured_ir_value -show_equivalent_device_ir_dr_shift
Returns:
Info: Equivalent device ir and dr shift commands
Info: device_ir_shift -ir_value 14
Info: device_dr_shift –length 5 –dr_value 0B –value_in_hex
Info: device_dr_shift -length 5 -dr_value 11 -value_in_hex
Virtual DR Shift
device_virtual_dr_shift -instance_index 0 -length 8 -dr_value \
04 -value_in_hex -show_equivalent_device_ir_dr_shift
Returns:
Info: Equivalent device ir and dr shift commands
Info: device_ir_shift -ir_value 12
Info: device_dr_shift -length 8 -dr_value 04 -value_in_hex
The figure below shows an example of VIR/VDR Shift Commands with captured IR
values. DR Scan Shift 1 is the VIR_CAPTURE command, as shown in the figure below.
It targets the VIR of the sld_hub. This command is an address cycle to select the
active VIR chain to shift after jtag_state_cir is asserted. The HUB_FORCE_IR
capture must be issued whenever you capture the VIR from a target SLD node that is
different than the current active node. DR Scan Shift 1 targets the SLD hub VIR to
force a captured value from Virtual JTAG instance 1 and is shown as the VIR_CAPTURE
command. DR Scan Shift 2 targets the VIR of Virtual JTAG instance.
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Figure 12. Equivalent Bit Pattern Shifted into Device by VIR/VDR Shift Commands with
Captured IR Values
Virtual IR Scan
Virtual DR Scan
IR Scan Shift
IR Scan Shift
DR Scan Shift 1
DR Scan Shift
USER1
USER0
VIR Value
VDR Value
Addr
000000 101
00000 00000
0 0 0
1 1
1 1 0 0
1
1 0 1
0
DR Scan Shift 2
VIR ValueAddr
000
1 1
Note: If you use an embedded processor as a controller for the JTAG chain and your Virtual
JTAG IP core instances, consider using the JAM Standard Test and Programming
Language (STAPL). JAM STAPL is an industry-standard flow-control-based language
that supports JTAG communication transactions. JAM STAPL is open source, with
software downloads and source code available from the Intel website.
Related Information
•ISP & the Jam STAPL
•Embedded Programming With Jam STAPL
Reset Considerations when Using a Custom JTAG Controller
The SLD hub decodes TMS independently to determine the JTAG controller state.
Under normal operation, the SLD hub mirrors all of the JTAG TAP controller states
accurately. The JTAG pins (TCK, TMS, TDI, and TDO) are accessible to the core
programmable logic; however, the JTAG TAP controller outputs are not visible to the
core programmable logic. In addition, the hard JTAG TAP controller does not use any
reset signals as inputs from the core programmable logic.
This can cause the following two situations in which control states of the SLD hub and
the JTAG TAP controller are not in lock-step:
•An assertion of the device wide global reset signal (DEV_CLRn)
•An assertion of the TRST signal, if available on the device
DEV_CLRn resets the SLD hub but does not reset the hard TAP controller block. The
TAP controller is meant to be decoupled from USER mode device operation to run
boundary scan operations. Asserting the global reset signal does not disrupt
boundary-scan test (BST) operation.
Conversely, the TRST signal, if available, resets the JTAG TAP controller but does not
reset the SLD hub. The TRST signal does not route into the core programmable logic
of the PLD.
To guarantee that the states of the JTAG TAP controller and the SLD hub state
machine are properly synchronized, TMS should be held high for at least five clock
cycles after any intentional reset of either the TAP controller or the system logic. Both
the JTAG TAP controller and the sld_hub controller are guaranteed to be in the Test
Logic Reset state after five clock cycles of TMS held high.
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Instantiating the Virtual JTAG IP Core
To create the Virtual JTAG IP core in an Intel Quartus Prime design requires the
following system and software requirements:
• The Intel Quartus Prime software
• An Intel download cable, such as an Intel FPGA Download Cable cable
The download cable is required to communicate with the Virtual JTAG IP core from a
host running the quartus_stp executable.
IP Catalog and Parameter Editor
The IP Catalog displays the IP cores available for your project, including Intel FPGA IP
and other IP that you add to the IP Catalog search path.. Use the following features of
the IP Catalog to locate and customize an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all
device families. If you have no project open, select the Device Family in IP
Catalog.
• Type in the Search field to locate any full or partial IP core name in IP Catalog.
• Right-click an IP core name in IP Catalog to display details about supported
devices, to open the IP core's installation folder, and for links to IP documentation.
• Click Search for Partner IP to access partner IP information on the web.
The parameter editor generates a top-level Quartus IP file (.qip) for an IP variation
in Intel Quartus Prime Standard Edition projects. These files represent the IP variation
in the project, and store parameterization information.
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Figure 13. IP Parameter Editor (Intel Quartus Prime Standard Edition)
The Parameter Editor
The parameter editor helps you to configure IP core ports, parameters, and output file
generation options. The basic parameter editor controls include the following:
• Use the Presets window to apply preset parameter values for specific applications
(for select cores).
• Use the Details window to view port and parameter descriptions, and click links to
documentation.
•Click Generate ➤ Generate Testbench System to generate a testbench system
(for select cores).
•Click Generate ➤ Generate Example Design to generate an example design
(for select cores).
The IP Catalog is also available in Platform Designer (View ➤ IP Catalog). The
Platform Designer IP Catalog includes exclusive system interconnect, video and image
processing, and other system-level IP that are not available in the Intel Quartus Prime
IP Catalog. Refer to Creating a System with Platform Designer or Creating a System
with Platform Designer (Standard) for information on use of IP in Platform Designer
(Standard) and Platform Designer, respectively.
Related Information
•Creating a System with Platform Designer
•Creating a System with Platform Designer (Standard) (Standard)
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Specifying IP Core Parameters and Options
Follow these steps to specify IP core parameters and options.
1. In the Platform Designer IP Catalog (Tools ➤ IP Catalog), locate and double-
click the name of the IP core to customize. The parameter editor appears.
2. Specify a top-level name for your custom IP variation. This name identifies the IP
core variation files in your project. If prompted, also specify the target FPGA
device family and output file HDL preference. Click OK.
3. Specify parameters and options for your IP variation:
• Optionally select preset parameter values. Presets specify all initial parameter
values for specific applications (where provided).
• Specify parameters defining the IP core functionality, port configurations, and
device-specific features.
• Specify options for generation of a timing netlist, simulation model, testbench,
or example design (where applicable).
• Specify options for processing the IP core files in other EDA tools.
4. Click Finish to generate synthesis and other optional files matching your IP
variation specifications. The parameter editor generates the top-level .qsys IP
variation file and HDL files for synthesis and simulation. Some IP cores also
simultaneously generate a testbench or example design for hardware testing.
5. To generate a simulation testbench, click Generate ➤ Generate Testbench
System. Generate Testbench System is not available for some IP cores that do
not provide a simulation testbench.
6. To generate a top-level HDL example for hardware verification, click Generate ➤
HDL Example. Generate ➤ HDL Example is not available for some IP cores.
The top-level IP variation is added to the current Intel Quartus Prime project. Click
Project ➤ Add/Remove Files in Project to manually add a .qsys (Intel Quartus
Prime Standard Edition) or .ip (Intel Quartus Prime Pro Edition) file to a project.
Make appropriate pin assignments to connect ports.
Files Generated for Altera IP Cores (Legacy Parameter Editor)
The Quartus II software version generates the following output for your IP core that
uses the legacy parameter editor.
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Figure 14. IP Core Generated Files
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
<Project Directory>
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
synthesis - IP synthesis files
<your_ip>.qip - Lists files for synthesis
testbench - Simulation testbench files 1
<testbench_hdl_files>
<simulator_vendor> - Testbench for supported simulators
<simulation_testbench_files>
<your_ip>.v or .vhd - Top-level IP variation synthesis file
simulation - IP simulation files
<your_ip>.sip - NativeLink simulation integration file
<simulator vendor> - Simulator setup scripts
<simulator_setup_scripts>
<your_ip> - IP core variation files
<your_ip>.qip or .qsys - System or IP integration file
<your_ip>_generation.rpt - IP generation report
<your_ip>.bsf - Block symbol schematic file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.spd - Combines individual simulation startup scripts 1
<your_ip>.html - Contains memory map
<your_ip>.sopcinfo - Software tool-chain integration file
<your_ip>_syn.v or .vhd - Timing & resource estimation netlist 1
<your_ip>.debuginfo - Lists files for synthesis
<your_ip>.v, .vhd, .vo, .vho - HDL or IPFS models2
<your_ip>_tb - Testbench for supported simulators
<your_ip>_tb.v or .vhd - Top-level HDL testbench file
Instantiating Directly in HDL
To properly connect the Virtual JTAG IP core in your design, follow these basic
connection rules:
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•The tck output from the Virtual JTAG IP core is the clock used for shifting the
data in and out on the TDI and TDO pins.
•The TMS output of the Virtual JTAG IP core reflects the TMS input to the main JTAG
circuit.
•The ir_in output port of the Virtual JTAG IP core is the parallel output of the
contents that get shifted into the virtual IR of the Virtual JTAG instance. This port
is used for decoding logic to select the active virtual DR chain.
The purpose of instantiating a Virtual JTAG instance in this example is to load
my_counter through the JTAG port using a software application built with Tcl
commands and the quartus_stp executable. In this design, the Virtual JTAG
instance is called my_vji. Whenever a Virtual JTAG IP core is instantiated in a design,
three logic blocks are usually needed: a decode logic block, a TDO logic block, and a
Data Register block. The example below combines the Virtual JTAG instance, the
decode logic, the TDO logic and the Data Register blocks.
You can use the following Verilog HDL template as a guide for instantiating and
connecting various signals of the IP cores in your design.
module counter (clock, my_counter);
input clock;
output [3:0] my_counter;
reg [3:0] my_counter;
always @ (posedge clock)
if (load && e1dr) // decode logic: used to load the counter my_counter
my_counter <= tmp_reg;
else
my_counter <= my_counter + 1;
// Signals and registers declared for VJI instance
wire tck, tdi;
reg tdo;
wire cdr, eldr, e2dr, pdr, sdr, udr, uir, cir;
wire [1:0] ir_in;
// Instantiation of VJI
my_vji VJI_INST(
.tdo (tdo),
.tck (tck),
.tdi (tdi),
.tms(),
.ir_in(ir_in),
.ir_out(),
.virtual_state_cdr (cdr),
.virtual_state_e1dr(e1dr),
.virtual_state_e2dr(e2dr),
.virtual_state_pdr (pdr),
.virtual_state_sdr (sdr),
.virtual_state_udr (udr),
.virtual_state_uir (uir),
.virtual_state_cir (cir)
);
// Declaration of data register
reg [3:0] tmp_reg;
// Deocde Logic Block
// Making some decode logic from ir_in output port of VJI
wire load = ir_in[1] && ~ir_in[0];
// Bypass used to maintain the scan chain continuity for
// tdi and tdo ports
bypass_reg <= tdi;
// Data Register Block
always @ (posedge tck)
if ( load && sdr )
tmp_reg <= {tdi, tmp_reg[3:1]};
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// tdo Logic Block
always @ (tmp_reg[0] or bypass_reg)
if(load)
tdo <= tmp_reg[0]
else
tdo <= bypass_reg;
endmodule
The decode logic is produced by defining a wire load to be active high whenever the
IR of the Virtual JTAG IP core is 01. The IR scan shift is used to load the data into the
IR of the Virtual JTAG IP core. The ir_in output port reflects the IR contents.
The Data Register logic contains a 4-bit shift register named tmp_reg. The always
blocks shown for the Data Register logic also contain the decode logic consisting of the
load and sdr signals. The sdr signal is the output of the Virtual JTAG IP core that is
asserted high during a DR scan shift operation. The time during which the sdr output
is asserted high is the time in which the data on tdi is valid. During that time period,
the data is shifted into the tmp_reg shift register. Therefore, tmp_reg gets the data
from the Virtual JTAG IP core on the tdi output port during a DR scan operation.
There is a 1-bit register named bypass_reg whose output is connected with tdo
logic to maintain the continuity of the scan chain during idle or IR scan shift operation
of the Virtual JTAG IP core. The tdo logic consists of outputs coming from tmp_reg
and bypass_reg and connecting to the tdo input of the Virtual JTAG IP core. The
tdo logic passes the data from tmp_reg to the Virtual JTAG IP core during DR scan
shift operations.
The always block of a 4-bit counter also consists of some decode logic. This decode
logic uses the load signal and e1dr output signal of the Virtual JTAG IP core to load
the counter with the contents of tmp_reg. The Virtual JTAG output signal e1dr is
asserted high during a DR scan shift operation when all the data is completely shifted
into the tmp_reg and sdr has been de-asserted. In addition to sdr and e1dr, there
are other outputs from the Virtual JTAG IP core that are asserted high to show various
states of the TAP controller and internal states of the Virtual JTAG IP core. All of these
signals can be used to perform different logic operations as needed in your design.
Simulation Support
Virtual JTAG interface operations can be simulated using all Intel-supported
simulators. The simulation support is for DR and IR scan shift operations. For
simulation purposes, a behavioral simulation model of the IP core is provided in both
VHDL and Verilog HDL in the altera_mf libraries. The I/O structure of the model is
the same as the IP core.
In its implementation, the Virtual JTAG IP core connects to your design on one side
and to the JTAG port through the JTAG hub on the other side. However, a simulation
model connects only to your design. There is no simulation model for the JTAG circuit.
Therefore, no stimuli can be provided from the JTAG ports of the device to imitate the
scan shift operations of the Virtual JTAG IP core in simulation.
The scan operations in simulation are realized using the simulation model. The
simulation model consists of a signal generator, a model of the SLD hub, and the
Virtual JTAG model. The stimuli defined in the wizard are passed as parameters to this
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simulation model from the variation file. The simulation parameters are listed in the
table below. The signal generator then produces the necessary signals for Virtual JTAG
IP core outputs such as tck, tdi, tms, and so forth.
The model is parameterized to allow the simulation of an unlimited number of Virtual
JTAG instances. The parameter sld_sim_action defines the strings used for IR and
DR scan shifts. Each Virtual JTAG’s variation file passes these parameters to the
Virtual JTAG component. The Virtual JTAG’s variation file can always be edited for
generating different stimuli, though the preferred way to specify stimuli for DR and IR
scan shifts is to use the parameter editor.
Note: To perform functional and timing simulations, you must use the altera_mf.v library
located in the <Intel Quartus Prime installation directory>\eda\sim_lib
directory. For VHDL, you must use the altera_mf.vhd library located in the <Intel
Quartus Prime installation directory>\eda\sim_lib directory. The VHDL
component declaration file is located in the altera_mf_components.vhd library in
the <Intel Quartus Prime installation directory>\eda\sim_lib directory.
Table 10. Description of Simulation Parameters
Parameter Comments
SLD_SIM_N_SCAN Specifies the number of shifts in the simulation model.
SLD_SIM_TOTAL_LENGTH The total number of bits to be shifted in either an IR shift or a DR shift. This value
should be equal to the sum of all the length values specified in the SLD_SIM_ACTION
string.
SLD_SIM_ACTION Specifies the strings used for instruction register (IR) and data register (DR) scan
shifts. The string has the following format:
((time,type,value,length),
(time,type,value,length),
...
(time,type,value,length))
where:
•time—A 32-bit value in milliseconds that represents the start time of the shift
relative to the completion of the previous shift.
•type—A 4-bit value that determines whether the shift is a DR shift or an IR shift.
•value—The data associated with the shift. For IR shifts, it is a 32-bit value. For DR
shifts, the length is determined by length.
•length—A 32-bit value that specifies the length of the data being shifted. This
value should be equal to SLD_NODE_IR_WIDTH; otherwise, the value field may be
padded or truncated. 0 is invalid.
Entries are in hexadecimal format.
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Simulation has the following limitations:
• Scan shifts (IR or DR) must be at least 1 ms apart in simulation time.
• Only behavioral or functional level simulation support is present for this IP core.
There is no gate level or timing level simulation support.
• For behavioral simulation, the stimuli tell the signal generator model in the Virtual
JTAG model to generate the sequence of signals needed to produce the necessary
outputs for tck, tms, tdi, and so forth. You cannot provide the stimulus at the
JTAG pins of the device.
•The tck clock period used in simulation is 10 MHz with a 50% duty cycle. In
hardware, the period of the tck clock cycle may vary.
• In a real system, each instance of the Virtual JTAG IP core works independently. In
simulation, multiple instances can work at the same time. For example, if you
define a scan shift for Virtual JTAG instance number 1 to happen at 3 ms and a
scan shift for Virtual JTAG instance number 2 to happen at the same time, the
simulation works correctly.
If you are using the ModelSim* - Intel FPGA Edition simulator, the altera_mf.v and
altera_mf.vhd libraries are provided in precompiled form with the simulator.
The inputs and outputs of the Virtual JTAG IP core during a typical IR scan shift
operation are shown in the figure below.
Figure 15. IR Shift Waveform
The figure below shows the inputs and outputs of the Virtual JTAG IP core during a
typical DR scan shift operation.
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Figure 16. DR Shift Waveform
Value of shift register
feed_reg changes
from xxxx to 1100
after a DR shift
Compiling the Design
You can instantiate a maximum of 128 instances of the Virtual JTAG IP core in a
design. After compilation, each instance has a unique ID, as shown on the Virtual
JTAG Settings page of the Analysis & Synthesis section of the Compilation Report, as
shown in the figure below.
Figure 17. IDs of Virtual JTAG Instances
ID of sid_virtual_jtag
instances
These unique IDs are necessary for the Intel Quartus Prime Tcl API to properly
address each instance of the IP core.
The addition of Virtual JTAG IP cores uses logic resources in your design. The Fitter
Resource Section in the Compilation Report shows the logic resource utilization, as
shown in the figure below.
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Figure 18. Logic Resources Utilized
sld_virtual_jtag
instances
Related Information
•Design Implementation and Optimization
•Verification
Third-Party Synthesis Support
In addition to the variation file, the parameter editor creates a black box file for the
Virtual JTAG IP core you created.
For example, if you create a my_vji.v file, a my_vji_bb.v file is also created. In
third-party synthesis, you include this black box file with your design files to
synthesize your project. A VQM file is usually produced by third-party synthesis tools.
This VQM netlist and the Virtual JTAG IP core’s variation files are input to the Intel
Quartus Prime software for further compilation.
SLD_NODE Discovery and Enumeration
You can use a custom JTAG controller to discover transactions necessary to enumerate
all Virtual JTAG IP core instances from your design at runtime. All SLD nodes and the
virtual JTAG registers that they contain are targeted by two Instruction Register
values, USER0 and USER1, which are shown in the table below.
Table 11. USER1 and USER2 Instruction Values
Instruction Binary Pattern
USER0 00 0000 1100
USER1 00 0000 1110
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The USER1 instruction targets the virtual IR of either the sld_hub or a SLD node.
That is, when the USER1 instruction is issued to the device, the subsequent DR scans
target a specific virtual IR chain based on an address field contained within the DR
scan. The table below shows how the virtual IR, the DR target of the USER1
instruction is interpreted.
The VIR_VALUE in the table below is the virtual IR value for the target SLD node. The
width of this field is m bits in length, where m is the length of the largest VIR for all of
the SLD nodes in the design. All SLD nodes with VIR lengths of fewer than m bits must
pad VIR_VALUE with zeros up to a length of m.
Table 12. USER1 DR
m + n – 1 m m – 1 0
ADDR [(n – 1)..0] VIR_VALUE [(m – 1)..0]
The ADDR bits act as address values to signal the active SLD node that the virtual IR
shift targets. ADDR is n bits in length, where n bits must be long enough to encode all
SLD nodes within the design, as shown below.
n = CEIL(log2(Number of SLD_nodes +1))
The SLD hub is always 0 in the address map, as shown below.
ADDR[(n -1)..0] = 0
Discovery and enumeration of the SLD instances within a design requires interrogation
of the sld_hub to determine the dimensions of the USER1 DR (m and n) and
associating each SLD instance, specifically the Virtual JTAG IP core instances, with an
address value contained within the ADDR bits of the USER1 DR.
The discovery and enumeration process consists of the following steps:
1. Interrogate the SLD hub with the HUB_INFO instruction.
2. Shift out the 32-bit HUB IP Configuration Register to determine the number of SLD
nodes in the design and the dimensions of the USER1 DR.
3. Associate the Virtual JTAG instance index to an ADDR value by shifting out the
32-bit SLD node info register for each SLD node in the design.
Issuing the HUB_INFO Instruction
The SLD hub contains the HUB IP Configuration Register and SLD_NODE_INFO register
for each SLD node in the design. The HUB IP configuration register provides
information needed to determine the dimensions of the USER1 DR chain.
The SLD_NODE_INFO register is used to determine the address mapping for Virtual
JTAG instance in your design. This register set is shifted out by issuing the HUB_INFO
instruction. Both the ADDR bits for the SLD hub and the HUB_INFO instruction is
0 × 0.
Because m and n are unknown at this point, the DR register
(ADDR bits + VIR_VALUE) must be filled with zeros. Shifting a sequence of 64
zeroes into the USER1 DR is sufficient to cover the most conservative case for m and
n.
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HUB IP Configuration Register
When the USER1 and HUB_INFO instruction sequence is issued, the USER0 instruction
must be applied to enable the target register of the HUB_INFO instruction.
The HUB IP configuration register is shifted out using eight four-bit nibble scans of the
DR register. Each four-bit scan must pass through the UPDATE_DR state before the
next four-bit scan. The 8 scans are assembled into a 32-bit value with the definitions
shown in the table below.
Table 13. Hub IP Configuration Register
Nibble7Nibble6Nibble5Nibble4Nibble3Nibble2Nibble1Nibble0
31 27 26 19 18 8 7 0
HUB IP version NALTERA_MFG_ID (0 × 06E) m
The dimensions of the USER1 DR chain can be determined from the SUM (m, n) and N
(number of nodes in the design). The equations below shows the values of m and n.
n = CEIL(log2(N+1))
m = SUM(m,n) – n
SLD_NODE Info Register
When the number of SLD nodes is known, the nodes on the hub can be enumerated
by repeating the 8 four-bit nibble scans, once for each Node, to yield the
SLD_NODE_INFO register of each node.
The DR nibble shifts are a continuation of the HUB_INFO DR shift used to shift out the
Hub IP Configuration register.
The order of the Nodes as they are shifted out determines the ADDR values for the
Nodes, beginning with, for the first Node SLD_NODE_INFO shifted out, up to and
including, for the last node on the hub. The tables below show the SLD_NODE_INFO
register and their functional descriptions.
Table 14. SLD_NODE_INFO Register
31 27 26 19 18 8 7 0
Node Version NODE ID NODE MFG_ID NODE_INST_ID
Table 15. SLD_NODE_INFO Register Descriptions
Field Function
Node Version Identifies the version of the SLD node
NODE ID Identifies the type of NODE IP (0x8 for the Virtual JTAG IP core)
NODE MFG_ID SLD Node Manufacturer ID (0x6E for Virtual JTAG IP core)
NODE_INST_ID Used to distinguish multiple instances of the same IP. Corresponds to the instance index
assigned in the parameter editor.
You can identify each Virtual JTAG instance within the design by decoding NODE ID
and NODE_INST_ID. The Virtual JTAG IP core uses a NODE ID of 8. The
NODE_INST_ID corresponds to the instance index that you configured within the
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parameter editor. The ADDR bits for each Virtual JTAG node is then determined by
matching each Virtual JTAG instance to the sequence number in which the
SLD_NODE_INFO register is shifted out.
Capturing the Virtual IR Instruction Register
In applications that contain multiple nodes, capturing the value of the VIR may require
issuing an instruction to the SLD hub to target a SLD node. You can query for a VIR
using the VIR_CAPTURE instruction.
Each NODE VIR register acts as a parallel hold rank register to the USER1 DR chain.
The sld_hub uses the bits prepended to the VIR shift value to target the correct SLD
NODE VIR register. After the SLD_state_machine asserts virtual_update_IR,
the active SLD node latches VIR_VALUE of the USER1 DR register.
The figure below shows a functional model of the interaction of the USER1 DR register
and the SLD node VIR. The ADDR bits target the selection muxes in the figure after
the sld_hub FSM has exited the virtual_update_IR state. Upon the next USER1 DR
transaction, the USER1 DR chain will latch the VIR of the last active SLD_NODE to
shift out of TDO. Thus, if you need to capture the VIR of an SLD node that is different
than the one addressed in the previous shift cycle, you must issue the VIR_CAPTURE
instruction. The VIR_CAPTURE instruction to the sld_hub acts as an address cycle to
force an update to the muxes.
Figure 19. Functional Model Interaction between USER1 DR CHAIN and SLD Node VIRs
TDI TDO
ADDR[n - 1..0] VIR_value
msb lsb
ADDR[n - 1..0]
ADDR[n - 1..0]
SLD NODE1 VIR
SLD NODE2 VIR
SLD NODE N VIR
USER1 DR
SLD Nodes
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To form the VIR_CAPTURE instruction, use the following instruction format:
VIR_CAPTURE = ZERO [ (m – 4)..0] ## ADDR [(n – 1)..0] ## 011
In this format, ZERO[] is an array of zeros, ## is the concatenation operator, m is the
width of VIR_VALUE, and n is the width of the ADDR bit.
AHDL Function Prototype
The following AHDL function prototype is located in the sld_virtual_jtag.inc file in
the <Intel Quartus Prime installation directory> \libraries\megafunctions
directory.
Note: Port name and order also apply to Verilog HDL.
FUNCTION sld_virtual_jtag(
ir_out[sld_ir_width-1..0],
tdo
)
WITH(
lpm_hint,
lpm_type,
sld_auto_instance_index,
sld_instance_index,
sld_ir_width,
sld_sim_action,
sld_sim_n_scan,
sld_sim_total_length
)
RETURNS(
ir_in[sld_ir_width-1..0],
jtag_state_cdr,
jtag_state_cir,
jtag_state_e1dr,
jtag_state_e1ir,
jtag_state_e2dr,
jtag_state_e2ir,
jtag_state_pdr,
jtag_state_pir,
jtag_state_rti,
jtag_state_sdr,
jtag_state_sdrs,
jtag_state_sir,
jtag_state_sirs,
jtag_state_tlr,
jtag_state_udr,
jtag_state_uir,
tck,
tdi,
tms,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir
);
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VHDL Component Declaration
The following VHDL component declaration is located in the
ALTERA_MF_COMPONENTS.vhd file located in the <Intel Quartus Prime
installation directory>\libraries\vhdl\altera_mf directory.
component sld_virtual_jtag
generic (
lpm_hint : string := "UNUSED";
lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1;
sld_sim_action : string := "UNUSED";
sld_sim_n_scan : natural := 0;
sld_sim_total_length : natural := 0 );
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out: in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
VHDL LIBRARY-USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component
Declaration.
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
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Design Example: TAP Controller State Machine
The TAP controller is a state machine with a set of control signals that routes TDI data
between the Instruction Register and the bank of DR chains. It controls the start and
stop of any shift transactions, and controls the data flow between the parallel hold
registers and the shift registers of the Instruction Register and the Data Register. The
TAP controller is controlled by the TMS pin.
The figure below shows the TAP controller state machine. The table that follows
provides a description of each of the states.
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Figure 20. JTAG TAP Controller State Machine
CAPTURE_DR
SHIFT_DR
EXIT1_DR
PAUSE_DR
EXIT2_DR
UPDATE_DR
CAPTURE_IR
SHIFT_IR
EXIT1_IR
PAUSE_IR
EXIT2_IR
UPDATE_IR
RUN_TEST/
IDLE
TEST_LOGIC/
RESET
TMS = 1
TMS = 0
TMS = 1
TMS = 0 TMS = 1
TMS = 1
TMS = 0 TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 0
TMS = 0 TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 0
TMS = 0 TMS = 0
TMS = 1
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
TMS = 0 TMS = 0
TMS = 0
TMS = 1
SELECT_
DR_SCAN
SELECT_
IR_SCAN
Table 16. Functional Description for the TAP Controller States
TAP Controller State Functional Description
Test-Logic-Reset The test logic of the JTAG scan chain is disabled.
Run-Test/Idle This is a hold state. Once entered, the controller remains in this state as long as
TMS is held low.
Select DR-Scan/Select IR Scan These are temporary controller states. A decision is made here whether to enter
the DR states or the IR states.
continued...
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TAP Controller State Functional Description
Capture DR/Capture IR These states enable a parallel load of the shift registers from the hold registers
on the rising edge of TCK.
Shift DR/Shift IR These states enable shifting of the DR and IR chains.
Exit1 DR/Exit1 IR Temporary hold states. A decision is made in these states to either advance to
the Update states or the Pause states.
Pause DR/Pause IR This controller state allows shifting of the Instruction Register and Data Register
to be temporarily halted.
Exit2 DR/Exit2 IR Temporary hold states. A decision is made in these states to advance to the
Update states.
Update DR/Update IR These states enable a parallel load of the hold registers from the shift registers.
Update happens on the falling edge of TCK.
Design Example: Modifying the DCFIFO Contents at Runtime
This design example demonstrates the use of the Virtual JTAG IP core and a
command-line script to dynamically modify the contents of a DCFIFO at runtime.
The Tcl API that ships with the Virtual JTAG IP core makes it an ideal solution for
developing command-line scripts that can be used to either update data values or
toggle control bits at run time. This visibility into the FPGA can help expedite debug
closure during the prototyping phase of the design, especially when external
equipment is not available to provide a stimulus.
This design example consists of an Intel Quartus Prime project file that implements a
DCFIFO and a command-line script that is used to modify the contents of the FIFO at
runtime.
The RTL consists of a single instantiation of the Virtual JTAG IP core to communicate
with the JTAG circuitry. Both read and write ports of the DCFIFO are clocked at 50
MHz. A Signal Tap logic analyzer instance taps the data output bus of the DCFIFO to
read burst transactions from the DCFIFO. The following sections discuss the RTL
implementation and the runtime control of the DCFIFO using the Tcl API.
Write Logic
The RTL uses a single instance of the Virtual JTAG IP core to decode both the
instructions for the write side and read side logic. The IR register is three bits wide,
with the three instructions decoded in the RTL, as shown in the table below.
Table 17. Instruction Register Values
Instruction Register Value Function
PUSH Instruction to write a single value to the write side logic of the DCFIFO.
POP Instruction to read a single value from the read side logic of the DCFIFO
FLUSH Instruction to perform a burst read transaction from the FIFO until empty.
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The IR decode logic shifts the Push_in virtual DR chain when the PUSH instruction is
on the IR port and virtual_state_sdr is asserted. A write enable pulse,
synchronized to the write_clock, asserts after the virtual_state_udr signal
goes high. The virtual_state_udr signal guarantees stability from the virtual DR
chain. The figure below shows the write side logic for the DCFIFO.
Figure 21. Write Side Logic for DCFIFO
DCFIFO
IR Decode/State
Decode Logic
IR_register
State
Information
TDI
TDO Write_req
Data[7:0]
Write_clock
Read_req
Read_clock
Q[7:0]
Rd_empty
Data_out
Virtual_DR
(Push_in)
VJI Instance
Read Logic
Two runtime instructions read the contents out of the FIFO. The IR decode logic
selects the Push_out virtual DR chain and generates a single read pulse to the read
logic when the POP instruction is active. The Push_out DR chain is parallel loaded
upon the assertion of virtual_state_cdr and shifted out to TDO upon the
assertion of virtual_state_sdr.
When the FLUSH instruction is shifted into the Virtual JTAG instance, the IR decode
logic asserts the read_req line until the FIFO is empty. The bypass register is
selected when the FLUSH instruction is active to maintain TDI-to-TDO connectivity.
The figure below shows the read side logic for the DCFIFO.
Figure 22. Read Side Logic for DCFIFO Design Example
IR Decode/State
Decode Logic
IR_register
State
Information
TDO
TDO
Write_req
Data[7:0]
Write_clock
Read_req
Read_clock
Q[7:0]
Rd_empty
Data_out
VJI Instance
Virtual DR
(Push_out)
Signal Tap
Embedded Logic
Analyzer
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Runtime Communication
The Tcl script, dc_fifo_vji.tcl, contains three procedures, each corresponding to
one of the virtual JTAG instructions. The table below describes each of the procedures.
Table 18. Run-Time Communication Tcl Procedures
Procedure Description
push [value] IR shift the PUSH instruction, followed by a DR shift of the value argument. Value
must be an integer less than 256.
pop IR shift the POP instruction, followed by a DR shift of 8 bits.
flushfifo IR shift the FLUSH instruction.
The figure below shows runtime execution of eight values pushed into the DCFIFO and
a flushfifo command, and a Signal Tap logic analyzer capture triggering on a flush
operation.
Figure 23. Runtime Execution
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Figure 24. Signal Tap Logic Analyzer Capture Triggering on a Flush Operation
Design Example: Offloading Hardwired Revision Information
This example demonstrates how you can use a GUI to offload revision information that
is hardwired into a design. The GUI offloads the time that the design was compiled,
the USERCODE from the device, and compile number that tracks the number of
compile iterations that have been performed.
Because the Intel Quartus Prime software ships with an installation of Tcl/Tk, you can
use the Tk package to build a custom GUI to interact with your design. In many cases,
the JTAG port is a convenient interface to use, since it is present in most designs for
debug purposes. By leveraging Tk and the virtual JTAG interface, you perform rapid
prototyping such as creating virtual front panels or creating simple software
applications. The figure below shows the organization of the design.
Figure 25. Design Organization Example
JTAG
Version
Control
Information
VJI
USERCODE
Top-Level Design
A Tcl script creates and updates the verilog file containing the hardcoded version
control information every time the project goes through a full compile. The Tcl script is
executed automatically by adding the following assignment to the project’s .qsf file.
The USERCODE value shifted out by this design example is a user-configurable 32-bit
JTAG register. This value is configured in the Intel Quartus Prime software using the
Device and Pin Options dialog box.
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Configuring the JTAG User Code Setting
The following steps describe how to configure the JTAG User Code setting. A separate
script generates the GUI and is executed with the quartus_stp command line
executable. During runtime, the GUI queries the device for the version information
and formats it for display within the message box.
1. On the Assignment menu, click Settings.
2. On the Settings page, in the Category list, click Device.
3. The Device dialog box appears. Click Device and Pin Options.
4. In the Device and Pin Options dialog box, on the General tab, the JTAG user
code appears. Type the user code in 32-bit hexadecimal format.
5. Click OK.
Related Information
Tcl Example Scripts: Automatic Version Number
Document Revision History for the Virtual JTAG
(altera_virtual_jtag) IP Core User Guide
Document Version Intel Quartus
Prime Version
Changes
2018.07.19 16.1 • Updated the following terms:
— Changed Quartus II to Intel Quartus Prime.
— Changed SignalTap II to Signal Tap.
— Changed megafunction to Intel FPGA IP core.
— Changed USB Blaster to Intel FPGA Download Cable.
— Changed ByteBlaster II to Intel FPGA Parallel Port Cable.
— Changed ModelSim-Altera to ModelSim - Intel FPGA Edition.
• Rebranded as Intel.
Date Version Changes
October 2016 2016.10.31 Removed Upgrading IP Cores section.
November 2015 2015.11.20 Corrected the flow for EXIT2_DR to SHIFT_DR in the JTAG TAP
Controller State Machine figure.
July 2014 2014.07.08 • Replaced MegaWizard Plug-In Manager information with IP Catalog.
• Added standard information about upgrading IP cores.
• Added standard installation and licensing information.
• Removed outdated device support level information. IP core device
support is now available in IP Catalog and parameter editor.
March 2014 2014.03.19 Updated the description of the SLD_IR_WIDTH parameter in the
"Parameters for the Virtual JTAG Megafunction" table.
February 2014 2014.02.25 • Added Document Revision History table.
• Updated "Hub IP Configuration Register" figure.
Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide
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