PDM31256 3.3V 256K Static RAM 32K x 8-Bit Description Features n High-speed access times Com'l: 10, 12, 15 and 20ns Ind'l: 12, 15 and 20ns n Low power operation (typical) - PDM31256SA Active: 200 mW Standby: 15mW n 1 The PDM31256 is a high-performance CMOS static RAM organized as 32,768 x 8 bits. Writing to this device is accomplished when the write enable (WE) and the chip enable (CE) inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE are both LOW. The PDM31256 operates from a single +3.3V power supply and all the inputs and outputs are fully TTLcompatible. Single +3.3V (0.3V) power supply n TTL-compatible inputs and outputs n Packages Plastic SOJ (300 mil) - SO Plastic TSOP (I) - T The PDM31256 is available in a 28-pin 300-mil plastic SOJ and a 28-pin plastic TSOP (I). 2 3 4 5 6 Functional Block Diagram Addresses I/O 0 * 7 A0 * * * * * A14 Decoder * * * * * * Memory 8 Matrix * * * * * Input Data Control 9 Column I/O * I/O 7 10 * * CE WE * 11 Control OE 12 Rev. 3.3 - 4/29/98 1 PDM31256 Pin Configurations SOJ Pin Description TSOP OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Vss I/O2 I/O1 I/O0 A0 A1 A2 A14 1 28 Vcc A12 2 27 WE A7 3 26 A6 4 25 A5 5 24 A9 A4 6 23 A11 Name Description A13 A14-A0 Address Inputs A8 I/O7-I/O0 Data Inputs/Outputs OE Output Enable Input Write Enable Input A3 7 22 OE WE A2 8 21 A10 CE Chip Enable Input A1 9 CE VCC Power (+3.3V) A0 10 20 19 I/O0 11 18 I/O6 VSS Ground I/O1 12 17 I/O5 I/O2 13 14 16 I/O4 15 I/O3 Vss I/O7 Truth Table OE WE CE I/O MODE X X L H H Hi-Z Standby L DOUT Read X L L DIN Write H H L Hi-Z Output Disable NOTE: 1. H = VIH, L = VIL, X = DON'T CARE Absolute Maximum Ratings (1) Symbol Rating Com'l. Ind. Unit VTERM Terminal Voltage with Respect to Vss -0.5 to +4.6 -0.5 to +4.6 V TBIAS Temperature Under Bias -55 to +125 -65 to +135 C TSTG Storage Temperature -55 to +125 -65 to +150 C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA 125 145 C Tj Maximum Junction Temperature (2) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * ja where Ta is the ambient temperature, P is average operating power and ja the thermal resistance of the package. For this product, use the following ja values: SOJ: 78 oC/W TSOP: 112 oC/W 2 Rev. 3.3 - 4/29/98 PDM31256 Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 3.0 3.3 3.6 V VSS Supply Voltage 0 0 0 V Commercial Ambient Temperature 0 25 70 C Industrial Ambient Temperature -40 25 85 C 1 2 3 DC Electrical Characteristics (VCC = 3.3V 0.3V) Symbol Parameter Test Conditions Min. Max. Unit ILI Input Leakage Current VCC = MAX., VIN = Vss to VCC -5 5 A ILO Output Leakage Current VCC= MAX., CE = VIH, VOUT = Vss to VCC -5 5 A VIL Input Low Voltage -0.3(1) 0.8 V VIH Input High Voltage 2.2 Vcc+0.3 V VOL Output Low Voltage IOL= 8 mA VCC = Min. -- 0.4 V VOH Output High Voltage IOH = -4 mA, VCC = Min. 2.4 -- V 4 5 6 NOTE:1.VIL(min) = -3.0V for pulse width less than 20 ns. 7 Power Supply Characteristics -10 Symbol Parameter ICC Operating Current CE = VIL Com'l. 140 -12 -15 -17 8 -20 Com'l Ind. Com'l Ind. Com'l Ind. Com'l Ind. 130 130 120 120 120 120 110 110 Unit mA 9 f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA ISB Standby Current CE = VIH 45 40 35 35 35 35 35 30 30 mA 10 f = fMAX = 1/tRC VCC = Max. ISB1 Full Standby Current CE VCC - 0.2V 10 10 15 10 15 10 15 10 15 mA 11 f=0 VCC = Max., VIN VCC - 0.2V or 0.2V 12 NOTES: All values are maximum guaranteed values. Rev. 3.3 - 4/29/98 3 PDM31256 Capacitance(1) (TA = +25C, f = 1.0 MHz) Symbol Parameter Max. Unit CIN COUT Input Capacitance 8 pF Output Capacitance 8 pF NOTE: 1. This parameter is determined by device characterization but is not production tested. AC Test Conditions Input pulse levels VSS to 3.0V Input rise and fall times 2.5 ns Input timing reference levels 1.5V Output reference levels 1.5V Output load See Figures 1 and 2 +3.3V +3.3V 319 319 DATAOUT DATAOUT 353 353 30 pF Delta tAA - ns Figure 1. Output Load Equivalent 5 pF Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE) Typical Delta tAA vs Capacitive Loading 5 4 3 2 1 0 0 30 60 90 120 Additional Lumped Capacitive Loading (pF) Figure 3. 4 Rev. 3.3 - 4/29/98 PDM31256 Read Cycle No. 1(1) t RC ADDR 1 t AA t OH DOUT PREVIOUS DATA VALID 2 DATA VALID 3 Read Cycle No. 2(2) tRC 4 ADDR tAA tACE CE tHZCE tLZCE 5 OE tLZOE tHZOE DOUT DATA VALID tAOE 6 7 AC Electrical Characteristics Description -10 READ Cycle Sym -12 -15 -17 Min. Max. Min. Max. Min. Max. Min 17 Max 20 tAA 10 12 15 17 20 ns Chip enable access time tACE 10 12 15 17 20 ns Output hold from address change tOH 3 3 3 3 3 ns tLZCE 5 5 5 5 5 ns Chip enable to power up time(4) tHZCE tPU Chip disable to power down time (4) Output enable access time (4,5) Output enable to output in low Z Output disable to output in high Z (4,5) 8 0 10 0 12 10 0 0 ns 15 0 12 15 17 20 ns tAOE 5 6 8 9 10 ns tHZOE 0 8 0 0 8 8 0 8 10 ns 10 0 9 ns tPD tLZOE 8 Units Address access time Chip disable to output in high Z 15 Min tRC (3,4,5) 12 Max READ cycle time Chip enable to output in low Z(3,4,5) 10 -20 11 ns 8 ns 12 Rev. 3.3 - 4/29/98 5 PDM31256 Write Cycle No. 1 (Write Enable Controlled) t WC ADDR t AW CE t WE t AH t CW t WP AS t DH t DS DIN DATA VALID t HZWE t LZWE HIGH Z DOUT Write Cycle No. 2 (Chip Enable Controlled) t WC ADDR t AW tCW tAS CE t AH t WP UNDEFINED WE t DS DIN t DH DON'T CARE DATA VALID AC Electrical Characteristics Description 6 -10 -12 -15 -17 Min. Max. Min. Max. Min. Max. WRITE Cycle Sym WRITE cycle time tWC 10 12 15 17 20 ns Chip enable to end of write tCW 10 10 12 12 13 ns Address valid to end of write tAW 10 10 12 12 13 ns Address setup time tAS 0 0 0 0 0 ns Address hold from end of write tAH 0 0 0 0 0 ns Write pulse width tWP 8 10 11 11 12 ns Data setup time tDS 7 7 7 8 9 ns Data hold time tDH 0 0 0 0 0 ns (4,5) Write disable to output in low Z tLZWE 0 Write enable to output in high Z(4,5) tHZWE 0 3 Max. 0 0 3 Min. -20 3 Min. Max. 0 3 Units ns 3 ns Rev. 3.3 - 4/29/98 PDM31256 NOTES: (For two previous Electrical Characteristics tables) 1. The device is continuously selected. Chip Enable is held in its active state. 2. The address is valid prior to or coincident with the latest occuring Chip Enable. 3. At any given temperature and voltage condition, tHZCE is less than tLZCE. 4. This parameter is sampled. 5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured 200 mV from steady state voltage. 1 2 3 Ordering Information XXXXX X Device Type Power XX Speed X X X Package Type Process Temp. Range Preferred Shipping Container 4 Blank Tubes TR Tape & Reel TY Tray 5 Blank Commercial (0 to +70C) I Industrial (-40C to +85C) A Automotive ( -40C to +105C) SO T 28-pin 300-mil Plastic SOJ 28-pin Plastic TSOP (I) 10 12 15 17 20 Commercial Only SA Standard Power 6 7 8 PDM31256 - 256K (32Kx8) Sync. Static RAM 9 10 11 12 Faster Memories for a FasterWorld TM Rev. 3.3 - 4/29/98 7