1
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
------Table of Contents------
Description
The M16C/61 group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of in-
struction efficiency. With 1M bytes of address space, they are capable of executing instructions at high
speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communi-
cations, industrial equipment, and other high-speed processing applications.
The M16C/61 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Memory capacity............................................ROM (See Figure 1.1.4. ROM Expansion)
RAM 4K to 10K bytes
• Shortest instruction execution time................100ns (f(XIN)=10MHZ)
• Supply voltage ...............................................4.0 to 5.5V (f(XIN)=10MHZ)
2.7 to 5.5V (f(XIN)=7MHZ with software one-wait)
• Low power consumption ................................18mW ( f(XIN)=7MHZ, with software one-wait, VCC = 3V)
• Interrupts........................................................20 internal and 5 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer................................5 output timers + 3 input timers
• Serial I/O (UART or clock synchronous)........3 channels
• DMAC ............................................................2 channels (trigger: 16 sources)
• A-D converter.................................................10 bits X 8 channels
(Expandable up to 10 channels)
• D-A converter.................................................8 bits X 2 channels
• CRC calculation circuit...................................1 circuit
• Watchdog timer..............................................1 line
• Programmable I/O .........................................87 lines
• Input port........................................................ _______
1 line (P85 shared with NMI pin)
• Memory expansion ........................................Available (to a maximum of 1M bytes)
• Chip select output ..........................................4 lines
• Clock generating circuit .................................2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
Timer.............................................................70
Serial I/O .......................................................87
A-D Converter .............................................114
D-A Converter .............................................124
CRC Calculation Circuit ..............................126
Programmable I/O Ports .............................128
Electrical Characteristics.............................142
Central Processing Unit (CPU) .....................11
Reset.............................................................14
Processor Mode............................................19
Clock Generating Circuit ...............................30
Protection......................................................39
Interrupts.......................................................40
Watchdog Timer............................................59
DMAC ...........................................................61
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2
Description
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96
97
98
99
100
P00/D0
P01/D1
P02/D2
P03/D3
P04/D4
P05/D5
P06/D6
P07/D7
P1
0
/D
8
P1
1
/D
9
P1
2
/D
10
P1
3
/D
11
P1
4
/D
12
P1
5
/D
13
VREF
P1
6
/D
14
P1
7
/D
15
V
CC
X
IN
RESET
X
OUT
V
SS
CNVss
P8
6
/X
COUT
P8
7
/X
CIN
BYTE P2
0
/A
0
(/D
0
/-)
P2
1
/A
1
(/D
1
/D
0
)
P2
2
/A
2
(/D
2
/D
1
)
P2
3
/A
3
(/D
3
/D
2
)
P2
4
/A
4
(/D
4
/D
3
)
P2
5
/A
5
(/D
5
/D
4
)
P2
6
/A
6
(/D
6
/D
5
)
P2
7
/A
7
(/D
7
/D
6
)
P3
0
/A
8
(/-/D
7
)
P3
1
/A
9
P3
2
/A
10
P3
3
/A
11
P3
4
/A
12
P3
5
/A
13
P3
6
/A
14
P3
7
/A
15
P4
0
/A
16
P4
1
/A
17
P4
2
/A
18
P4
3
/A
19
P7
4
/TA2
OUT
P7
5
/TA2
IN
P7
6
/TA3
OUT
P56/ALE
P7
7
/TA3
IN
P55/HOLD
P54/HLDA
P53/BCLK
P52/RD
Vcc
Vss
AVcc
P63/TXD0
P65/CLK1
P66/RxD1
P67/TXD1
P61/CLK0
P62/RxD0
P57/RDY/CLKOUT
AVSS
P100/AN0
P101/AN1
P102/AN2
P103/AN3
P9
3
/DA
0
P9
4
/DA
1
P9
5
/ANEX0
P9
6
/ANEX1
P9
1
/TB1
IN
P9
2
/TB2
IN
P8
2
/INT
0
P8
3
/INT
1
P8
1
/TA4
IN
P8
4
/INT
2
P8
0
/TA4
OUT
P60/CTS0/RTS0
P64/
CTS
1
/RTS
1
/CTS
0
/CLKS
1
P7
3
/CTS
2
/RTS
2
/TA1
IN
P7
2
/CLK
2
/TA1
OUT
P8
5
/NMI
P97/ADTRG
P45/CS1
P46/CS2
P47/CS3
P44/CS0
P50/WRL/WR
P51/WRH/BHE
P9
0
/TB0
IN
P7
0
/TxD
2
/TA0
OUT
(Note)
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P7
1
/RxD
2
/TA0
IN
(Note)
Note: P7
0
and P7
1
are N channel open-drain output pin.
M16C/61 Group
Pin Configuration
Figures 1.1.1 and 1.1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
Package: 100P6S-A
Figure 1.1.1. Pin configuration (top view)
3
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
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100
P4
2
/A
18
P4
3
/A
19
P1
3
/D
11
P1
4
/D
12
P1
5
/D
13
P1
6
/D
14
P1
7
/D
15
P2
0
/A
0
(/D
0
/-)
P2
1
/A
1
(/D
1
/D
0
)
P2
2
/A
2
(/D
2
/D
1
)
P2
3
/A
3
(/D
3
/D
2
)
P2
4
/A
4
(/D
4
/D
3
)
P2
5
/A
5
(/D
5
/D
4
)
P2
6
/A
6
(/D
6
/D
5
)
P2
7
/A
7
(/D
7
/D
6
)
P3
0
/A
8
(/-/D
7
)
P3
1
/A
9
P3
2
/A
10
P3
3
/A
11
P3
4
/A
12
P3
5
/A
13
P3
6
/A
14
P3
7
/A
15
P4
0
/A
16
P4
1
/A
17
Vcc
Vss
P5
6
/ALE
P5
5
/HOLD
P5
4
/HLDA
P5
3
/BCLK
P5
2
/RD
P6
3
/T
X
D
0
P6
5
/CLK
1
P6
6
/RxD
1
P6
7
/T
X
D
1
P6
1
/CLK
0
P6
2
/RxD
0
P5
7
/RDY/CLK
OUT
P6
0
/CTS
0
/RTS
0
P6
4/
CTS
1
/RTS
1
/CTS
0
/CLKS
1
P4
6
/CS2
P4
7
/CS3
P4
5
/CS1
P4
4
/CS0
P5
0
/WRL/WR
P5
1
/WRH/BHE
V
CC
X
IN
X
OUT
V
SS
CNVss
P8
6
/X
COUT
P8
7
/X
CIN
BYTE
P7
4
/TA2
OUT
P7
5
/TA2
IN
P7
6
/TA3
OUT
P7
7
/TA3
IN
P9
3
/DA
0
P9
4
/DA
1
P9
1
/TB1
IN
P9
2
/TB2
IN
P8
1
/TA4
IN
P8
0
/TA4
OUT
P7
2
/CLK
2
/TA1
OUT
P8
4
/INT
2
P7
1
/RxD
2
/TA0
IN
(Note)
P8
5
/NMI
P9
0
/TB0
IN
P7
0
/TxD
2
/TA0
OUT
(Note)
P8
3
/INT
1
P8
2
/INT
0
P1
0
/D
8
P1
1
/D
9
P1
2
/D
10
P9
5
/ANEX0
P9
6
/ANEX1
P0
0
/D
0
P0
1
/D
1
P0
2
/D
2
P0
3
/D
3
P0
4
/D
4
P0
5
/D
5
P0
6
/D
6
P0
7
/D
7
V
REF
AVcc
AV
SS
P10
0
/AN
0
P10
1
/AN
1
P10
2
/AN
2
P10
3
/AN
3
P9
7
/AD
TRG
P10
7
/AN
7
/KI
3
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4/
KI
0
RESET
P7
3
/CTS
2
/RTS
2
/TA1
IN
Note: P7
0
and P7
1
are N channel open-drain output pin.
M16C/61 Group
Figure 1.1.2. Pin configuration (top view)
Package: 100P6Q-A
PIN CONFIGURATION (top view)
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
4
Description
Block Diagram
Figure 1.1.3 is a block diagram of the M16C/61 group.
Block diagram of the M16C/61 group
AAAA
A
AA
A
AAAA
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
A-D converter
(10 bits
X
8 channels
Expandable up to 10 channels)
UART/clock synchronous SI/O
(8 bits
X
3channels) (Note 3)
System clock generator
X
IN
-X
OUT
X
CIN
-X
COUT
M16C/60 series16-bit CPU core
I/O ports
Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
Port P6
8
8
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
Registers
ISP
USP
Stack pointer
Vector table
INTB
CRC arithmetic circuit (CCITT )
(Polynomial : X
16
+X
12
+X
5
+1)
Multiplier
788
Port P10
Port P9
Port P8
Port P7
AAAAAA
A
AAAA
A
A
AAAA
A
AAAAAA
Memory
Port P8
5
ROM
(Note 1)
RAM
(Note 2)
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Note 3: One of serial I/O can use for SIM interface.
SB FLG
PC
Program counter
Figure 1.1.3. Block diagram of M16C/61 group
5
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time 100ns(f(XIN)=10MHZ)
Memory ROM (See the Figure 4. ROM Expansion)
capacity RAM 4K to 10K bytes
I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1
Input port P851 bit x 1
Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5
timer TB0, TB1, TB2 16 bits x 3
Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3
A-D converter 10 bits x (8 + 2) channels
D-A converter 8 bits x 2
DMAC 2 channels (trigger: 16 sources)
CRC calculation circuit CRC - CCITT
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt
20 internal and 5 external sources, 4 software sources, 7 levels
Clock generating circuit 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Supply voltage 4.0 to 5.5V (f(XIN ) = 10MHZ)
2.7 to 5.5V(f(XIN)=7MHZ with software one-wait)
Power consumption
18mW (f(XIN) = 7MHZ with software one-wait,VCC = 3V)
I/O I/O withstand voltage 5V
characteristics Output current 5mA
Memory expansion Available (to a maximum of 1M bytes)
Device configuration CMOS silicon gate
Package 100-pin plastic mold QFP
Table 1.1.1. Performance outline of M16C/61 group
Performance Outline
Table 1.1.1 is a performance outline of M16C/61 group.
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
6
Description
Mitsubishi plans to release the following products in the M16C/61 group:
(1) Support for mask ROM version, external ROM version, one-time PROM version, and EPROM version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP (mask ROM version and one-time PROM version)
100P6Q-A : Plastic molded QFP (mask ROM version and one-time PROM version)
100D0 : Ceramic LCC (EPROM version)
Figure 1.1.4. ROM expansion
The M16C/61 group products currently supported are listed in Table 2.
ROM
Size(Byte)
External
ROM
128 K
96 K
64 K
32 K
M30610M8A-XXXFP/GP
M30612M8A-XXXFP/GP
M30610MAA-XXXFP/GP
M30612MAA-XXXFP/GP
M30610MCA-XXXFP/GP
M30612MCA-XXXFP/GP
Mask ROM version One-time PROM version EPROM version External ROM version
M30612E4FP/GP
M30610ECFP/GP M30610ECFS
M30612SAFP/GP
M30610SAFP/GP
M30612M4A-XXXFP/GP
RAM capacityROM capacity Package type RemarksType No
M30612M4A-XXXFP 32K byte 4K byte 100P6S-A
Mask ROM version
M30612M4A-XXXGP 100P6Q-A
M30612M8A-XXXFP 64K byte 4K byte 100P6S-A
M30612M8A-XXXGP 100P6Q-A
M30610MAA-XXXFP
96K byte 10K byte 100P6S-A
M30612MAA-XXXFP 4K byte 100P6S-A
128K byte
M30610MCA-XXXFP 10K byte 100P6S-A
M30612MCA-XXXFP 5K byte 100P6S-A
One-time PROM version
32K byte 4K byte
M30612E4FP 100P6S-A
M30612E4GP 100P6Q-A
EPROM version (Note)
10K byteM30610ECFS 128K byte 100D0
10K byte
M30610SAFP 100P6S-A
External ROM version
M30610SAGP 100P6Q-A
Apr. 1999
M30610MAA-XXXGP 100P6Q-A
M30612MAA-XXXGP 100P6Q-A
M30610MCA-XXXGP
M30610ECFP 128K byte 10K byte 100P6S-A
M30610ECGP 100P6Q-A
M30612MCA-XXXGP 100P6Q-A
100P6Q-A
Note: Do not use the EPROM version for mass production, because it is a tool for program development
(for evaluation).
4K byte
M30612SAFP 100P6S-A
M30612SAGP 100P6Q-A
M30610M8A-XXXFP
M30610M8A-XXXGP
100P6S-A
100P6Q-A
10K byte
Table 1.1.2. M16C/61 group
7
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Package type:
FP : Package 100P6S-A
GP : 100P6Q-A
FS : 100D0
ROM No.
Omitted for blank one-time PROM version
and EPROM version
ROM capacity:
4 : 32K bytes A : 96K bytes
8 : 64K bytes C : 128K bytes
Memory type:
M : Mask ROM version
E : EPROM or one-time PROM version
S : External ROM version
Type No. M 3 0 6 1 2 M 4 – X X X F P
M16C/61 Group
M16C Family
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
Figure 1.1.5. Type No., memory size, and package
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
8
Pin Description
VCC, VSS
CNVSS
XIN
XOUT
BYTE
AVCC
AVSS
VREF
P00 to P07
D0 to D7
P10 to P17
D8 to D15
P20 to P27
A0 to A7
A0/D0 to
A7/D7
A0, A1/D0
to A7/D6
P30 to P37
A8 to A15
A8/D7,
A9 to A15
P40 to P47
Signal name
Power supply
input
CNVSS
Reset input
Clock input
Clock output
External data
bus width
select input
Analog power
supply input
Reference
voltage input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
Function
This pin switches between processor modes. Connect it to the
VSS pin when operating in single-chip or memory expansion mode.
Connect it to the VCC pin when in microprocessor mode.
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
XOUT pin open.
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. When
operating in single-chip mode,connect this pin to VSS.
This pin is a power supply input for the A-D converter. Connect this
pin to VCC.
This pin is a power supply input for the A-D converter. Connect this
pin to VSS.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When used for input in single-chip mode, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. In memory expansion and microprocessor modes, selection
of the internal pull-resistor is not available.
When set as a separate bus, these pins input and output data (D0–D7).
This is an 8-bit I/O port equivalent to P0.
When set as a separate bus, these pins input and output data
(D
8
–D
15
).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 low-order address bits (A0–A7).
If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D0–D7) and output 8 low-order address bits
(A0–A7) separated in time by multiplexing.
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D0–D6) and output address (A1–A7) separated
in time by multiplexing. They also output address (A0).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 middle-order address bits (A8–A15).
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D7) and output address (A8) separated in time
by multiplexing. They also output address (A9–A15).
This is an 8-bit I/O port equivalent to P0.
Pin name
Input
Input
Input
Output
Input
Input
Input/output
Input/output
Input/output
Input/output
I/O type
Analog power
supply input
Input/output
Output
Input/output
Output
Input/output
Input/output
Output
Input/output
Output
Input/output
Output
Output
CS0 to CS3,
A16 to A19 These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip
select signals used to specify an access space. A16–A19 are 4 high-
order address bits.
RESET
Pin Description
9
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Signal name FunctionPin name I/O type
I/O port P5 Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input
Input/output
Input/output
I/O port P6
I/O port P7
I/O port P8
I/O port P85
I/O port P9
I/O port P10
P50 to P57
P60 to P67
P70 to P77
P80 to P84,
P86,
P87,
P85
P90 to P97
P100 to P107
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
Output
Output
Output
Output
Output
Input
Output
Input
This is an 8-bit I/O port equivalent to P0. When used for input in single-
chip, memory expansion, and microprocessor modes, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. Pins in this port also function as UART0 and UART1 I/O pins
as selected by software.
This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel
open-drain output). Pins in this port also function as timer A0–A3 or
UART2 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as Timer B0–B2 input pins, D-A converter output pins, A-D converter
extended input pins, or A-D trigger input pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins. Furthermore, P104–P107 also function as
input pins for the key input interrupt function.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state.
P80 to P84, P86, and P87 are I/O ports with the same functions as P6.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P86 and P87 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P86 (XCOUT
pin) and P87 (XCIN pin). P85 is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.
10
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M16C/61 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit,
A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.4.1 is a memory map of the M16C/61 group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30612M4A-XXXFP,
there is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as
_______
the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is
stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the
internal register (INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30612M4A-XXXFP, 4K bytes of internal RAM is mapped
to the space from 0040016 to 013FF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. For example, in the M30612M4A-XXXFP, the following spaces cannot be used.
• The space between 0140016 and 03FFF16
• The space between D000016 and F7FFF16 (When external area do not expand in memory expansion
mode)
Do not expand the external area in single chip mode. A part of internal memory cannot be used depending
on MCU.
Figure 1.4.1. Memory map
00000
16
YYYYY
16
FFFFF
16
00400
16
04000
16
XXXXX
16
D0000
16
AAAAA
A
AAA
A
A
AAA
A
AAAAA
External area
Internal ROM area
SFR area
For details, see Figure
1.7.1 and Figure 1.7.2
Internal RAM area
Internal reserved
area (Note 1)
Internal reserved
area (Note 2)
FFE00
16
FFFDC
16
FFFFF
16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: When external area do not expand in memory expansion mode.
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
Reset
Special page
vector table
DBC
NMI
Type No. Address YYYYY
16
Address XXXXX
16
M30612M4A/E4
F0000
16
02BFF
16
E0000
16
02BFF
16
M30612M8A F8000
16
013FF
16
M30612MAA
M30612MCA
F0000
16
013FF
16
M30610M8A
M30610MCA/EC
E8000
16
013FF
16
E0000
16
017FF
16
E8000
16
02BFF
16
M30610MAA
11
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
AAAAAAA
AAAAAAA
HL
b15 b8 b7 b0
R0
(Note)
AAAAAAA
HL
b15 b8 b7 b0
R1
(Note)
R2
(Note)
AAAAAAA
AAAAAAA
b15 b0
R3
(Note)
AAAAAAA
AAAAAAA
b15 b0
A0
(Note)
AAAAAAA
AAAAAAA
b15 b0
A1
(Note)
AAAAAAA
AAAAAAA
b15 b0
FB
(Note)
AAAAAAA
b15 b0
Data
registers
Address
registers
Frame base
registers
b15 b0
b15 b0
b15 b0
b15 b0
b0
b19
b0
b19
HL
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
Note: These re
g
isters consist of two re
g
ister banks.
A
A
AA
AA
AA
AA
A
A
AAAAAAA
AAAAAAA
A
A
AA
AA
AA
AA
AA
AA
A
A
CDZSBOIU
IPL
Figure 1.5.1. Central processing unit register
12
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to
“1”
when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”
.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
13
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
Figure 1.5.2. Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register (FLG)
AA
AA
AA
AA
A
A
AA
AA
AAAAAAA
AAAAAAA
AA
AA
AA
AA
AA
AA
A
A
AA
AA
CDZSBOIU
IPL
b0b15
14
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Figure 1.6.2. Reset sequence
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence.
Figure 1.6.1. Example reset circuit
BCLK
Address
Address
Address
Microprocessor
mode BYTE = “H”
Microprocessor
mode BYTE = “L”
Content of reset vector
Single chip
mode
BCLK 24cycles
FFFFC
16
FFFFD
16
FFFFE
16
Content of reset vector
FFFFC
16
FFFFE
16
Content of reset vector
FFFFE
16
X
IN
RESET
RD
WR
CS0
RD
WR
CS0
FFFFC
16
More than 20 cycles are needed
RESET V
CC
0.8V
RESET
V
CC
0V
0V
5V
5V
4.0V
Example when V
CC
= 5V
.
15
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
____________
Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figure 1.6.3 shows the
internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.6.1. Pin status when RESET pin level is “L”
Status
CNVSS = VCC
CNVSS = VSS BYTE = VSS BYTE = VCC
Pin name
P0
P1
P2, P3, P40 to P43
P44
P45 to P47
P50
P51
P52
P53
P54
P55
P56
P57
P6, P7, P80 to P84,
P86, P87, P9, P10
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Data input (floating)
Data input (floating)
Address output (undefined)
BCLK output
ALE output (“L” level is output)
CS0 output (“H” level is output)
WR output (“H” level is output)
RD output (“H” level is output)
RDY input (floating)
Input port (floating)
BCLK output
BHE output (undefined)
HLDA output (The output value
depends on the input to the
HOLD pin)
HOLD input (floating)
Data input (floating)
Address output (undefined)
CS0 output (“H” level is output)
Input port (floating)
Input port (floating) Input port (floating)
RDY input (floating)
ALE output (“L” level is output)
HOLD input (floating)
HLDA output (The output value
depends on the input to the
HOLD pin)
RD output (“H” level is output)
BHE output (undefined)
WR output (“H” level is output)
Input port (floating)
16
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Figure 1.6.3. Device's internal status after a reset is cleared
(1) Processor mode register 0 (Note)
(2) Processor mode register 1
(3) System clock control register 0
(4) System clock control register 1
(5) Chip select control register
(6) Address match interrupt enable register
(7) Protect register
(8) Watchdog timer control register
(9) Address match interrupt register 0
(10)Address match interrupt register 1
(11)DMA0 control register
(12)DMA1 control register
(13)Bus collision detection interrupt control
register
(14)DMA0 interrupt control register
(15)DMA1 interrupt control register
(16)Key input interrupt control register
(17)A-D conversion interrupt control register
(18)UART2 transmit interrupt control register
(19)UART2 receive interrupt control register
(20)UART0 transmit interrupt control register
(21)UART0 receive interrupt control register
(22)UART1 transmit interrupt control register
(23)UART1 receive interrupt control register
(24)Timer A0 interrupt control register
(25)Timer A1 interrupt control register
(26)Timer A2 interrupt control register
(27)Timer A3 interrupt control register
(28)Timer A4 interrupt control register
(29)Timer B0 interrupt control register
(30)Timer B1 interrupt control register
(31)Timer B2 interrupt control register
(32)INT0 interrupt control register
(33)INT1 interrupt control register
(34)INT2 interrupt control register
(35)UART2 transmit/receive mode register
(36)UART2 transmit/receive control register 0
(37)UART2 transmit/receive control register 1
(38)Count start flag
(39)
One-shot start flag(40)
Trigger select flag
Up-down flag(42)
Timer A0 mode register(43)
Timer A1 mode register(44)
Timer A2 mode register
(47)
Timer B0 mode register(48)
Timer B1 mode register(49)
Timer B2 mode register(50)
UART0 transmit/receive mode register(51)
UART0 transmit/receive control register 0(52)
UART0 transmit/receive control register 1(53)
UART1 transmit/receive mode register(54)
UART1 transmit/receive control register 0(55)
UART1 transmit/receive control register 1(56)
UART transmit/receive control register 2(57)
DMA0 cause select register(58)
DMA1 cause select register(59)
A-D control register 2(60)
A-D control register 0(61)
A-D control register 1(62)
D-A control register(63)
Port P0 direction register(64)
Port P1 direction register(65)
Port P2 direction register(66)
Port P3 direction register(67)
Port P4 direction register(68)
Port P5 direction register(69)
Port P6 direction register(70)
Port P7 direction register(71)
Port P8 direction register(72)
Port P9 direction register(73)
Port P10 direction register(74)
Pull-up control register 0(75)
Pull-up control register 1(76)
Pull-up control register 2(77)
Data registers (R0/R1/R2/R3)(78)
Address registers (A0/A1)(79)
Frame base register (FB)(80)
Interrupt table register (INTB)(81)
User stack pointer (USP)(82)
Interrupt stack pointer (ISP)(83)
Static base register (SB)(84)
Flag register (FLG)
(45)
Timer A3 mode register(46)
(039616)···
(039716)···
(039816)···
(039B16)···
(039C16)···
(039D16)···
(03A016)···
(03A416)···
(03A516)···
(03A816)···
(03AC16)···
(03AD16)···
(03B016)···
(03B816)···
(03BA16)···
(03D416)···
(03D616)···
(03D716)···
(03DC16)···
(03E216)···
(03E316)···
(03E616)···
(03E716)···
(03EA16)···
(03EB16)···
(03EE16)···
(03EF16)···
(03F216)···
(03F316)···
(03F616)···
(03FC16)···
(03FD16)···
(03FE16)···
(039916)···
(039A16)···Timer A4 mode register
x : Nothing is mapped to this bit
? : Undefined
(85)
(000416)···
(000516)···
(000616)···
(000716)···
(000816)···
(000916)···
(000A16)···
(000F16)···
(001016)···
(001116)···
(001216)···
(001416)···
(001516)···
(001616)···
(002C16)···
(003C16)···
(004A16)···
(004B16)···
(004C16)···
(004D16)···
(004E16)···
(004F16)···
(005016)···
(005116)···
(005216)···
(005316)···
(005416)···
(005516)···
(005616)···
(005716)···
(005816)···
(005916)···
(005A16)···
(005B16)···
(005C16)···
(005D16)···
(005E16)···
(005F16)···
(037816)···
(037C16)···
(037D16)···
(038016)···
(038216)···
(038316)···
(038416)···
(038116)···Clock prescaler reset flag
(41)
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
0
0
0
0016
0016
0016
0016
0016
0? 0000
00? 0000
00? 0000
0016
000 1000
000 0010
0
0
0016
000 1000
000 0010
0
0
000000
0016
0016
000 0???0
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
000016
000016
000016
0000016
000016
000016
000016
000016
00 00000
0
1
0
0
0
0
0
0016
00
0000100
00010000
00000010
0
0
0
00?0????
0016
0016
000
0
0016
0016
000
0000?00
00000?00
000
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
?000
?000
?000
0016
00000001
01000000
0016
000000
0016
0016
00
00
00
?
0
0000
17
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
INT1 interrupt control register (INT1IC)
Timer B0 interrupt control register (TB0IC)
Timer B2 interrupt control register (TB2IC)
Timer A1 interrupt control register (TA1IC)
Timer A3 interrupt control register (TA3IC)
UART0 transmit interrupt control register (S0TIC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Timer B1 interrupt control register (TB1IC)
Timer A0 interrupt control register (TA0IC)
Timer A2 interrupt control register (TA2IC)
Timer A4 interrupt control register (TA4IC)
UA R T 0 re c e ive in te rrup t c o n trol re g iste r (S 0 RIC)
UART1 transmit interrupt control register (S1TIC)
UA R T 1 re c e ive in te rrup t c o n trol re g iste r (S 1 RIC)
DMA1 interrupt control register (DM1IC)
DMA0 interrupt control register (DM0IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
DMA0 control register (DM0CON)
DMA0 source pointer (SAR0)
DMA0 transfer counter (TCR0)
DMA0 destination pointer (DAR0)
DMA1 control register (DM1CON)
DMA1 source pointer (SAR1)
DMA1 transfer counter (TCR1)
DMA1 destination pointer (DAR1)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Chip select control register (CSR)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Processor mode register 1(PM1)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Bus collision detection interrupt control register (BCNIC)
UART2 receive buffer register (U 2RB )
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive mode register (U 2M R)
UART2 transmit/receive control register 1 (U2C1)
UART2 bit rate generator (U2BRG)
UART2 transmit interrupt control register (S2TIC)
UA R T 2 re c e ive in te rrup t c o n trol re g iste r (S 2 RIC)
Figure 1.7.1. Location of peripheral unit control registers
18
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
Figure 1.7.2. Location of peripheral unit control registers
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
03D5
16
03D6
16
03D7
16
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
03FD
16
03FE
16
03FF
16
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
DMA1 cause select register (DM1SL)
DMA0 cause select register (DM0SL)
Port P0 (P0)
Port P0 direction register (PD0)
Port P1 (P1)
Port P1 direction register (PD1)
Port P2 (P2)
Port P2 direction register (PD2)
Port P3 (P3)
Port P3 direction register (PD3)
Port P4 (P4)
Port P4 direction register (PD4)
Port P5 (P5)
Port P5 direction register (PD5)
Port P6 (P6)
Port P6 direction register (PD6)
Port P7 (P7)
Port P7 direction register (PD7)
Port P8 (P8)
Port P8 direction register (PD8)
Port P9 (P9)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
A-D register 7 (AD7)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
D-A register 1 (DA1)
D-A control register (DACON)
UART0 transmit/receive mode register (U0MR)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
Timer A0 (TA0)
Timer A1 (TA1)
Timer A2 (TA2)
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
Count start flag (TABSR)
One-shot start flag (ONSF)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
Up-down flag (UDF)
Timer A3 (TA3)
Timer A4 (TA4)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Trigger select register (TRGSR)
UART0 bit rate generator (U0BRG)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 bit rate generator (U1BRG)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART transmit/receive control register 2 (UCON)
CRC data register (CRCD)
CRC input register (CRCIN)
Clock prescaler reset flag (CPSRF)
A-D control register 2 (ADCON2)
19
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus ControlSoftware Reset
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.8.1 shows the processor mode register 0 and 1. Figure 1.9.1 shows the memory maps appli-
cable for each of the modes.
20
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus ControlProcessor Mode
Figure 1.8.1. Processor mode register 0 and 1
Processor mode register 0 (Note 1)
Symbol Address When reset
PM0 0004
16
00
16
(Note 2)
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
1 1: Microprocessor mode
b1 b0
PM03
PM01
PM00
Processor mode bit
PM02
R/W mode select bit
0 : RD,BHE,WR
1 : RD,WRH,WRL
Software reset bit
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
PM04 0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
b5 b4
Multiplexed bus space
select bit
PM05
PM06
PM07
Port P4
0
to P4
3
function
select bit (Note 3) 0 : Address output
1 : Port function
(Address is not output)
BCLK output disable bit 0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new
values to this register.
Note 2: If the V
CC
voltage is applied to the CNV
SS
, the value of this register when
reset is 03
16.
(PM00 and PM01 both are set to “1”.)
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose
an 8-bit width.The processor operates using the separate bus after reset is
revoked, so the entire space multiplexed bus cannot be chosen in microprocessor
mode.
The higher-order address becomes a port if the entire space multiplexed
bus is chosen, so only 256 bytes can be used in each chip select.
Processor mode register 1 (Note 1)
Symbol Address When reset
PM1 0005
16
00XXXXX0
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
PM16
External memory area
expansion bit (Note 2) 0 : Do not expand
1 : Expand
Reserved bit Must always be set to “0”
0
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” when writing
new values to this register.
Note 2: When this bit is set to “1” in memory expansion mode, M30612M4A/E4
provides the means of using part of internal reserved area as an external
area. Set this bit to “0” except M30612M4A/E4. Set this bit to “0” in single
chip mode.
PM17
Wait bit 0 : No wait state
1 : Wait state inserted
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
Reserved bit Must always be set to “0”
A
AA
000
21
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Single-chip mode
SFR area
Internal RAM
area
Inhibited
Internal ROM
area (Note 2)
Memory expansion mode
AAAA
AAAA
AAAA
SFR area
Internal RAM
area
External area
Internal ROM
area
Internally reserved
area (Note 1)
Internally
reserved area
Microprocessor mode
AAA
AAA
AAA
AAA
AAA
AAA
SFR area
Internal RAM
area
External area
Internally
reserved area
0000016
0040016
XXXXX16
YYYYY16
FFFFF16
D000016
External area : Accessing this area allows the user to
access a device connected externally
to the microcomputer.
Note 1: This area becomes external area when PM16 (external
memory area expansion bit ) = “1” in M30612M4A/E4.
Set “0” except M30612M4A/E4.
Note 2: Set “0” to PM16 (external memory area expansion bit)
in single chip mode.
0400016
Type No. Address
YYYYY16
Address
XXXXX16
M30612M4A/E4
F00001602BFF16
E00001602BFF16
M30612M8A F800016013FF16
M30612MAA
M30612MCA
F000016013FF16
M30610M8A
M30610MCA/EC
E800016013FF16 E000016017FF16
E80001602BFF16M30610MAA
Processor Mode
Figure 1.9.1. Memory maps in each processor mode
22
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Table 1.10.1. Factors for switching bus settings
Bus Settings
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus
settings.
Table 1.10.1 shows the factors used to change the bus settings.
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0
is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address
bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set
to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the
address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin =
“H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8.
D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are
mapped to the microcomputer’s even addresses (every 2nd address). To access these external de-
vices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before using the multiplex bus for access, be sure to insert a software wait.
If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed
bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256
bytes can be used in each chip select.
Bus setting Switching factor
Switching external address bus width Bit 6 of processor mode register 0
Switching external data bus width BYTE pin
Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
23
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Table 1.10.2. Pin functions for each processor mode
P0
0
to P0
7
I/O port Data bus Data bus Data bus Data bus I/O port
Either CS1 or CS2 is for
multiplexed bus and others
are for separate bus (separate bus)
multiplexed
bus for the
entire
space
Single-chip
mode Memory expansion mode/microprocessor modes
Memory
expansion mode
Data bus width
BYTE pin level
Port P4
0
to P4
3
function select bit = 0
“01”, “10” “00” “11” (Note 1)
8 bit
“H”
8 bits
“H”
16 bits
“L”
8 bits
“H” 16 bits
“L”
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be
chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
Note 2: Address bus when in separate bus mode.
Processor mode
Multiplexed bus
space select bit
CS (chip select) or programmable I/O port
(For details, refer to “Bus control”)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”)
Port P4
0
to P4
3
function select bit = 1
P1
0
to P1
7
I/O port I/O port Data bus I/O port Data bus I/O port
P2
1
to P2
7
I/O port
Address bus Address bus
Address bus Address bus Address bus
/data bus
(Note 2)
/data bus
(Note 2)
/data bus
P2
0
I/O port
Address bus
Address bus Address bus Address bus Address bus
/data bus
(Note 2)
/data bus
P3
0
I/O port Address bus
Address bus
Address bus Address bus A
8
/D
7
/data bus
(Note 2)
P3
1
to P3
7
I/O port Address bus Address bus Address bus Address bus I/O port
P4
0
to P4
3
I/O port I/O port I/O port /O port I/O port I/O port
P4
0
to P4
3
I/O port Address bus Address bus Address bus Address bus I/O port
P4
4
to P4
7
I/O port
P5
0
to P5
3
I/O port
P5
4
I/O port HLDA HLDA HLDA HLDA HLDA
P5
5
I/O port HOLD HOLD HOLD HOLD HOLD
P5
6
I/O port ALE ALE ALE ALE ALE
P5
7
I/O port RDY RDY RDY RDY RDY
Bus Settings
24
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
W
Function
Bit symbol
Bit name
Chip select control register
Symbol Address When reset
CSR 0008
16
01
16
R
b7 b6 b5 b4 b3 b2 b1 b0
CS1
CS0
CS3
CS2
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS1W
CS0W
CS3W
CS2W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
A
AA
AA
Figure 1.11.1. Chip select control register
Table 1.11.1. External areas specified by the chip select signals
Chip select Specified address range
Memory expansion mode Microprocessor mode
30000
16
to CFFFF
16
(640K) (Note)
CS0
CS1
CS2
CS3
28000
16
to 2FFFF
16
(32K)
08000
16
to 27FFF
16
(128K)
04000
16
to 07FFF
16
(16K)
30000
16
to FFFFF
16
(832K)
28000
16
to 2FFFF
16
(32K)
08000
16
to 27FFF
16
(128K)
04000
16
to 07FFF
16
(16K)
30000
16
to F7FFF
16
(800K)
Note: When PM16 (External memory area expansion bit) = “1”. (Only M30612M4A/E4 is valid.)
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as
the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
Both the address and data bus retain their previous states when internal ROM or RAM is accessed. Also,
when a change is made from single-chip mode to memory expansion mode, the value of the address bus
is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register. _______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been cancelled.
_______ _______ _______ _______
CS1 to CS3 function as input ports. Therefore, when using CS1 to CS3, external pull-up resistors are
required. Figure 1.11.1 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 1.11.1
shows the external memory areas specified using the chip select signal.
25
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
_____ ______ ________
Table 1.11.3. Operation of RD, WR, and BHE signals
Status of external data bus
RD BHEWR
HLL
LHL
HLH
LHH
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Data bus width A0
H
H
L
L
HLLL
LHLL
HL H / L
LH H / L
8-bit (BYTE = “H”)
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
16-bit
(BYTE = “L”)
Not used
Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRHWRLRD
Data bus width
16-bit
(BYTE = “L”) H
H
H
H
L
H
L
H
H
L
L
L
_____ ________ _________
Table 1.11.2. Operation of RD, WRL, and WRH signals
Figure 1.11.2. ALE signal and address/data bus
When BYTE pin = “H” When BYTE pin = “L”
ALE
Address Data (Note 1)
Address (Note 2)
D
0
/A
0
to D
7
/A
7
A
8
to A
19
ALE
Address Data (Note 1)
Address
D
0
/A
1
to D
7
/A
8
A
9
to A
19
Address
A
0
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
_____ ________ ______ _____ ________ _________
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
_____ ______ _______
pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 1.11.2 and 1.11.3 show the operation of these signals.
_____ ______ ________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________ _________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
26
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
_____ ________
Figure 1.11.3. Example of RD signal extended by RDY signal
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
AAAA
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
AAAAAA
AA
AA
In an instance of separate bus
In an instance of multiplexed bus
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
Accept timing of RDY signal
________
(5) The RDY signal
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in
________
Figure 1.11.3, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state.
________
If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table
1.11.4 shows the state of the microcomputer with the bus in the wait state, and Figure 1.11.3 shows an
____ ________
example in which the RD signal is prolonged by the RDY signal.
________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
________
chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to all
________
bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as
properly as in non-using.
Table 1.11.4. Microcomputer status in ready state (Note)
Item Status
Oscillation On
___ _____
R/W signal, address bus, data bus, CS ________
Maintain status when RDY signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits On
________
Note: The RDY signal cannot be received immediately prior to a software wait.
27
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Table 1.11.5. Microcomputer status in hold state
Item Status
Oscillation ON
___ _____ _______
R/W signal, address bus, data bus, CS, BHE Floating
Programmable I/O ports P0, P1, P2, P3, P4, P5 Floating
P6, P7, P8, P9, P10 Maintains status when hold signal is received
__________
HLDA Output “L”
Internal peripheral circuits ON (but watchdog timer stops)
ALE signal Undefined
__________
HOLD > DMAC > CPU
Figure 1.11.4. Bus-using priorities
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________ __________
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.11.5
shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
(7) External bus status when the internal area is accessed
Table 1.11.6 shows the external bus status when the internal area is accessed.
Table 1.11.6. External bus status when the internal area is accessed
Item SFR accessed Internal ROM/RAM accessed
Address bus Address output Maintain status before accessed
address of external area
Data bus When read Floating Floating
When write Output data Undefined
RD, WR, WRL, WRH RD, WR, WRL, WRH output Output "H"
BHE BHE output Maintain status before accessed
status of external area
CS Output "H" Output "H"
ALE Output "L" Output "L"
28
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Area Bus status Wait bit Bits 4 to 7 of chip select
control register Bus cycle
Invalid1 2 BCLK cycles
External
memory
area
Separate bus 0 1 1 BCLK cycle
Separate bus 0 0 2 BCLK cycles
Separate bus 1 0 (Note) 2 BCLK cycles
Multiplex bus 0 0 3 BCLK cycles
Multiplex bus 1 3 BCLK cycles0 (Note)
SFR
Internal
ROM/RAM 0 Invalid 1 BCLK cycle
Invalid Invalid 2 BCLK cycles
Note: When using the RDY signal, always set to “0”.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 1.11.7. Software waits and bus cycles
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).
When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When
set to “1”, a wait is applied to all memory areas (two or three BCLK
cycles), regardless of the contents of bits 4 to 7 of the chip select control register
. Set this bit after referring
to the recommended operating conditions (main clock input oscillation frequency) of the electric character-
________
istics.
However, when the user is using the RDY signal, the relevant bit in the chip select control register’s
bits 4 to 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______ _______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
insert a software wait if using the multiplex bus to access the external memory area.
Table 1.11.7 shows the software wait and bus cycles. Figure 1.11.5 shows example bus timing when
using software waits.
29
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Figure 1.11.5. Typical bus timings using software wait
Output Input
Address Address
Bus cycle
< Separate bus (with wait) >
BCLK
Read signal
Write signal
Data bus
Address bus
Chip select
BCLK
Read signal
Address bus/
Data bus
Chip select
Address
Address
Address bus
Data output
Address
Address
Input
ALE
Bus cycle
< Multiplexed bus >
Write signal
BCLK
Read signal
Write signal
Address bus Address Address
Bus cycle
< Separate bus (no wait) >
Output
Data bus
Chip select
Input
30
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.12.2. Examples of sub-clock
Table 1.12.1. Main clock and sub-clock generating circuits
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Example of oscillator circuit
Figure 1.12.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.12.2 shows some examples
of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.12.1 and 1.12.2 vary with each oscillator used. Use
the values recommended by the manufacturer of your oscillator.
Figure 1.12.1. Examples of main clock
Main clock generating circuit Sub-clock generating circuit
Use of clock • CPU’s operating clock source • CPU’s operating clock source
• Internal peripheral units’ • Timer A/B’s count clock
operating clock source source
Usable oscillator Ceramic or crystal oscillator Crystal oscillator
Pins to connect oscillator XIN, XOUT XCIN, XCOUT
Oscillation stop/restart function Available Available
Oscillator status immediately after reset
Oscillating Stopped
Other Externally derived clock can be input
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
Externally derived clock
Open
Vcc
Vss
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
R
d
C
IN
C
OUT
(Note)
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
IN
and X
OUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
X
CIN
X
COUT
Externally derived clock
Open
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
CIN
and X
COUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
X
CIN
X
COUT
(Note)
C
CIN
C
COUT
R
Cd
31
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Control
Figure 1.12.3 shows the block diagram of the clock generating circuit.
Sub clock
CM04
f
C32
CM0i : Bit i at address 0006
16
CM1i : Bit i at address 0007
16
WDCi : Bit i at address 000F
16
X
CIN
CM10 “1”
Write signal
1/32
X
COUT
Q
S
R
WAIT instruction
X
OUT
Main clock
CM05
f
C
CM02
f
1
QS
R
NMI
Interrupt request
level judgment
output
RESET
Software reset f
C
CM07=0
CM07=1
f
AD
AAA
AAA
Divider
ad
1/2 1/2 1/2 1/2
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=10
CM06=1
CM06=0
CM17,CM16=11
d
a
Details of divider
X
IN
f
8
f
32
c
b
b
1/2
c
f
32
SIO2
f
8
SIO2
f
1
SIO2
BCLK
Figure 1.12.3. Clock generating circuit
32
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-
tained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expan-
sion and the microprocessor modes.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
33
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.12.4 shows the system clock control registers 0 and 1.
Figure 1.12.4. Clock control registers 0 and 1
System clock control register 0 (Note 1)
Symbol Address When reset
CM0 0006
16
48
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : I/O port P5
7
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bit
(Valid only in single-chip
mode)
WAIT peripheral function
clock stop bit 0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN
-X
COUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
Port X
C
select bit 0 : I/O port
1 : X
CIN
-X
COUT
generation
Main clock (X
IN
-X
OUT
)
stop bit (Note 3, 4, 5) 0 : On
1 : Off
Main clock division select
bit 0 (Note 7) 0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Note 6) 0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with X
IN
, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, X
OUT
turns “H”. The built-in feedback resistor remains being connected, so X
IN
turns
pulled up to X
OUT
(“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: f
C32
is not included.
System clock control register 1 (Note 1)
Symbol Address When reset
CM1 0007
16
20
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit
(Note4) 0 : Clock on
1 : All clocks off (stop mode)
Note 1: Set bit 0 of the protect register (address 000A
16
) to
“1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006
16
) is
“0”. If
“1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, X
OUT
turns “H”, and the built-in feedback resistor is cut off. X
CIN
and X
COUT
turn high-
impedance state.
CM15 X
IN
-X
OUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
WR
WR
CM16
CM17
Reserved bit Always set to
“0”
Reserved bit Always set to
“0”
Main clock division
select bit 1 (Note 3) 0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
00
Reserved bit Always set to
“0”
Reserved bit Always set to
“0”
00
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
34
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______
Address bus, data bus, CS0 to CS3
Retains status before stop mode
_____ ______ ________ ________ _________
RD, WR, BHE, WRL, WRH “H”
__________
HLDA, BCLK “H”
ALE “H”
Port
Retains status before stop mode
Retains status before stop mode
CLKOUT When fC selected Valid only in single-chip mode “H”
When f8, f32 selected Valid only in single-chip mode
Retains status before stop mode
Table 1.12.2. Port status during stop mode
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fC to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation, BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 1.12.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
35
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Table 1.12.3. Port status during wait mode
Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______
Address bus, data bus, CS0 to CS3
Retains status before wait mode
_____ ______ ________ ________ _________
RD, WR, BHE, WRL, WRH “H”
__________
HLDA,BCLK “H”
ALE “H”
Port
Retains status before wait mode Retains status before wait mode
CLKOUT When fC selected Valid only in single-chip mode Does not stop
When f8, f32 selected Valid only in single-chip mode Does not stop when the WAIT
peripheral function clock stop
bit is “0”.
When the WAIT peripheral
function clock stop bit is “1”,
the status immediately prior
to entering wait mode is main-
tained.
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function
clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. Table 1.12.3 shows the status of the ports in wait
mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Wait Mode
36
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
01000Invalid Division by 2 mode
10000Invalid Division by 4 mode
Invalid Invalid 0 1 0 Invalid Division by 8 mode
11000Invalid Division by 16 mode
00000Invalid No-division mode
Invalid Invalid 1 Invalid 0 1 Low-speed mode
Invalid Invalid 1 Invalid 1 1 Low power dissipation mode
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.13.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK
Table 1.12.4. Operating modes dictated by settings of system clock control registers 0 and 1
Status Transition Of BCLK
37
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the internal clock selected. Each peripheral function oper-
ates according to its assigned clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fC clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 1.12.5 is the state transition diagram of the above modes.
Power control
38
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Power control
Transition of stop mode, wait mode
Transition of normal mode
Reset
Medium-speed mode
(divided-by-8 mode)
Interrupt
CM10 = “1”
All oscillators stopped CPU operation stopped
Medium-speed mode
(divided-by-8 mode)
BCLK : f(X
IN
)/8
CM07 = “0” CM06 = “1”
Low-speed mode
High-speed mode
Main clock is oscillating
Sub clock is stopped
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is oscillating
Low power dissipation mode
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
Normal mode
Stop mode
Stop mode
Stop mode
All oscillators stopped
All oscillators stopped
Wait mode
Wait mode
Wait mode
CPU operation stopped
CPU operation stopped
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
CM10 = “1”
Interrupt
Interrupt
CM10 = “1”
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0” BCLK : f(X
IN
)/8
Medium-speed mode
(divided-by-8 mode)
CM07 = “0”
CM06 = “1”
High-speed mode
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(X
CIN
)
CM07 = “1”
BCLK : f(X
CIN
)
CM07 = “1”
Main clock is oscillating
Sub clock is oscillating
CM07 = “0”
(Note 1, 3)
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM07 = “1”
(Note 2)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
CM07 = “1” (Note 2)
CM05 = “1”
CM05 = “0” CM05 = “1”
CM04 = “0” CM04 = “1”
CM06 = “0”
(Notes 1,3)
CM06 = “1”
CM04 = “0” CM04 = “1”
(Notes 1, 3)
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
(Refer to the following for the transition of normal mode.)
Figure 1.12.5. State transition diagram of Power control mode
39
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.12.6 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 000716) and port P9 direction register
(address 03F316) can only be changed when the respective bit in the protect register is set to “1”. There-
fore, important outputs can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
Symbol Address When reset
PRCR 000A16 XXXXX0002
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC0
PRC2
Enables writing to processor mode
registers 0 and 1 (addresses 0004
16
and 0005
16
)
Function
0 : Write-inhibited
1 : Write-enabled
Enables writing to system clock
control registers 0 and 1 (addresses
0006
16
and 0007
16
)
Enables writing to port P9 direction
register (address 03F3
16
) (Note)0 : Write-inhibited
1 : Write-enabled
WR
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
A
AA
A
A
AA
AA
A
AA
Figure 1.12.6. Protect register
Protection
40
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Figure 1.13.1. Classification of interrupts
Interrupt
Software
Hardware
Special
Peripheral I/O (Note)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
_______
NMI
________
DBC
Watchdog timer
Single step
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Overview of Interrupt
Type of Interrupts
Figure 1.13.1 lists the types of interrupts.
41
Interrupt
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing
the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts,
so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-
quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset ____________
Reset occurs if an “L” is input to the RESET pin.
_______
• NMI interrupt
_______ _______
An NMI interrupt occurs if an “L” is input to the NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs. For address match interrupt, see 2.11 Address match Interrupt.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• Key-input interrupt ___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1 and UART2 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1 and UART2 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B2 interrupt
These are interrupts that timer B generates.
________ ________
• INT0 interrupt through INT2 interrupt
______ ______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
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Interrupt
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt source Vector table addresses Remarks
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction
BRK instruction FFFE416 to FFFE716
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
Address match FFFE816 to FFFEB16 There is an address-matching interrupt enable bit
Single step (Note) FFFEC16 to FFFEF16 Do not use
Watchdog timer FFFF016 to FFFF316
________
DBC (Note) FFFF416 to FFFF716 Do not use
NMI FFFF816 to FFFFB16 _______
External interrupt by input to NMI pin
Reset FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
Figure 1.13.2. Format for specifying interrupt vector addresses
AAAAAAAA
AAAAAAAA
Mid address
AAAAAAAA
AAAAAAAA
Low address
AAAAAAAA
AAAAAAAA
0 0 0 0 High address
AAAAAAAA
AAAAAAAA
0 0 0 0 0 0 0 0
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
MSB
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.13.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.13.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.13.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
44
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Table 1.13.2. Interrupts assigned to the variable vector tables and addresses of vector tables
AAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAA
Software interrupt number Interrupt source
Vector table address
Address (L) to address (H)
Remarks
Cannot be masked I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0
+44 to +47 (Note) DMA0Software interrupt number 11
+48 to +51 (Note) DMA1Software interrupt number 12
+52 to +55 (Note) Key input interruptSoftware interrupt number 13
+56 to +59 (Note) A-DSoftware interrupt number 14
+68 to +71 (Note) UART0 transmitSoftware interrupt number 17
+72 to +75 (Note) UART0 receiveSoftware interrupt number 18
+76 to +79 (Note) UART1 transmitSoftware interrupt number 19
+80 to +83 (Note) UART1 receiveSoftware interrupt number 20
+84 to +87 (Note) Timer A0Software interrupt number 21
+88 to +91 (Note) Timer A1Software interrupt number 22
+92 to +95 (Note) Timer A2Software interrupt number 23
+96 to +99 (Note) Timer A3Software interrupt number 24
+100 to +103 (Note) Timer A4Software interrupt number 25
+104 to +107 (Note) Timer B0Software interrupt number 26
+108 to +111 (Note) Timer B1Software interrupt number 27
+112 to +115 (Note) Timer B2Software interrupt number 28
+116 to +119 (Note) INT0
Software interrupt number 29
+120 to +123 (Note) INT1
Software interrupt number 30
+124 to +127 (Note) INT2
Software interrupt number 31
+128 to +131 (Note) Software interrupt
Software interrupt number 32
+252 to +255 (Note)Software interrupt number 63 toto
Note: Address relative to address in interrupt table register (INTB)
Cannot be masked I flag
+40 to +43 (Note) Bus collision detectionSoftware interrupt number 10
+60 to +63 (Note) UART2 transmitSoftware interrupt number 15
+64 to +67 (Note) UART2 receiveSoftware interrupt number 16
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 1.13.2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
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Interrupt
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 1.13.3 shows the memory map of the interrupt control registers.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Figure 1.13.3. Interrupt control registers
Symbol Address When reset
INTiIC(i=0 to 2) 005D
16
to 005F
16
XX00X000
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
ILVL0
IR
POL
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
ILVL1
ILVL2
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
(Note 1)
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
AA
AA
AA
AA
Bit name FunctionBit symbol
WR
Symbol Address When reset
BCNIC 004A
16
XXXXX000
2
DMiIC(i=0, 1) 004B
16
, 004C
16
XXXXX000
2
KUPIC 004D
16
XXXXX000
2
ADIC 004E
16
XXXXX000
2
SiTIC(i=0 to 2) 0051
16
, 0053
16
, 004F
16
XXXXX000
2
SiRIC(i=0 to 2) 0052
16
, 0054
16
, 0050
16
XXXXX000
2
TAiIC(i=0 to 4) 0055
16
to 0059
16
XXXXX000
2
TBiIC(i=0 to 2) 005A
16
to 005C
16
XXXXX000
2
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit 0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
(Note 1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
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Interrupt
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Table 1.13.4.
Interrupt levels enabled according
to the contents of the IPL
Table 1.13.3. Settings of interrupt priority levels
Interrupt priority
level select bit Interrupt priority
level Priority
order
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
b2 b1 b0
Enabled interrupt priority levels
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL
2
IPL
1
IPL
0
IPL
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.13.3 shows the settings of interrupt priority levels and Table 1.13.4 shows the interrupt levels
enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ; Four NOP instructions are required when using HOLD function.
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ; Push Flag register onto stack
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
49
Interrupt
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M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.13.4 shows the interrupt response time.
Instruction Interrupt sequence Instruction in
interrupt routine
Time
Interrupt response time
(a) (b)
Interrupt request acknowledgedInterrupt request generated
Figure 1.13.4. Interrupt response time
50
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt sources without priority levels
7
Value set in the IPL
_______
Watchdog timer, NMI
Other Not changed
0
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.13.6 is set in the IPL.
Table 1.13.6. Relationship between interrupts without interrupt priority levels and IPL
Stack pointer (SP) valueInterrupt vector address 16-Bit bus, without wait 8-Bit bus, without wait
Even
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Table 1.13.5. Time required for executing the interrupt sequence
Reset
Indeterminate
123456789 101112 13 14 15 16 17 18
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate SP-2
contents SP-4
contents vec
contents vec+2
contents
Interrupt
information
Address
0000 Indeterminate SP-2 SP-4 vec vec+2 PC
BCLK
Address bus
Data bus
W
R
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.13.5.
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure 1.13.5. Time required for executing the interrupt sequence
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 1.13.6 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
Content of previous stack
Stack area
[SP]
Stack pointer
value before
interrupt occurs
m
m – 1
m – 2
m – 3
m – 4
Stack status before interrupt request
is acknowledged Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB LSB
m
m – 1
m – 2
m – 3
m – 4
Address
Flag register (FLG
L
)
Content of previous stack
Stack area
Flag register
(FLG
H
)Program
counter (PC
H
)
[SP]
New stack
pointer value
Content of previous stack
m + 1
MSB LSB
Program counter (PC
L
)
Program counter (PC
M
)
Figure 1.13.6. State of stack before and after acceptance of interrupt request
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Figure 1.13.7. Operation of saving registers
(2) Stack pointer (SP) contains odd number
[SP] (Odd)
[SP] – 1 (Even)
[SP] – 2(Odd)
[SP] – 3 (Even)
[SP] – 4(Odd)
[SP] – 5 (Even)
Address Sequence in which order
registers are saved
(2)
(1)
Finished saving registers
in four operations.
(3)
(4)
(1) Stack pointer (SP) contains even number
[SP] (Even)
[SP] – 1(Odd)
[SP] – 2 (Even)
[SP] – 3(Odd)
[SP] – 4 (Even)
[SP] – 5 (Odd)
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Saved simultaneously,
all 8 bits
Flag register
(FLG
H
)Program
counter (PC
H
)
Flag register
(FLG
H
)Program
counter (PC
H
)
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.13.7 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
53
Interrupt
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.13.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-
tion before executing the REIT instruction.
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 1.13.9 shows the circuit that judges the interrupt priority level.
Figure 1.13.8. Hardware interrupts priorities
_______ ________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Figure 1.13.9. Maskable interrupts priorities (peripheral I/O interrupts)
Timer B2
Timer B0
Timer A3
Timer A1
Timer B1
Timer A4
Timer A2
UART1 reception
UART0 reception
UART2 reception
A-D conversion
DMA1
Bus collision detection
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission
Key input interrupt
DMA0
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Watchdog timer
Reset
INT1
INT2
INT0
DBC
NMI
Interrupt
request
accepted
Level 0 (initial value)
Priority level of each interrupt
High
Low
Priority of peripheral I/O interrupts
(if priority levels are same)
Address match
55
Interrupt
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt control circuit
Key input interrupt control register (address 004D
16
)
Key input interrupt
request
P10
7
/KI
3
P10
6
/KI
2
P10
5
/KI
1
P10
4
/KI
0
Port P10
4
-P10
7
pull-up
select bit
Port P10
7
direction
register
Pull-up
transistor
Port P10
7
direction register
Port P10
6
direction
register
Port P10
5
direction
register
Port P10
4
direction
register
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Figure 1.13.10. Block diagram of key input interrupt
______
NMI Interrupt
______ ______ ______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.13.10 shows the block diagram of the key input interrupt. Note that if an
“L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as
an interrupt.
________
NMI Interrupt
______
INT Interrupt
________ ________
INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity
select bit.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Figure 1.13.11 shows the address match interrupt-related registers.
Bit nameBit symbol
Symbol Address When reset
AIER 000916 XXXXXX002
Address match interrupt enable register
Function WR
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
Address match interrupt 0
enable bit 0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Symbol Address When reset
RMAD0 001216 to 001016 X0000016
RMAD1 001616 to 001416 X0000016
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
b7 b6 b5 b4 b3 b2 b1 b0
WR
Address setting register for address match interrupt
Function Values that can be set
Address match interrupt register i (i = 0, 1)
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7 b0b3
(b19) (b16) b7 b0
(b15) (b8)
b7
(b23)
AA
A
AA
A
AA
AA
A
A
Figure 1.13.11. Address match interrupt-related registers
Address Match Interrupt
57
Interrupt
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
_______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point
at the beginning of a program. Concerning the first instruction immediately after reset, generating any
_______
interrupts including the NMI interrupt is prohibited.
_______
(3) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor
(pull-up) if unused. Be sure to work on it.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input. _______
• Do not reset the CPU with the input to the NMI pin being in the “L” state.
_______
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned
down. _______
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved.
In this instance, the CPU is returned to the normal state by a later interrupt.
_______
• Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt ________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
through INT2 regardless of the CPU operation clock.
________ ________
• When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.13.12 shows the procedure for
______
changing the INT interrupt generate factor.
Precautions for Interrupts
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
______
Figure 1.13.12. Switching condition of INT interrupt request
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt enable flag to “1”
(Enable interrupt)
Precautions for Interrupts
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ; Four NOP instructions are required when using HOLD function.
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ; Push Flag register onto stack
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
BCLK
Write to the watchdog timer
start register
(address 000E
16
)
RESET
Watchdog timer
interrupt request
Watchdog timer
Set to
“7FFF
16
”
1/128
1/16
“CM07 = 0”
“WDC7 = 1”
“CM07 = 0”
“WDC7 = 0”
“CM07 = 1”
HOLD
1/2
Prescaler
Figure 1.14.1. Block diagram of watchdog timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calcu-
lated as given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler.
For example, suppose that BCLK runs at 10 MHZ and that 16 has been chosen for the dividing ratio of the
pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 1.14.1 shows the block diagram of the watchdog timer. Figure 1.14.2 shows the watchdog timer-
related registers.
With XIN chosen for BCLK
Watchdog timer period = pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
With XCIN chosen for BCLK
Watchdog timer period = pre-scaler dividing ratio (2) X watchdog timer count (32768)
BCLK
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog timer control register
Symbol Address When reset
WDC 000F
16
000XXXXX
2
FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
High-order bit of watchdog timer
WDC7
Bit name
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
Symbol Address When reset
WDTS 000E
16
Indeterminate
WR
b7 b0
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF
16
”
regardless of whatever value is written.
Reserved bit
Reserved bit Must always be set to “0”
Must always be set to “0”
00
AA
AA
A
AA
A
AA
A
A
Figure 1.14.2. Watchdog timer control and start registers
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
A
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Data bus low-order bits
DMA latch high-order bits DMA latch low-order bits
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20) (Note)
Data bus high-order bits
A
A
A
A
A
A
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAA
AAAAAAAA
Address bus
A
A
A
A
A
A
A
A
DMA1 destination pointer DAR1 (20)
DMA1 source pointer SAR1 (20)
DMA1 forward address pointer (20) (Note)
A
A
A
A
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
A
A
A
A
(addresses 0029
16
, 0028
16
)
(addresses 0039
16
, 0038
16
)
(addresses 0022
16
to 0020
16
)
(addresses 002616 to 002416)
(addresses 0032
16
to 0030
16
)
(addresses 003616 to 003416)
Note: Pointer is incremented by a DMA request.
AA
AA
AA
AA
AA
AA
A
A
A
A
A
A
A
A
A
A
A
AA
AA
A
A
A
A
A
A
Figure 1.15.1. Block diagram of DMAC
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-
bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.15.1 shows the block diagram
of the DMAC. Table 1.15.1 shows the DMAC specifications. Figure 1.15.2 to Figure 1.15.3 show the regis-
ters used by the DMAC.
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
Item Specification
No. of channels 2 (cycle steal method)
Transfer memory space • From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum No. of bytes transferred
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors (Note)
________ ________ ________ ________
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests (UART1 trans-
mission can be selected by DMA0, UART1 reception by DMA1)
UART2 transmission and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit 8 bits or 16 bits
Transfer address direction forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode •Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to
“0”, and the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
DMA interrupt request generation timing
When an underflow occurs in the transfer counter
Active When the DMA enable bit is set to “1”, the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
Inactive • When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active,
re
the value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer,and the value
of the transfer counter reload register is reloaded to the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Reading the register Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Table 1.15.1. DMAC specifications
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
Forward address pointer and
load timing for transfer
counter
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAi request cause select register
Symbol Address When reset
DMiSL(i=0,1) 03B8
16
,03BA
16
00
16
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DMA request cause
select bit
DSEL0
RW
DSEL1
DSEL2
DSEL3
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Software DMA request bit If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
DSR
DMAi control register
Symbol Address When reset
DMiCON(i=0,1) 002C
16
, 003C
16
00000X00
2
Bit name FunctionBit symbol
Transfer unit bit select bit
b7 b6 b5 b4 b3 b2 b1 b0
0 : 16 bits
1 : 8 bits
DMBIT
RW
DMASL
DMAS
DMAE
Repeat transfer mode
select bit 0 : Single transfer
1 : Repeat transfer
DMA request bit (Note 1) 0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 3)
Destination address
direction select bit (Note 3) 0 : Fixed
1 : Forward
DSD
DAD
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 / INT1
pin (Note 1)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit / UART1
receive (Note 2)
Note 1: Address 03B8
16
is for INT0 ; address 03BA
16
is for INT1.
Note 2: Address 03B8
16
is for UART1 transmit ; address 03BA
16
is for UART1 receive.
(Note 2)
AA
AA
A
A
AA
A
AA
AA
A
A
AA
AA
A
A
AA
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Bit name
Figure 1.15.2. DMAC register (1)
64
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
b7 b0 b7 b0
(b8)(b15)
Function
RW
• Transfer counter
Set a value one less than the transfer count
Symbol Address When reset
TCR0 0029
16
, 0028
16
Indeterminate
TCR1 0039
16
, 0038
16
Indeterminate
DMAi transfer counter (i = 0, 1)
Transfer count
specification
0000
16
to FFFF
16
b7
(b23) b3 b0 b7 b0 b7 b0
(b8)(b16)(b15)(b19)
Function
RW
• Source pointer
Stores the source address
Symbol Address When reset
SAR0 0022
16
to 0020
16
Indeterminate
SAR1 0032
16
to 0030
16
Indeterminate
DMAi source pointer (i = 0, 1)
Transfer count
specification
00000
16
to FFFFF
16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Symbol Address When reset
DAR0 0026
16
to 0024
16
Indeterminate
DAR1 0036
16
to 0034
16
Indeterminate
b3 b0 b7 b0 b7 b0
(b8)(b15)(b16)(b19)
Function
RW
• Destination pointer
Stores the destination address
DMAi destination pointer (i = 0, 1)
Transfer count
specification
00000
16
to FFFFF
16
b7
(b23)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
A
A
A
A
A
A
A
A
Figure 1.15.3. DMAC register (2)
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.15.4 shows the example of the transfer cycles for a source read. For convenience, the destina-
tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.
In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-
tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 36,
if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source
read cycle and the destination write cycle.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.15.4. Example of the transfer cycles for a source read
67
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
Single-chip mode Memory expansion mode
Transfer unit Bus width Access address Microprocessor mode
No. of read No. of write No. of read No. of write
cycles cycles cycles cycles
16-bit Even 1111
8-bit transfers (BYTE= “L”) Odd 1111
(DMBIT= “1”) 8-bit Even — — 1 1
(BYTE = “H”) Odd — — 1 1
16-bit Even 1111
16-bit transfers (BYTE = “L”) Odd 2222
(DMBIT= “0”) 8-bit Even — — 2 2
(BYTE = “H”) Odd — — 2 2
Table 1.15.2. No. of DMAC transfer cycles
Internal memory External memory
Internal ROM/RAM Internal ROM/RAM
SFR area Separate bus Separate bus Multiplex
No wait With wait No wait With wait bus
122123
Coefficient j, k
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.15.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
68
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA enable bit
Setting the DMA enable bit to 1 makes the DMAC active. The DMAC carries out the following operations at
the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting 1 to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant 1 is overwritten to the DMA enable
bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA
request factors for each channel.
DMA request factors include the following.
* Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
* External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.
The DMA request bit turns to 1 if the DMA transfer request signal occurs regardless of the DMAC's state
(regardless of whether the DMA enable bit is set 1 or to 0). It turns to 0 immediately before data transfer
starts.
In addition, it can be set to 0 by use of a program, but cannot be set to 1.
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit
to turn to 1. So be sure to set the DMA request bit to 0 after the DMA request factor selection bit is changed.
The DMA request bit turns to 1 if a DMA transfer request signal occurs, and turns to 0 immediately before
data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request
bit, if read by use of a program, turns out to be 0 in most cases. To examine whether the DMAC is active,
read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to 1 due
to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to
turn to 1 due to several factors.
Turning the DMA request bit to 1 due to an internal factor is timed to be effected immediately before the
transfer starts.
(2) External factors
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on
which DMAC channel is used).
Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from
these pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to 1 when an external factor is selected synchronizes with the
signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes
with the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to 0 immediately before data transfer
starts similarly to the state in which an internal factor is selected.
69
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from
the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently
turn to 1. If the channels are active at that moment, DMA0 is given a high priority to start data transfer.
When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus
access, then DMA1 starts data transfer and gives the bus right to the CPU.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
Figure 1.15.5 An example of DMA transfer effected by external factors.
Figure 1.15.5. An example of DMA transfer effected by external factors
BCLK
AAAA
AAAA
DMA0
AAAA
DMA1
DMA0
request bit
DMA1
request bit
AAA
AAA
AAAAA
AAAAA
A
A
AAAAAA
AAAAAA
AA
AA
CPU
INT0
INT1
Obtainm
ent of the
bus right
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
70
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer
There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(three). All these timers function independently. Figure 1.16.1 shows the block diagram of timers.
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
TA0
IN
TA1
IN
TA2
IN
TA3
IN
TA4
IN
TB0
IN
TB1
IN
TB2
IN
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
f
1
f
8
f
32
f
C32
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer B0 interrupt
Timer B1 interrupt
Timer B2 interrupt
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
1/32 f
C32
1/8
1/4
f
1
f
8
f
32
X
IN
X
CIN
Clock prescaler reset flag (bit 7
at address 0381
16
) set to “1”
Reset
Clock prescaler
Figure 1.16.1. Block diagram of timer
71
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A
Figure 1.16.2 shows the block diagram of timer A. Figures 1.16.3 to 1.16.5 show the timer A-related
registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Figure 1.16.3. Timer A-related registers (1)
Count start flag
(Address 0380
16
)
Up count/down count
TAi Addresses TAj TAk
Timer A0 0387
16
0386
16
Timer A4 Timer A1
Timer A1 0389
16
0388
16
Timer A0 Timer A2
Timer A2 038B
16
038A
16
Timer A1 Timer A3
Timer A3 038D
16
038C
16
Timer A2 Timer A4
Timer A4 038F
16
038E
16
Timer A3 Timer A0
Always down count except
in event counter mode
Reload register (16)
Counter (16)
Low-order
8 bits
AAAA
AAAA
High-order
8 bits
Clock source
selection
• Timer
(gate function)
• Timer
• One shot
• PWM
f
1
f
8
f
32
External
trigger
TAi
IN
(i = 0 to 4)
TB2 overflow
• Event counter
f
C32
Clock selection
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
Pulse output
Toggle flip-flop
TAi
OUT
(i = 0 to 4)
Data bus low-order bits
Data bus high-order bits
A
A
A
Up/down flag
Down count
(Address 0384
16
)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Polarity
selection
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 4) 0396
16
to 039A
16
00
16
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode select bit
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
A
AA
AA
Figure 1.16.2. Block diagram of timer A
72
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Figure 1.16.4. Timer A-related registers (2)
Timer A4 up/down flag
Timer A3 up/down flag
Timer A2 up/down flag
Timer A1 up/down flag
Timer A0 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
Symbol Address When reset
UDF 0384
16
00
16
TA4P
TA3P
TA2P
Up/down flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
TA4UD
TA3UD
TA2UD
TA1UD
TA0UD 0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Symbol Address When reset
TABSR 0380
16
00
16
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
Symbol Address When reset
TA0 0387
16
,0386
16
Indeterminate
TA1 0389
16
,0388
16
Indeterminate
TA2 038B
16
,038A
16
Indeterminate
TA3 038D
16
,038C
16
Indeterminate
TA4 038F
16
,038E
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Ai register (Note)
WR
• Timer mode 0000
16
to FFFF
16
Counts an internal count source
Function
Values that can be set
• Event counter mode 0000
16
to FFFF
16
Counts pulses from an external source or timer overflow
• One-shot timer mode 0000
16
to FFFF
16
Counts a one shot width
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
00
16
to FE
16
(Both high-order
and low-order
addresses)
0000
16
to FFFE
16
Note: Read and write data in 16-bit units.
AA
AA
A
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
AA
A
A
A
A
A
A
AA
AA
A
A
AA
A
A
A
A
A
73
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Symbol Address When reset
CPSRF 0381
16
0XXXXXXX
2
Clock prescaler reset flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
WR
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
TA1TGL
Symbol Address When reset
TRGSR 0383
16
00
16
Timer A1 event/trigger
select bit 0 0 :
Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 :
Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 :
Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 :
Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
WR
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
b1 b0
b3 b2
b5 b4
b7 b6
Note: Set the corresponding port direction register to “0”.
TA1OS
TA2OS
TA0OS
One-shot start flag
Symbol Address When reset
ONSF 0382
16
00X00000
2
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA3OS
TA4OS
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
i
ndeterminate.
TA0TGL
TA0TGH
0 0 :
Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Timer A0 event/trigger
select bit
b7 b6
Note: Set the corresponding port direction register to “0”.
WR
1 : Timer start
When read, the value is “0”
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.16.5. Timer A-related registers (3)
74
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Item Specification
Count source f1, f8, f32, fC32
Count operation • Down count
•
When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
When the timer underflows
TAiIN pin function Programmable I/O port or gate input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.16.1.) Figure 1.16.6
shows the timer Ai mode register in timer mode.
Table 1.16.1. Specifications of timer mode
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 4) 0396
16
to 039A
16
00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA
iOUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA
iOUT
pin is a pulse output pin)
Gate function select bit 0 X
(Note 2)
: Gate function not available
(TAi
IN
pin is a normal port pin)
1 0 : Timer counts only when TA
iIN
pin is
held “L” (Note 3)
1 1 : Timer counts only when TA
iIN
pin is
held “H” (Note 3)
b4 b3
MR2
MR1
MR3 0 (Must always be fixed to “0” in timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
00
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.16.6. Timer Ai mode register in timer mode
75
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Item Specification
Count source
•
External signals input to TAi
IN
pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
Count operation • Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
Divide ratio 1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer overflows or underflows
TAiIN pin function Programmable I/O port or count source input
TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 1.16.2 lists timer specifications when counting a single-phase external signal.
Figure 1.16.7 shows the timer Ai mode register in event counter mode.
Table 1.16.3 lists timer specifications when counting a two-phase external signal. Figure 1.16.8 shows
the timer Ai mode register in event counter mode.
Table 1.16.2.
Timer specifications in event counter mode (when not processing two-phase pulse signal)
Figure 1.16.7. Timer Ai mode register in event counter mode
Timer Ai mode register
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 0382
16
and 0383
16
).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAi
OUT
pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Symbol Address When reset
TAiMR(i = 0, 1) 0396
16
, 0397
16
00
16
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
(Note 1)
b1 b0
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA
iOUT
pin is a normal port pin)
1 : Pulse is output (Note 2)
(TA
iOUT
pin is a pulse output pin)
Count polarity
select bit (Note 3)
MR2
MR1
MR3 0 (Must always be fixed to “0” in event counter mode)
TCK0 Count operation type
select bit
010
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit 0 : Up/down flag's content
1 : TA
iOUT
pin's input signal (Note 4)
0 : Reload type
1 : Free-run type
Bit symbol Bit name Function RW
TCK1 Invalid in event counter mode
Can be “0” or “1”
TMOD1
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
76
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Item Specification
Count source • Two-phase pulse signals input to TAiIN or TAiOUT pin
Count operation • Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio 1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
Timer overflows or underflows
TAiIN pin function Two-phase pulse input
TAiOUT pin function Two-phase pulse input
Read from timer Count value can be read out by reading timer A2, A3, or A4 register
Write to timer • When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
Select function • Normal processing operation
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
• Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
Note: This does not apply when the free-run function is selected.
Table 1.16.3. Timer specifications in event counter mode (when processing two-phase pulse
signal with timers A2, A3, and A4)
TAi
OUT
Up
count Up
count Up
count Down
count Down
count Down
count
TAi
IN
(i=2,3)
TAi
OUT
TAi
IN
(i=3,4)
Count up all edges
Count up all edges
Count down all edges
Count down all edges
77
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for the timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 0384
16
) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 0382
16
and 0383
16
) to “00”.
Timer Ai mode register
(When not using two-phase pulse signal processing)
Symbol Address When reset
TAiMR(i = 2 to 4) 0398
16
to 039A
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TAi
OUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAi
OUT
pin is a pulse output pin)
Count polarity
select bit (Note 2)
MR2
MR1
MR3 0 : (Must always be “0” in event counter mode)
TCK1
TCK0
010
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
Up/down switching
cause select bit 0 : Up/down flag's content
1 : TA
iOUT
pin's input signal (Note 3)
Bit symbol Bit name Function
WR
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit (Note 4)(Note 5)
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0” or “1”.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 0384
16
) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 0382
16
and 0383
16
) to “00”.
Timer Ai mode register
(When using two-phase pulse signal processing)
Symbol Address When reset
TAiMR(i = 2 to 4) 0398
16
to 039A
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 0 (Must always be “0” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR2
MR1
MR3 0 (Must always be “0” when using two-phase pulse signal
processing)
TCK1
TCK0
010
1 (Must always be “1” when using two-phase pulse signal
processing)
Bit symbol Bit name Function
WR
Count operation type
select bit
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
001
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.16.8. Timer Ai mode register in event counter mode
78
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Item Specification
Count source f1, f8, f32, fC32
Count operation • The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : Set value
Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing
The count reaches 000016
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Table 1.16.4. Timer specifications in one-shot timer mode
Figure 1.16.9. Timer Ai mode register in one-shot timer mode
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.16.4.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.16.9 shows the timer Ai mode register in one-shot
timer mode.
Bit name
Timer Ai mode register
Symbol Address When reset
TAiMR(i = 0 to 4) 0396
16
to 039A
16
00
16
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 1 0 : One-shot timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA
iOUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAi
OUT
pin is a pulse output pin)
MR2
MR1
MR3 0 (Must always be “0” in one-shot timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
100
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
Trigger select bit
External trigger select
bit (Note 2)
0 : Falling edge of TAi
IN
pin's input signal (Note 3)
1 : Rising edge of TAi
IN
pin's input signal (Note 3)
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TA
iIN
pin is selected by the event/trigger select bit
(addresses 0382
16
and 0383
16
). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the correspondin
g
port direction re
g
ister to “0”.
WR
AA
A
AA
AA
A
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
79
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Item Specification
Count source f1, f8, f32, fC32
Count operation • T
he timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
•
The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
16-bit PWM • High level width n / fi n : Set value
• Cycle time (216
-
1) / fi fixed
8-bit PWM
•
High level widthn X (m+1) / fi n : values set to timer Ai register’s high-order address
•
Cycle time (2
8
- 1) X (m +1) / fim : values set to timer Ai register’s low-order address
Count start condition • External trigger is input
• The timer overflows
• The count start flag is set (= 1)
Count stop condition • The count start flag is reset (= 0)
Interrupt request generation timing
PWM pulse goes “L”
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Pulse output
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.16.5.) In this mode, the counter functions
as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.16.10 shows the configuration of the
timer Ai mode register in pulse width modulation mode. Figure 1.16.11 shows an example of how a 16-bit pulse width
modulator operates. Figure 1.16.12 shows an example of how an 8-bit pulse width modulator operates.
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 4) 0396
16
to 039A
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 1 : PWM mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0
Count source select bit
WR
111
1 (Must always be fixed to “1” in PWM mode)
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
Trigger select bit
External trigger select
bit (Note 1)
0: Falling edge of TAi
IN
pin's input signal (Note 2)
1: Rising edge of TAi
IN
pin's input signal (Note 2)
0: Count start flag is valid
1: Selected by event/trigger select register
Note 1: Valid only when the TA
iIN
pin is selected by the event/trigger select bit
(addresses 0382
16
and 0383
16
). If timer overflow is selected, this bit can be “1” or “0
Note 2: Set the corresponding port direction register to “0”.
AA
A
AA
AA
A
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
Table 1.16.5. Timer specifications in pulse width modulation mode
Figure 1.16.10. Configuration of timer Ai mode register in pulse width modulation mode
80
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
1 / f
i
X
(2 – 1)
16
Count source
TA
iIN
pin
input signal
PWM pulse output
from TA
iOUT
pin
Condition : Reload register = 0003
16
, when external trigger
(rising edge of TA
iIN
pin input signal) is selected
Trigger is not generated by this signal
“H”
“H”
“L”
“L”
Timer Ai interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
f
i
: Frequency of count source
(f
1
, f
8
, f
32
, f
C32
)
Note: n = 0000
16
to FFFE
16
.
1 / f
i
X
n
Count source (Note1)
TA
iIN
pin input signal
Underflow signal of
8-bit prescaler (Note2)
PWM pulse output
from TA
iOUT
pin
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
Timer Ai interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleaerd by software
f
i
: Frequency of count source
(f
1
, f
8
, f
32
, f
C32
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 00
16
to FE
16
; n = 00
16
to FE
16
.
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Condition : Reload register high-order 8 bits = 02
16
Reload register low-order 8 bits = 02
16
External trigger (falling edge of TA
iIN
pin input signal) is selected
1 / f
i
X (m
+ 1) X (2 – 1)
8
1 / f
i
X (m + 1) X n
1 / f
i
X (m + 1)
Figure 1.16.11. Example of how a 16-bit pulse width modulator operates
Figure 1.16.12. Example of how an 8-bit pulse width modulator operates
81
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer B
Figure 1.16.13 shows the block diagram of timer B. Figures 1.16.14 and 1.16.15 show the timer B-related
registers.
Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Figure 1.16.13. Block diagram of timer B
Timer Bi mode register
Symbol Address When reset
TBiMR(i = 0 to 2) 039B
16
to 039D
16
00XX0000
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode select bit
(Note 1)
(Note 2)
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
AA
AA
A
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
AA
A
A
AA
A
AA
Clock source selection
(address 0380
16
)
• Event counter
• Timer
• Pulse period/pulse width measurement Reload register (16)
Low-order 8 bits High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f
1
f
8
f
32
TBj overflow
(j = i – 1. Note, however,
j = 2 when i = 0)
Can be selected in only
event counter mode
Count start flag
f
C32
Polarity switching
and edge pulse
TBi
IN
(i = 0 to 2)
Counter reset circuit
Counter (16)
TBi Address TBj
Timer B0 0391
16
0390
16
Timer B2
Timer B1 0393
16
0392
16
Timer B0
Timer B2 0395
16
0394
16
Timer B1
Figure 1.16.14. Timer B-related registers (1)
82
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Symbol Address When reset
TABSR 0380
16
00
16
Count start flag
Bit name
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
Symbol Address When reset
CPSRF 0381
16
0XXXXXXX
2
Clock prescaler reset flag
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
A
AAAAAAAAAAAAA
A
AAAAAAAAAAAAAAA
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Symbol Address When reset
TB0 0391
16
, 0390
16
Indeterminate
TB1 0393
16
, 0392
16
Indeterminate
TB2 0395
16
, 0394
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Bi register (Note)
WR
• Pulse period / pulse width measurement mode
Measures a pulse period or width
• Timer mode 0000
16
to FFFF
16
Counts the timer's period
Function
Values that can be set
• Event counter mode 0000
16
to FFFF
16
Counts external pulses input or a timer overflow
Note: Read and write data in 16-bit units.
Function
A
A
AA
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
Figure 1.16.15. Timer B-related registers (2)
83
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Item Specification
Count source f1, f8, f32, fC32
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TBiIN pin function Programmable I/O port
Read from timer Count value is read out by reading timer Bi register
Write to timer • When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.16.6.) Figure 1.16.16
shows the timer Bi mode register in timer mode.
Table 1.16.6. Timer specifications in timer mode
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Timer Bi mode register Symbol Address When reset
TBiMR(i=0 to 2) 039B
16
to 039D
16
00XX0000
2
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AA
A
Operation mode select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Invalid in timer mode
Can be “0” or “1”
MR2
MR1
MR3
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
TCK1
TCK0 Count source select bit
0
Invalid in timer mode.
In an attempt to write to this bit, write “0” . The value, if read in
timer mode, turns out to be indeterminate.
0
0 (Fixed to “0” in timer mode ; i = 0)
Nothing is assiigned (i = 1,2).
In an attempt to write to this bit, write “0” . The value, if read, turns out
to be indeterminate.
(Note 1)
(Note 2)
b7 b6
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.16.16. Timer Bi mode register in timer mode
84
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Item Specification
Count source • External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TBiIN pin function Count source input
Read from timer Count value can be read out by reading timer Bi register
Write to timer • When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.16.7.)
Figure 1.16.17 shows the timer Bi mode register in event counter mode.
Table 1.16.7. Timer specifications in event counter mode
Figure 1.16.17. Timer Bi mode register in event counter mode
Timer Bi mode register
Symbol Address When reset
TBiMR(i=0 to 2) 039B16 to 039D16 00XX00002
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AA
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 Count polarity select
bit (Note 1)
MR2
MR1
MR3 Invalid in event counter mode.
In an attempt to write to this bit, write “0” . The value, if read
in event counter mode, turns out to be indeterminate.
TCK1
TCK0
01
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
b3 b2
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0” . The value, if read,
turns out to be indeterminate.
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
Note 4: Set the corresponding port direction register to “0”.
Invalid in event counter mode.
Can be “0” or “1”.
Event clock select 0 : Input from TBiIN pin (Note 4)
1 : TBj overflow
(j = i – 1; however, j = 2 when i = 0)
0 (Fixed to “0” in event counter mode; i = 0) (Note 2)
(Note 3)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
85
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Item Specification
Count source f1, f8, f32, fC32
Count operation • Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
• When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function Measurement pulse input
Read from timer When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer Cannot be written to
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.16.8.)
Figure 1.16.18 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.16.19 shows the operation timing when measuring a pulse period. Figure 1.16.20 shows the operation
timing when measuring a pulse width.
Table 1.16.8. Timer specifications in pulse period/pulse width measurement mode
Figure 1.16.18. Timer Bi mode register in pulse period/pulse width measurement mode
Note 1:
An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2:
The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
Symbol Address When reset
TBiMR(i=0 to 2) 039B
16
to 039D
16
00XX0000
2
Bit nameBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 0 : Pulse period / pulse width
measurement mode
b1 b0
TMOD1
TMOD0
MR0 Measurement mode
select bit
MR2
MR1
MR3
TCK1
TCK0
01
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
Function
b3 b2
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0” . The value, if read, turns out to be
indeterminate.
Count source
select bit
Timer Bi overflow
flag ( Note 1) 0 : Timer did not overflow
1 : Timer has overflowed
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Note 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0)
(Note 2)
(Note 3)
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
A
86
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Figure 1.16.20. Operation timing when measuring a pulse width
Measurement pulse
“H”
Count source
Count start flag
Timer Bi interrupt
request bit
Timing at which counter
reaches “0000
16
”
“1”
“1”
Transfer
(measured value) Transfer
(measured value)
“L”
“0”
“0”
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)(Note 1)
Transfer
(measured
value)
(Note 1)
Cleared to “0” when interrupt request is accepted, or cleared by software.
(Note 2)
Transfer
(indeterminate
value)
Reload register counter
transfer timing
Figure 1.16.19. Operation timing when measuring a pulse period
Count source
Measurement pulse
Count start flag
Timer Bi interrupt
request bit
Timing at which counter
reaches “0000
16
”
“H”
“1”
Transfer
(indeterminate value)
“L”
“0”
“0”
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)
When measuring measurement pulse time interval from falling edge to falling edge
(Note 2)
Cleared to “0” when interrupt request is accepted, or cleared by software.
Transfer
(measured value)
“1”
Reload register counter
transfer timing
87
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured as three channels: UART0, UART1 and UART2. UART0, UART1 and UART2 each
have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 1.17.1 shows the block diagram of UART0, UART1 and UART2. Figure 1.17.2 and figure 1.17.3
show the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART.
UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is
compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode
(Note). It also has the bus collision detection function that generates an interrupt request if the TXD pin and
the RXD pin are different in level.
Note: SIM : Subscriber Identity Module
Table 1.17.1 shows the comparison of functions of UART0 through UART2, and Figures 1.17.4 through
1.17.8 show the registers related to UARTi.
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
UART0 UART1 UART2Function
CLK polarity selection
Continuous receive mode selection
LSB first / MSB first selection
Impossible
Transfer clock output from multiple
pins selection Impossible
Impossible Impossible
ImpossibleSerial data logic switch Impossible
Sleep mode selection Impossible
ImpossibleTxD, RxD I/O polarity switch Impossible Possible
CMOS outputTxD, RxD port output format CMOS output N-channel open-drain
output
ImpossibleParity error signal output Impossible
ImpossibleBus collision detection Impossible Possible
Possible (Note 1)
Separate CTS/RTS pins
Possible (Note 1)
Possible (Note 1)
Possible (Note 3)
Possible (Note 1)
Possible (Note 1)
Possible (Note 1)
Possible (Note 1)
Possible (Note 3)
Possible
Possible (Note 1)
Possible (Note 2)
Possible (Note 1)
Possible (Note 4)
Possible (Note 4)
Table 1.17.1. Comparison of functions of UART0 through UART2
88
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Figure 1.17.1. Block diagram of UARTi (i = 0 to 2)
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
RxD
2
Reception
control circuit
Transmission
control circuit
1 / (n
2
+1)
1/16
1/16
1/2
Bit rate generator
(address 0379
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK
2
CTS
2
/ RTS
2
f
1
f
8
f
32
Vcc
RTS
2
CTS
2
TxD
2
(UART2)
RxD polarity
reversing circuit
TxD
polarity
reversing
circuit
RxD
0
1 / (n
0
+1)
1/2
Bit rate generator
(address 03A1
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK
0
Clock source selection
CTS
0
/ RTS
0
f
1
f
8
f
32
Reception
control circuit
Transmission
control circuit
Internal
External
Vcc
RTS
0
CTS
0
TxD
0
Transmit/
receive
unit
RxD
1
1 / (n
1
+1)
1/16
1/16
1/2
Bit rate generator
(address 03A9
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK
1
Clock source selection
f
1
f
8
f
32
Reception
control circuit
Transmission
control circuit
Internal
External
RTS
1
CTS
1
TxD
1
(UART1)
(UART0)
CLK
polarity
reversing
circuit
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS separated
Clock output pin
select switch
CTS
1
/ RTS
1
CTS
0
/ CLKS
1
CTS/RTS disabled
CTS0 from UART1
CTS/RTS selected
CTS/RTS disabled
V
CC
CTS0 to UART0
CTS
0
CTS/RTS disabled
CTS/RTS separated
CTS/RTS disabled
CTS/RTS disabled
CTS/RTS
selected
CLK
polarity
reversing
circuit
Internal
External
Clock source selection
Transmit/
receive
unit
Transmit/
receive
unit
1/16
1/16
89
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Figure 1.17.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
SP SP
PAR
2SP
1SP
UART
UART (7 bits)
UART (8 bits)
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock synchronous
type
TxDi
UARTi transmit register
PAR
enabled
PAR
disabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SP: Stop bit
PAR: Parity bit
UARTi transmit
buffer register
MSB/LSB conversion circuit
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UARTi receive
buffer register
UARTi receive register
2SP
1SP
PAR
enabled
PAR
disabled
UART
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock
synchronous type
UART (7 bits)
UART (8 bits)
RxDi
Clock
synchronous type
UART (8 bits)
UART (9 bits)
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
Data bus low-order bits
MSB/LSB conversion circuit
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
0000000
SP SP
PAR
“0”
Data bus high-order bits
90
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
SP SP
PAR
2SP
1SP
UART
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous
type
Clock
synchronous type
Data bus low-order bits
TxD2
UART2 transmit register
PAR
disabled
PAR
enabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0UART2 transmit
buffer register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART2 receive
buffer register
UART2 receive register
2SP
1SP
UART
(7 bits)
UART
(8 bits) UART(7 bits)
UART
(9 bits)
Clock
synchronous type
Clock
synchronous type
RxD2
UART
(8 bits)
UART
(9 bits)
Address 037E
16
Address 037F
16
Address 037A
16
Address 037B
16
Data bus high-order bits
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
0000000
SP SP
PAR
“0”
Reverse
No reverse
Error signal
output circuit
RxD data
reverse circuit
Error signal output
enable
Error signal output
disable
Reverse
No reverse
Logic reverse circuit + MSB/LSB conversion circuit
Logic reverse circuit + MSB/LSB conversion circuit
PAR
enabled
PAR
disabled
UART
Clock
synchronous
type
TxD data
reverse circuit
SP: Stop bit
PAR: Parity bit
Figure 1.17.3. Block diagram of UART2 transmit/receive unit
91
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Figure 1.17.4. Serial I/O-related registers (1)
b7 b0
(b15) (b8) b7 b0
UARTi transmit buffer register
Function
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Symbol Address When reset
U0TB 03A3
16
, 03A2
16
Indeterminate
U1TB 03AB
16
, 03AA
16
Indeterminate
U2TB 037B
16
, 037A
16
Indeterminate
UARTi bit rate generator
b7 b0
Symbol Address When reset
U0BRG 03A1
16
Indeterminate
U1BRG 03A9
16
Indeterminate
U2BRG 0379
16
Indeterminate
Function
Assuming that set value = n, BRGi divides the count source by
n + 1 00
16
to FF
16
Values that can be set
Symbol Address When reset
U0RB 03A7
16
, 03A6
16
Indeterminate
U1RB 03AF
16
, 03AE
16
Indeterminate
U2RB 037F
16
, 037E
16
Indeterminate
b7 b0
(b15) (b8) b7 b0
UARTi receive buffer register
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
Bit name
Bit
symbol
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0
16
,
03A8
16
and 0378
16
) are set to “000
2
” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A6
16
, 03AE
16
and 037E
16
) is read out.
Invalid
Invalid
Invalid
OER
FER
PER
SUM
Overrun error flag (Note)
Framing error flag (Note)
Parity error flag (Note)
Error sum flag (Note)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Receive data
WR
WR
WR
Receive data
AA
A
A
A
A
A
A
A
AA
92
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive mode register
Symbol Address When reset
UiMR(i=0,1) 03A016, 03A816 0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Must be fixed to 001
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
CKDIR
SMD1
SMD0 Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
Parity enable bit
0 : Internal clock
1 : External clock
Stop bit length select bit
Odd/even parity select bit
Sleep select bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
0 : Internal clock
1 : External clock
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
Invalid
Must always be “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
UART2 transmit/receive mode register
Symbol Address When reset
U2MR 037816 0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Must be fixed to 001
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
CKDIR
SMD1
SMD0 Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock
1 : External clock
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Usually set to “0”
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
Invalid
0 : No reverse
1 : Reverse
Usually set to “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Must always be “0”
Figure 1.17.5. Serial I/O-related registers (2)
93
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UART2 transmit/receive control register 0
Symbol Address When reset
U2C0 037C16 0816
b7 b6 b5 b4 b3 b2 b1 b0
Function
(During UART mode) WR
Function
(During clock synchronous
serial I/O mode)
TXEPT
CLK1
CLK0
CRS
CRD
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions
programmable I/O port)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
UFORM Transfer format select bit
(Note 3)
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
Must always be “0”
Bit name
Bit
symbol
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions programmable
I/O port)
UARTi transmit/receive control register 0
Symbol Address When reset
UiC0(i=0,1) 03A416, 03AC16 0816
b7 b6 b5 b4 b3 b2 b1 b0
Function
(During UART mode) WR
Function
(During clock synchronous
serial I/O mode)
TXEPT
CLK1
CLK0
CRS
CRD
NCH
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bit
Data output select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
UFORM Transfer format select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
Must always be “0”
Bit name
Bit
symbol
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
0 : LSB first
1 : MSB first
AA
AA
A
A
AA
AA
A
A
AA
A
AA
AA
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
AA
A
A
AA
A
Figure 1.17.6. Serial I/O-related registers (3)
94
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Figure 1.17.7. Serial I/O-related registers (4)
UARTi transmit/receive control register 1
Symbol Address When reset
UiC1(i=0,1) 03A516,03AD16 0216
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
UART2 transmit/receive control register 1
Symbol Address When reset
U2C1 037D16 0216
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
U2IRS UART2 transmit interrupt
cause select bit 0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit 0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
Data logic select bit 0 : No reverse
1 : Reverse 0 : No reverse
1 : Reverse
U2LCH
U2ERE Error signal output
enable bit Must be fixed to “0” 0 : Output disabled
1 : Output enabled
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
95
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A8
16
) = “0”.
UART transmit/receive control register 2
Symbol Address When reset
UCON 03B0
16
X0000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
CLKMD0
CLKMD1
RCSP
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit 0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
UART1 continuous
receive mode enable bit
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM
U1RRM
0 : CTS/RTS shared pin
1 : CTS/RTS separated
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Separate CTS/RTS bit
Invalid
Invalid
Invalid
CLK/CLKS select
bit 1 (Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.17.8. Serial I/O-related registers (5)
96
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.17.2
and table 1.17.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.17.9 shows the
UARTi transmit/receive mode register.
Table 1.17.2. Specifications of clock synchronous serial I/O mode (1)
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “1”) : Input from CLKi pin
Transmission/reception control
_______ _______ _______ _______
• CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition
• To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “0”
_______ _______
_ When CTS function selected, CTS input level = “L”
•
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
• When transmitting
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection • Overrun error (Note 2)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Interrupt request
generation timing
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
Clock synchronous serial I/O mode
97
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Serial I/O
Item Specification
Select function • CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
_______ _______
• Separate CTS/RTS pins (UART0) (Note)
_______ _______
UART0 CTS and RTS pins each can be assigned to separate pins
• Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TXD, RXD I/O polarity reverse (UART2)
This function is reversing TXD port output and RXD port input. All I/O data
level is reversed.
Table 1.17.3. Specifications of clock synchronous serial I/O mode (2)
_______ _______
Note: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
Clock synchronous serial I/O mode
98
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Serial I/O
Figure 1.17.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
CKDIR
UARTi transmit/receive mode registers
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
0 (Must always be “0” in clock synchronous serial I/O mode)
010
SMD0
SMD1
SMD2
Serial I/O mode select bit 0 0 1 : Clock synchronous serial
I/O mode
b2 b1 b0
0
Invalid in clock synchronous serial I/O mode
Symbol Address When reset
U2MR 0378
16
00
16
CKDIR
UART2 transmit/receive mode register
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
0 : Internal clock
1 : External clock
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
010
SMD0
SMD1
SMD2
Serial I/O mode select bit 0 0 1 : Clock synchronous serial
I/O mode
b2 b1 b0
0
Invalid in clock synchronous serial I/O mode
TxD, RxD I/O polarity
reverse bit (Note) 0 : No reverse
1 : Reverse
Note: Usually set to “0”.
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
AA
A
A
Clock synchronous serial I/O mode
99
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Serial I/O
Table 1.17.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
_______
table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/
_______
RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is
selected to when transfer starts, the TXDi pin outputs a “H”. (If the N-channel open-drain is selected, this
pin is in floating state.)
Table 1.17.4. Input/output pin functions in clock synchronous serial I/O mode
Pin name Function Method of selection
TxDi
(P6
3
, P6
7
, P7
0
)Serial data output
Serial data input
Transfer clock output
Transfer clock input
Programmable I/O port
(Outputs dummy data when performing reception only)
RxDi
(P6
2
, P6
6
, P7
1
)
CLKi
(P6
1
, P6
5
, P7
2
)Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
, 0378
16
) = “0”
Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
, 0378
16
) = “1”
Port P6
1
, P6
5
and P7
2
direction register (bits 1 and 5 at address 03EE
16
,
bit 2 at address 03EF
16
) = “0”
Port P6
2
, P6
6
and P7
1
direction register (bits 2 and 6 at address 03EE
16
,
bit 1 at address 03EF
16
)= “0”
(Can be used as an input port when performing transmission only)
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16
) =“0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
, 037C
16
) = “0”
Port P6
0
, P6
4
and P7
3
direction register (bits 0 and 4 at address 03EE
16
,
bit 3 at address 03EF
16
) = “0”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16)
= “0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
, 037C
16
) = “1”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16
) = “1”
CTS input
RTS output
CTSi/RTSi
(P6
0
, P6
4
, P7
3
)
Clock synchronous serial I/O mode
_______ _______
(when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected)
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Serial I/O
Figure 1.17.10. Typical transmit/receive timings in clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Tc
T
CLK
Stopped pulsing because transfer enable bit = “0”
Data is set in UARTi transmit buffer register
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f
1
, f
8
, f
32
)
n: value set to BRGi
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
CTSi
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Transmit interrupt
request bit (IR)
“0”
“1”
Stopped pulsing because CTS = “H”
Transferred from UARTi transmit buffer register to UARTi transmit register
Shown in ( ) are bit symbols. Cleared to “0” when interrupt request is accepted, or cleared by software
1 / f
EXT
Dummy data is set in UARTi transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
RxDi
Receive complete
flag (Rl)
RTSi
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE)
“0”
“1”
Receive data is taken in
Transferred from UARTi transmit buffer register to UARTi transmit register
Read out from UARTi receive buffer register
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
f
EXT
: frequency of external clock
Transferred from UARTi receive register
to UARTi receive buffer register
Receive interrupt
request bit (IR)
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
• Example of receive timing (when external clock is selected)
Clock synchronous serial I/O mode
101
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Serial I/O
(a) Polarity select function
As shown in Figure 1.17.11, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16)
allows selection of the polarity of the transfer clock.
• When CLK polarity select bit = “1”
Note 2: The CLK pin level when not
transferring data is “L”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
0
T
X
D
i
R
X
D
i
CLK
i
• When CLK polarity select bit = “0”
Note 1: The CLK pin level when not
transferring data is “H”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
T
X
D
i
R
X
D
i
CLK
i
Figure 1.17.11. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.17.12, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16,
037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
Figure 1.17.12. Transfer format
LSB first
• When transfer format select bit = “0”
D0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
T
X
D
i
R
X
D
i
CLK
i
• When transfer format select bit = “1”
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
T
X
D
i
R
X
D
i
CLK
i
MSB first
Note: This applies when the CLK polarity select bit = “0”.
Clock synchronous serial I/O mode
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(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.17.13.)
The multiple pins function is valid only when the internal clock is selected for UART1. Note that when
_______ _______
this function is selected, UART1 CTS/RTS function cannot be used.
Figure 1.17.13. The transfer clock output from the multiple pins function usage
Microcomputer
T
X
D
1
(P6
7
)
CLKS
1
(P6
4
)
CLK
1
(P6
5
)IN
CLK
IN
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
_______ _______
(e) Separate CTS/RTS pins function (UART0)
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
(f) Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 037D
16
) = “1”, and writing to transmit buffer register or
reading from receive buffer register, data is reversed. Figure
1.17.14
shows the example of serial data
logic switch timing.
Figure
1.17.14.
Serial data logic switch timing
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Transfer clock
TxD2
(no reverse)
TxD2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
•When LSB first
Clock synchronous serial I/O mode
103
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Serial I/O
Item Specification
Transfer data format • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock •
When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
•
When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) :
fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)
Transmission/reception control
_______ _______ _______ _______
• CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
-
Transmit buffer empty flag (bit 1 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “0”
_______ _______
- When CTS function selected, CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
- Start bit detection
Interrupt request • When transmitting
generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection • Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Table 1.17.5 and table 1.17.6 list the specifications of the UART mode. Figure 1.17.15
shows the UARTi transmit/receive mode register.
Table 1.17.5. Specifications of UART Mode (1)
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
Clock asynchronous serial I/O (UART) mode
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Serial I/O
Table 1.17.6. Specifications of UART Mode (2)
Item Specification
Select function _______ _______
• Separate CTS/RTS pins (UART0)
_______ _______
UART0 CTS and RTS pins each can be assigned to separate pins
• Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-
computers
•Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
•TXD, RXD I/O polarity switch
This function is reversing TXD port output and RXD port input. All I/O data
level is reversed.
Clock asynchronous serial I/O (UART) mode
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Figure 1.17.15. UARTi transmit/receive mode register in UART mode
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
CKDIR
UARTi transmit / receive mode registers
Internal / external clock
select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Stop bit length select bit
Odd / even parity
select bit
Parity enable bit
Sleep select bit
Symbol Address When reset
U2MR 0378
16
00
16
CKDIR
UART2 transmit / receive mode register
Internal / external clock
select bit
STPS
PRY
PRYE
IOPOL
Must always be “0”
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Stop bit length select bit
Odd / even parity
select bit
Parity enable bit
TxD, RxD I/O polarity
reverse bit (Note)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note: Usually set to “0”.
0
Clock asynchronous serial I/O (UART) mode
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Serial I/O
Table 1.17.7 lists the functions of the input/output pins during UART mode. This table shows the pin
_______ _______
functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the
UARTi operation mode is selected to when transfer starts, the TXDi pin outputs a “H”. (If the N-channel
open-drain is selected, this pin is in floating state.)
Table 1.17.7. Input/output pin functions in UART mode
Pin name Function Method of selection
TxDi
(P6
3
, P6
7
, P7
0
)Serial data output
Serial data input
Programmable I/O port
Transfer clock input
Programmable I/O port
RxDi
(P6
2
, P6
6
, P7
1
)
CLKi
(P6
1
, P6
5
, P7
2
)Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
, 0378
16
) = “0”
Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
) = “1”
Port P6
1
, P6
5
direction register (bits 1 and 5 at address 03EE
16
) = “0”
(Do not set external clock for UART2)
Port P6
2
, P6
6
and P7
1
direction register (bits 2 and 6 at address 03EE
16
,
bit 1 at address 03EF
16
)= “0”
(Can be used as an input port when performing transmission only)
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16
) =“0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
, 037C
16
) = “0”
Port P6
0
, P6
4
and P7
3
direction register (bits 0 and 4 at address 03EE
16
,
bit 3 at address 03EF
16
) = “0”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16)
= “0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
, 037C
16
) = “1”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16
) = “1”
CTS input
RTS output
CTSi/RTSi
(P6
0
, P6
4
, P7
3
)
Clock asynchronous serial I/O (UART) mode
________ _______
(when separate CTS/RTS pins function is not selected)
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Serial I/O
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
Start
bit Parity
bit
TxDi
CTSi
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
“1”
“0”
“1”
“L”
“H”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR) “0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt cause select bit = “0”.
Transfer clock
Tc
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR) “0”
“1”
Shown in ( ) are bit symbols.
Shown in ( ) are bit symbols.
Tc
Transfer clock
D0D1D2D3D4D5D6D7
ST PD0D1D2D3D4D5D6D7SP ST PSP D0D1
ST
Stopped pulsing because transmit enable bit = “0”
Stop
bit
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Data is set in UARTi transmit buffer register
D0D1D2D3D4D5D6D7
ST SP
D8D0D1D2D3D4D5D6D7
ST D8D0D1
ST
SPSP
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop
bit Stop
bit
Data is set in UARTi transmit buffer register.
“0”
SP
Cleared to “0” when interrupt request is accepted, or cleared by software
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Figure 1.17.16. Typical transmit timings in UART mode (UART0, UART1)
Clock asynchronous serial I/O (UART) mode
108
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Serial I/O
Figure 1.17.17. Typical transmit timings in UART mode (UART2)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Start
bit Parity
bit
Cleared to “0” when interrupt request is accepted, or cleared by software
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Tc
SP
Stop
bit
Data is set in UART2 transmit buffer register
Transferred from UART2 transmit buffer register to UARTi transmit register
SP
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
Transmit interrupt
request bit (IR) “0”
“1”
Transfer clock
TxD2
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Shown in ( ) are bit symbols.
Note
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
109
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Serial I/O
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Figure 1.17.18. Typical receive timing in UART mode
_______ _______
(a) Separate CTS/RTS pins function (UART0)
_______ _______ _______
Setting the CTS/RTS separate bit (bit 6 of address 03B016) to "1" inputs/outputs the CTS signal and
_______ _______ _______ _______ _______
RTS signal from different pins. Choose which to use, CTS or RTS, by use of the CTS/RTS function
select bit (bit 2 of address 03A416). This function is effective in UART0 only. With this function chosen,
_______ _______ _______ _______
the user cannot use the CTS/RTS function. Set "0" both to the CTS/RTS function select bit (bit 2 of
_______ _______
address 03AC16) and to the CTS/RTS disable bit (bit 4 of address 03AC16).
(b) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
D
0
Start bit
Sampled “L” Receive data taken in
BRGi count
source
Receive enable bit
RxDi
Transfer clock
Receive
complete flag
RTSi
Stop bit
“1”
“0”
“0”
“1”
“H”
“L”
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Receive interrupt
request bit “0”
“1”
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
is generated by falling edge of start bit
D
7
D
1
Cleared to “0” when interrupt request is accepted, or cleared by software
Microcomputer
T
X
D
0
(P6
3
)
R
X
D
0
(P6
2
)
IN
OUT
CTS
RTS
CTS0 (P6
4
)
RTS0 (P6
0
)
IC
Note : The user cannot use CTS and RTS at the same time.
Clock asynchronous serial I/O (UART) mode
_______ _______
Figure 1.17.19. The separate CTS/RTS pins function usage
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Serial I/O
(c) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 1.17.20 shows the ex-
ample of timing for switching serial data logic.
Figure 1.17.20. Timing for switching serial data logic
ST : Start bit
P : Even parity
SP : Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
SPST D3 D4 D5 D6 D7 PD0 D1 D2
Transfer clock
TxD
2
(no reverse)
TxD
2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
• When LSB first, parity enabled, one stop bit
(d) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
(e) Bus collision detection function (UART2)
This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.17.21
shows the example of detection timing of a buss collision (in UART mode).
Figure 1.17.21. Detection timing of a bus collision (in UART mode)
ST : Start bit
SP : Stop bit
ST
ST
SP
SP
Transfer clock
TxD
2
RxD
2
Bus collision detection
interrupt request signal
“H”
“L”
“H”
“L”
“H”
“L”
“1”
“0”
Bus collision detection
interrupt request bit
“1”
“0”
Clock asynchronous serial I/O (UART) mode
111
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Serial I/O
Item Specification
Transfer data format • Transfer data 8-bit UART mode
(bit 2 through bit 0 of address 037816 = “1012”)
• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 0378
16
= “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D16 = “0”).
Set transfer format to LSB (bit 7 of address 037C16 = “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 0378
16
= “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
Transfer clock •
With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32
(Do not set external clock)
Transmission / reception control
_______ _______
• Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
Other settings • The sleep mode select function is not available for UART2
•
Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D
16
= “1”)
Transmission start condition
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D16) = “1”
- Transmit buffer empty flag (bit 1 of address 037D16) = “0”
R
eceptio
n start condition
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D16) = “1”
- Detection of a start bit
• When transmitting
When data transmission from the UART2 transfer register is completed
(bit 4 of address 037D16 = “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection •
Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TXD2 pin by use of the parity error
signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RXD2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some
extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table
1.17.
8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface).
Interrupt request
generation timing
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLK2 pin.
Note 3: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
Table 1.17.8.
Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Clock asynchronous serial I/O (UART) mode
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Serial I/O
Figure 1.17.22. Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Start
bit Parity
bit
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
“0”
“1”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
1
, f
8
, f
32
)
n : value set to BRG2
Transmit interrupt
request bit (IR)
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
Data is set in UART2 transmit buffer register
SP
A “L” level returns from TxD
2
due to
the occurrence of a parity error.
The level is detected by the
interrupt routine.
The level is
detected by the
interrupt routine.
Receive enable
bit (RE)
Receive complete
flag (RI)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Start
bit Parity
bit
RxD
2
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
•
Transmit interru
p
t cause select bit
=“
0
”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
1
, f
8
, f
32
)
n : value set to BRG2
Receive interrupt
request bit (IR)
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
A “L” level returns from TxD
2
due to
the occurrence of a parity error.
TxD
2
Read to receive buffer Read to receive buffer
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Signal conductor level
(Note 1)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP
SP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP
SP
TxD
2
RxD
2
Signal conductor level
(Note 1)
Transferred from UART2 transmit buffer register to UART2 transmit register
Cleared to “0” when interrupt request is accepted, or cleared by software
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note
Clock asynchronous serial I/O (UART) mode
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Serial I/O
(a) Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you can output an “L”
level from the TXD2 pin when a parity error is detected. In step with this function, the generation timing
of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure
1.17.23 shows the output timing of the parity error signal.
Figure 1.17.23. Output timing of the parity error signal
ST : Start bit
P : Even Parity
SP : Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
Hi-Z
Transfer
clock
RxD
2
TxD
2
Receive
complete flag
“H”
“L”
“H”
“L”
“H”
“L”
“1”
• LSB first
“0”
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TXD2. If you choose the inverse format, D7 data is inverted
and output from TXD2.
Figure 1.17.24 shows the SIM interface format.
Figure 1.17.24. SIM interface format
P : Even parity
D0 D1 D2 D3 D4 D5 D6 D7 P
Transfer
clcck
TxD2
(direct)
TxD2
(inverse) D7 D6 D5 D4 D3 D2 D1 D0 P
Clock asynchronous serial I/O (UART) mode
114
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Serial I/O
Figure
1.17.25
shows the example of connecting the SIM interface. Connect T
X
D
2
and R
X
D
2
and apply pull-
up.
Figure 1.17.25. Connecting the SIM interface
Microcomputer
SIM card
TxD
2
RxD
2
Clock asynchronous serial I/O (UART) mode
115
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Item Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1)
0V to AVCC (VCC)
Operating clock φAD (Note 2)
VCC = 5V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
Resolution 8-bit or 10-bit (selectable)
Absolute precision VCC = 5V • Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN7 input : ±3LSB
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected) : ±7LSB
VCC = 3V • Without sample and hold function (8-bit resolution)
±2LSB
Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins 8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
A-D conversion start condition
• Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49
φ
AD cycles
,
10-bit resolution: 59
φ
AD cycles
• With sample and hold function
8-bit resolution: 28
φ
AD cycles
,
10-bit resolution: 33
φ
AD cycles
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling
amplifier. Pins P10
0
to P10
7
, P9
5
, and P9
6
also function as the analog signal input pins. The direction registers of
these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7
16
) can be
used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (V
REF
) when the A-D
converter is not used. Doing so stops any current flowing into the resistance ladder from V
REF
, reducing the power
dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D7
16
to connect V
REF
.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low
8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 1.18.1 shows the performance of the A-D converter. Figure 1.18.1 shows the block diagram of the A-
D converter, and Figures 1.18.2 and 1.18.3 show the A-D converter-related registers.
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the
φ
AD frequency to 250kHz min.
With the sample and hold function, set the
φ
AD frequency to 1MHz min.
Table 1.18.1. Performance of A-D converter
116
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A-D Converter
Figure 1.18.1. Block diagram of A-D converter
1/2
φ
AD
1/2
fAD
A-D conversion rate
selection
(03C1
16
, 03C0
16
)
(03C3
16
, 03C2
16
)
(03C5
16
, 03C4
16
)
(03C7
16
, 03C6
16
)
(03C9
16
, 03C8
16
)
(03CB
16
, 03CA
16
)
(03CD
16
, 03CC
16
)
(03CF
16
, 03CE
16
)
CKS1=1
CKS0=0
0 0 : Normal operation
0 1 : ANEX0
1 0 : ANEX1
1 1 : External op-amp mode
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
A-D register 4(16)
A-D register 5(16)
A-D register 6(16)
A-D register 7(16)
Resistor ladder
ANEX1
ANEX0
Successive conversion register
OPA1,OPA0=0,1
OPA0=1
OPA1=1
OPA1,OPA0=1,1
AN0
AN1
AN2
AN3
AN5
AN6
AN7
A-D control register 0 (address 03D616)
A-D control register 1 (address 03D716)
Vref
VIN
Data bus high-order
Data bus low-order
VREF
AN4
OPA1,OPA0=0,0
VCUT=0
AVSS VCUT=1
CKS0=1
CKS1=0
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
Decoder
Comparator
OPA1, OPA0
Addresses
117
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Figure 1.18.2. A-D converter-related registers (1)
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit 0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
MD0
MD1
Trigger select bit 0 : Software trigger
1 : AD
TRG
trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT
OPA0
Vref connect bit
OPA1
A-D operation mode
select bit 1 0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
0 : Vref not connected
1 : Vref connected
External op-amp
connection mode bit
WR
b2 b1 b0
b4 b3
When single sweep and repeat sweep
mode 0 are selected
0 0 : AN
0
, AN
1
(2 pins)
0 1 : AN
0
to AN
3
(4 pins)
1 0 : AN
0
to AN
5
(6 pins)
1 1 : AN
0
to AN
7
(8 pins)
b1 b0
When repeat sweep mode 1 is selected
0 0 : AN
0
(1 pin)
0 1 : AN
0
, AN
1
(2 pins)
1 0 : AN
0
to AN
2
(3 pins)
1 1 : AN
0
to AN
3
(4 pins)
b1 b0
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
b7 b6
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
118
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Figure 1.18.3. A-D converter-related registers (2)
A-D control register 2 (Note)
Symbol Address When reset
ADCON2 03D4
16
0000XXX0
2
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion method
select bit 0 : Without sample and hold
1 : With sample and hold
Bit symbol Bit name Function R W
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A
A
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out
to be “0”.
A-D register i
Symbol Address When reset
ADi(i=0 to 7)
03C0
16
to 03CF
16
Indeterminate
Eight low-order bits of A-D conversion result
Function R W
(b15) b7b7 b0 b0
(b8)
• During 10-bit mode
Two high-order bits of A-D conversion result
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
• During 8-bit mode
When read, the content is indeterminate
A
A
SMP
Reserved bit Always set to “0”
A
A
000
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A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. Table 1.18.2 shows the specifications of one-shot mode. Figure 1.18.4 shows the A-D control regis-
ter in one-shot mode.
Table 1.18.2. One-shot mode specifications
Figure 1.18.4. A-D conversion register in one-shot mode
A-D control register 0 (Note 1)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select
bit
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0
MD0
MD1 Trigger select bit 0 : Software trigger
1 : AD
TRG
trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0: f
AD
/4 is selected
1: f
AD
/2 is selected
CKS0
WR
00
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin
select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT
OPA0
Vref connect bit
OPA1
A-D operation mode
select bit 1 0 : Any mode other than repeat sweep
mode 1
1 : Vref connected
External op-amp
connection mode bit 0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
WR
Invalid in one-shot mode
0
0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected (Note 2)
b2 b1 b0
0 0 : One-shot mode (Note 2)
b4 b3
CH0
b7 b6
1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Frequency select bit1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
AA
A
AA
A
AA
AA
A
A
AA
AA
A
A
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
Item Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition
•
End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing
End of A-D conversion
Input pin One of AN0 to AN7, as selected
Reading of result of A-D converter
Read A-D register corresponding to selected pin
120
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(2) Repeat mode
I
n repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
Table 1.18.3 shows the specifications of repeat mode. Figure 1.18.5 shows the A-D control register in
repeat mode.
A-D control register 0 (Note 1)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0
MD0
MD1 Trigger select bit 0 : Software trigger
1 : AD
TRG
trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin
select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT
OPA0
Vref connect bit
OPA1
A-D operation mode
select bit 1
1 : Vref connected
External op-amp
connection mode bit
WR
01
Invalid in repeat mode
0
0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected (Note 2)
b2 b1 b0
0 1 : Repeat mode (Note 2)
b4 b3
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
b7 b6
1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
0 : Any mode other than repeat sweep mode 1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.18.5. A-D conversion register in repeat mode
Item Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Star condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin One of AN0 to AN7, as selected
Reading of result of A-D converter
Read A-D register corresponding to selected pin
Table 1.18.3. Repeat mode specifications
121
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(3) Single sweep mode
I
n single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 1.18.4 shows the specifications of single sweep mode. Figure 1.18.6 shows the A-D
control register in single sweep mode.
Table 1.18.4. Single sweep mode specifications
Figure 1.18.6. A-D conversion register in single sweep mode
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 1 0 : Single sweep mode
MD0
MD1
Trigger select bit 0 : Software trigger
1 : AD
TRG
trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note 1)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT
OPA0
Vref connect bit
0 : Any mode other than repeat sweep mode 1
OPA1
A-D operation mode
select bit 1
1 : Vref connected
External op-amp
connection mode
bit (Note 2)
WR
10
Invalid in single sweep mode
0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
b4 b3
When single sweep and repeat sweep mode 0
are selected
0 0 : AN
0
, AN
1
(2 pins)
0 1 : AN
0
to AN
3
(4 pins)
1 0 : AN
0
to AN
5
(6 pins)
1 1 : AN
0
to AN
7
(8 pins)
b1 b0
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
b7 b6
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Item Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Start condition Writing “1” to A-D converter start flag
Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing
End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
122
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 1.18.5 shows the specifications of repeat sweep mode 0. Figure 1.18.7 shows the
A-D control register in repeat sweep mode 0.
Figure 1.18.7. A-D conversion register in repeat sweep mode 0
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 1 1 : Repeat sweep mode 0
MD0
MD1
Trigger select bit 0 : Software trigger
1 : ADTRG trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
WR
A-D control register 1 (Note 1)
Symbol Address When reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT
OPA0
Vref connect bit
0 : Any mode other than repeat sweep mode 1
OPA1
A-D operation mode
select bit 1
1 : Vref connected
External op-amp
connection mode
bit (Note 2)
WR
11
Invalid in repeat sweep mode 0
0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither “01” nor “10” can be selected with the external op-amp connection mode bit.
b4 b3
When single sweep and repeat sweep mode 0
are selected
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
b1 b0
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
b7 b6
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Frequency select bit 1 0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
AA
A
AA
A
AA
Item Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
Table 1.18.5. Repeat sweep mode 0 specifications
123
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Item Specification
Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 1.18.6 shows the specifications of repeat sweep mode 1. Figure
1.18.8 shows the A-D control register in repeat sweep mode 1.
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 1 1 : Repeat sweep mode 1
MD0
MD1
Trigger select bit 0 : Software trigger
1 : AD
TRG
trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note 1)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT
OPA0
Vref connect bit
1 : Repeat sweep mode 1
OPA1
A-D operation mode
select bit 1
1 : Vref connected
External op-amp
connection mode
bit (Note 2)
WR
11
Invalid in repeat sweep mode 1
1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
b4 b3
When repeat sweep mode 1 is selected
0 0 : AN
0
(1 pin)
0 1 : AN
0
, AN
1
(2 pins)
1 0 : AN
0
to AN
2
(3 pins)
1 1 : AN
0
to AN
3
(4 pins)
b1 b0
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
b7 b6
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
AA
AA
A
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
Figure 1.18.8. A-D conversion register in repeat sweep mode 1
Table 1.18.6. Repeat sweep mode 1 specifications
124
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28
φ
AD cycle is
achieved with 8-bit resolution and 33
φ
AD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the
corresponding A-D register. The speed of A-D conversion depends on the response of the external op-
eration amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.18.9 is an example of how to
connect the pins in external operation amp mode.
Analog
input
External op-amp
AN
0
AN
7
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
ANEX1
ANEX0
Resistor ladder
Successive conversion register
Comparator
Figure 1.18.9. Example of external op-amp connection mode
125
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of
this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the
target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 1.19.1 lists the performance of the D-A converter. Figure 1.19.1 shows the block diagram of the D-A
converter. Figure 1.19.2 shows the D-A control register. Figure 1.19.3 shows the D-A converter equivalent
circuit.
Item Performance
Conversion method R-2R method
Resolution 8 bits
Analog output pin 2 channels
Table 1.19.1. Performance of D-A converter
AAAA
P9
3
/DA
0
AAAA
P9
4
/DA
1
Data bus low-order bits
D-A register0 (8)
R-2R resistor ladder
D-A0 output enable bit
D-A register1 (8)
R-2R resistor ladder
D-A1 output enable bit
(Address 03D8
16
)
(Address 03DA
16
)
Figure 1.19.1. Block diagram of D-A converter
126
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
Figure 1.19.2. D-A control register
Figure 1.19.3. D-A converter equivalent circuit
D-A control register Symbol Address When reset
DACON 03DC16 0016
b7 b6 b5 b4 b3 b2 b1 b0
D-A0 output enable bit DA0E
Bit symbol Bit name Function R W
0 : Output disabled
1 : Output enabled
D-A1 output enable bit 0 : Output disabled
1 : Output enabled
DA1E
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
D-A register Symbol Address When reset
DAi (i = 0,1) 03D816, 03DA16 Indeterminate
WR
b7 b0
Function R W
Output value of D-A conversion
A
AA
A
A
AA
AA
A
AA
V
REF
AV
SS
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
2R
DA0
MSB LSB
D-A0 output enable bit
"0"
"1"
D-A0 register0
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A
16
.
Note 2: The same circuit as this is also used for D-A1.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to
00
16
so that no current flows in the resistors Rs and 2Rs.
127
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom-
puter uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com-
pleted in two machine cycles.
Figure 1.20.1 shows the block diagram of the CRC circuit. Figure 1.20.2 shows the CRC-related registers.
Figure 1.20.3 shows the calculation example using the CRC calculation circuit
Figure 1.20.2. CRC-related registers
Figure 1.20.1. Block diagram of CRC circuit
AAAAAA
Eight low-order bits
AAAAAAA
Eight high-order bits
Data bus high-order bits
Data bus low-order bits
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAA
AAAAAAA
CRC data register (16)
CRC input register (8)
AAAAAAAAAAAA
AAAAAAAAAAAA
CRC code generating circuit
x
16
+ x
12
+ x
5
+ 1
(Addresses 03BD
16
, 03BC
16
)
(Address 03BE
16
)
Symbol Address When reset
CRCD 03BD
16
, 03BC
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
CRC data register
WR
CRC calculation result output register
Function Values that
can be set
0000
16
to FFFF
16
Symbo Address When reset
CRCIN 03BE
16
Indeterminate
b7 b0
CRC input register
WR
Data input register
Function Values that
can be set
00
16
to FF
16
AA
A
AA
A
128
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC
Figure 1.20.3. Calculation example using the CRC calculation circuit
b15 b0
(1) Setting 000016 CRC data register CRCD
[03BD16, 03BC16]
b0b7
b15 b0
(2) Setting 0116 CRC input register CRCIN
[03BE16]
2 cycles
After CRC calculation is complete
CRC data register CRCD
[03BD16, 03BC16]
118916
Stores CRC code
b0b7
b15 b0
(3) Setting 2316 CRC input register CRCIN
[03BE16]
After CRC calculation is complete
CRC data register CRCD
[03BD16, 03BC16]
0A4116
Stores CRC code
The code resulting from sending 01
16
in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
(X
16
+ X
12
+ X
5
+ 1), becomes the remainder resulting from dividing (1000 0000) X
16
by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 1189
16
in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
1000 1000
LSB MSB
LSB MSB
98 1 1
Modulo-2 operation is
operation that complies
with the law given below.
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
129
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Programmable I/O Ports
There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is
an input-only port and has no built-in pull-up resistance.
Figures 1.21.1 to 1.21.4 show the programmable I/O ports. Figure 1.21.5 shows the I/O pins.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.21.6 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 1.21.7 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.21.8 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P5
is invalid.
130
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.21.1. Programmable I/O ports (1)
P5
7
, P6
0
, P6
1
, P6
4
, P6
5
,
P7
2
to P7
4
, P7
6
, P8
0
Data bus
Pull-up selection
Output
“1”
Input to respective peripheral functions
(Note)
Direction register
Port latch
P6
3
, P6
7
Data bus
Pull-up selection
Output
“1”
(Note)
Direction register
Port latch
Data bus
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
, P3
0
to P3
7
,
P4
0
to P4
7
, P5
0
to P5
4
,
P5
6
Pull-up selection
(Note)
Direction register
Port latch
P5
5
, P6
2
, P6
6
, P7
5
, P7
7
,
P8
1
to P8
4
, P9
0
to P9
2
,
P9
7
Data bus
Pull-up selection
Input to respective peripheral functions
(Note)
Direction register
Port latch
Note : symbolizes a parasitic diode.
Do not apply a voltage higher than V
CC
to each port.
131
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.21.2. Programmable I/O ports (2)
Data bus
P8
2
to P8
4
(Note 1)
Direction register
Port latch
Pull-up selection
Input to respective peripheral functions
P7
0
Data bus
Direction register
Port latch output
“1”
(Note 2)
P7
1
Data bus
Direction register
Port latch
Input to respective peripheral functions
(Note 2)
P8
5
Data bus
NMI interrupt input
(Note 1)
Note 1 : symbolizes a parasitic diode.
Do not apply a voltage higher than V
CC
to each port.
Note 2 : symbolizes a parasitic diode.
132
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.21.3. Programmable I/O ports (3)
P93, P94
D-A output enabled
P95, P96, P100 to P103
(inside dotted-line not included)
P104 to P107
(inside dotted-line included)
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
Pull-up selection
Pull-up selection
Analog input
Analog input D-A output enabled
(Note)
(Note)
Note : symbolizes a parasitic diode.
Do not apply a voltage higher than VCC to each port.
133
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.21.4. Programmable I/O ports (4)
P8
7
P8
6
fc
Rf
Rd
Note : symbolizes a parasitic diode.
Do not apply a voltage higher than V
CC
to each port.
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
Pull-up selection
Pull-up selection
Input to respective peripheral functions
(Note)
(Note)
output
“1”
BYTE BYTE signal input
(Note 1)
CNVSS CNVSS signal input
(Note 1)
(Note 1)
RESET RESET signal input
(Note 2)
(Note 2)
Note 1 : symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each pin.
Note 2 : A parasitic diode on the VCC side is added to the mask ROM version.
Do not apply a voltage higher than Vcc to each pin.
Figure 1.21.5. I/O pins
134
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.21.6. Direction register
Port Pi direction register (Note)
Symbol Address When reset
PDi (i = 0 to 10, except 8) 03E2
16
, 03E3
16
, 03E6
16
, 03E7
16
, 03EA
16
00
16
03EB
16
, 03EE
16
, 03EF
16
, 03F3
16
, 03F6
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PDi_0 Port Pi
0
direction register
PDi_1 Port Pi
1
direction register
PDi_2 Port Pi
2
direction register
PDi_3 Port Pi
3
direction register
PDi_4 Port Pi
4
direction register
PDi_5 Port Pi
5
direction register
PDi_6 Port Pi
6
direction register
PDi_7 Port Pi
7
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 10 except 8)
Port P8 direction register
Symbol Address When reset
PD8
03F2
16
00X00000
2
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PD8_0 Port P8
0
direction register
PD8_1 Port P8
1
direction register
PD8_2 Port P8
2
direction register
PD8_3 Port P8
3
direction register
PD8_4 Port P8
4
direction register
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
PD8_6 Port P8
6
direction register
PD8_7 Port P8
7
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
Note: Set bit 2 of protect register (address 000A
16
) to “1” before rewriting to
the port P9 direction register.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
135
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi register
Symbol Address When reset
Pi (i = 0 to 10, except 8) 03E016, 03E116, 03E416, 03E516, 03E816 Indeterminate
03E916, 03EC16, 03ED16, 03F116, 03F416
Indeterminate
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Pi_0 Port Pi
0
register
Pi_1 Port Pi
1
register
Pi_2 Port Pi
2
register
Pi_3 Port Pi
3
register
Pi_4 Port Pi
4
register
Pi_5 Port Pi
5
register
Pi_6 Port Pi
6
register
Pi_7 Port Pi
7
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data (Note)
(i = 0 to 10 except 8)
Port P8 register
Symbol Address When reset
P8 03F016 Indeterminate
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
P8_0 Port P80 register
P8_1 Port P81 register
P8_2 Port P82 register
P8_3 Port P83 register
P8_4 Port P84 register
P8_5 Port P85 register
P8_6 Port P86 register
P8_7 Port P87 register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P8
5
)
0 : “L” level data
1 : “H” level data
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note : Since P7
0
and P7
1
are N-channel open drain ports, the data is high-impedance.
Figure 1.21.7. Port register
136
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.21.8. Pull-up control register
Pull-up control register 0
Symbol Address When reset
PUR0 03FC
16
00
16
Bit name Function Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PU00 P0
0
to P0
3
pull-up
PU01 P0
4
to P0
7
pull-up
PU02 P1
0
to P1
3
pull-up
PU03 P1
4
to P1
7
pull-up
PU04 P2
0
to P2
3
pull-up
PU05 P2
4
to P2
7
pull-up
PU06 P3
0
to P3
3
pull-up
PU07 P3
4
to P3
7
pull-up
Pull-up control register 1
Symbol Address When reset
PUR1 03FD
16
00
16
Bit name Function Bit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
PU10 P4
0
to P4
3
pull-up
PU11 P4
4
to P4
7
pull-up
PU12 P5
0
to P5
3
pull-up
PU13 P5
4
to P5
7
pull-up
PU14 P6
0
to P6
3
pull-up
PU15 P6
4
to P6
7
pull-up
PU16 P7
0
to P7
3
pull-up (Note)
PU17 P7
4
to P7
7
pull-up
Pull-up control register 2
Symbol Address When reset
PUR2 03FE
16
00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PU20 P8
0
to P8
3
pull-up
PU21 P8
4
to P8
7
pull-up
(Except P8
5
)
PU22 P9
0
to P9
3
pull-up
PU23 P9
4
to P9
7
pull-up
PU24 P10
0
to P10
3
pull-up
PU25 P10
4
to P10
7
pull-up
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Note: Since P7
0
and P7
1
are N-channel open drain ports, pull-up is not available for them.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
137
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pin name Connection
Ports P0 to P10
(excluding P8
5
)
X
OUT
(Note)
AV
SS
, V
REF
, BYTE
AV
CC
After setting for input mode, connect every pin to V
SS
via a resistor; or
after setting for output mode, leave these pins open.
Open
Connect to V
CC
Connect to V
SS
Note: With external clock input to X
IN
pin.
NMI Connect via resistor to V
CC
(pull-up)
CNV
SS
Connect via resistor to V
SS
(pull-down)
Table 1.21.1. Example connection of unused pins in single-chip mode
Pin name Connection
Ports P6 to P10
(excluding P8
5
)
AV
SS
, V
REF
AV
CC
After setting for input mode, connect every pin to V
SS
or V
CC
via a resistor; or
after setting for output mode, leave these pins open.
Open
Connect to V
CC
Connect to V
SS
Note: With external clock input to X
IN
pin.
HOLD, RDY, NMI Connect via resistor to V
CC
(pull-up)
BHE, ALE, HLDA,
X
OUT
(Note), BCLK
Connect via resistor to V
SS
(pull-down) in the memory expansion mode
CNV
SS
Connect via resistor to V
CC
(pull-up) in the microprocessor mode
Figure 1.21.9. Example connection of unused pins
Port P0 to P10 (except for P8
5
)
(Input mode)
·
·
·
(Input mode)
(Output mode)
NMI
XOUT
AVCC
BYTE
AVSS
VREF
Microcomputer
VCC
VSS
In single-chip mode
Port P6 to P10 (except for P8
5
)
(Input mode)
·
·
·
(Input mode)
(Output mode)
NMI
XOUT
AVCC
AVSS
VREF
Open
Microcomputer
VCC
VSS
In memory expansion mode or
in microprocessor mode
HOLD
RDY
ALE
BCLK
BHE
HLDA
Open
Open Open
·
·
··
·
·
0.47µs
CNVSS
0.47µs
CNVSS(memory expansion mode)
CNVSS(microprocessor mode)
Table 1.21.2.
Example connection of unused pins in memory expansion mode and microprocessor mode
138
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Timer A (timer mode)
Usage Precaution
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by underflow
or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with
a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading the
timer Ai register after setting a value in the timer Ai register with a count halted but before the counter
starts counting gets a proper value.
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
Timer A (one-shot timer mode)
(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the timer Ai interrupt request bit does not becomes “1”.
Timer A (pulse width modulation mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
Timer B (timer mode, event counter mode)
139
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the
WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction
queue are prefetched and then the program stops. So put at least four NOPs in succession either to
the WAIT instruction or to the instruction that sets the every-clock stop bit to 1.
Stop Mode and Wait Mode
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-
D conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
A-D Converter
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
Timer B (pulse period/pulse width measurement mode)
Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number
and interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 00000
16
will then be set to “0”.
Reading address 00000
16
by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an
interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to
set a value in the stack pointer before accepting an interrupt.
_______
When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning
_______
the first instruction immediately after reset, generating any interrupts including the NMI interrupt is
prohibited.
140
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
(4) External interrupt ________ ________
• When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to
"1". After changing the polarity, set the interrupt request bit to "0".
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ; Four NOP instructions are required when using HOLD function.
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ; Push Flag register onto stack
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt
request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt
control register after the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled,
the interrupt request bit is not set sometimes even if the interrupt request for that register has
been generated. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : AND, OR, BCLR, BSET
_______
(3) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a
resistor (pull-up) if unused. Be sure to work on it. _______
• Do not get either into stop mode or into wait mode with the NMI pin set to “L”.
141
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Built-in PROM version
(1) All built-in PROM versions
High voltage is required to program to the built-in PROM. Be careful not to apply excessive voltage.
Be especially careful during power-on.
(2) One Time PROM version
One Time PROM versions shipped in blank (M30612E4FP, M30612E4GP, M30610ECFP,
M30610ECGP), of which built-in PROMs are programmed by users, are also provided. For these
microcomputers, a programming test and screening are not performed in the assembly process and
the following processes. Therefore ROM write defectiveness occurs around 5 %. To improve their
reliability after programming, we recommend to program and test as flow shown in Figure 1.22.1
before use.
(3) EPROM version
Programming with PROM programmer
Screening (Note)
(Leave at 150˚C for 40 hours)
Verify test PROM programmer
Function check in target device
Note: Never expose to 150˚C exceeding 100 hours.
Figure 1.22.1. Programming and test flow for One Time PROM version
• Cover the transparent glass window with a shield or others during the read mode because exposing
to sun light or fluorescent lamp can cause erasing the information.
A shield to cover the transparent window is available from Mitsubishi Electric Corp. Be careful that
the shield does not touch the EPROM lead pins.
• Clean the transparent glass before erasing. Fingers’ flat and paste disturb the passage of ultraviolet
rays and may affect badly the erasure capability.
• The EPROM version is a tool only for program development (for evaluation), and do not use it for the
mass product run.
External ROM version
The external ROM version is operated only in microprocessor mode, so be sure to perform the following:
• Connect CNVSS pin to VCC.
• Fix the processor mode bit to “112”
142
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Items to be submitted when ordering masked ROM version
Please submit the following when ordering masked ROM products:
(1) Mask ROM confirmation form
(2) Mark specification sheet
(3) ROM data : EPROMs or floppy disks
*: In the case of EPROMs, there sets of EPROMs are required per pattern.
*: In the case of floppy disks, 3.5-inch double-sided high-density disk (IBM format) is required per pattern.
143
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Table 1.24.1. Absolute maximum ratings
Operating ambient temperature
Parameter Unit
Input voltage
Analog supply voltage
Supply voltage
Output voltage
X
OUT
V
O
–0.3 to Vcc+0.3
–0.3 to Vcc+0.3
P
d
Power dissipation
Storage temperature
Ta=25 C
–0.3 to 6.5
Rated value
–0.3 to 6.5 V
V
V
C
Condition
V
I
AVcc
Vcc
T
stg
T
opr
Symbol
C
mW
V
–65 to 150
300
–20 to 85 / –40 to 85
P3
0
to P3
7
, P4
0
to P4
7,
P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7,
P8
0
to P8
7
,
P0
0
to P0
7
, P1
0
to P1
7,
P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7,
P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7,
P8
0
to P8
4,
P0
0
to P0
7
, P1
0
to P1
7,
P2
0
to P2
7
,
RESET, V
REF
, X
IN
P9
0
to P9
7
, P10
0
to P10
7,
P8
6
,P8
7
, P9
0
to P9
7,
P10
0
to P10
7,
P7
0
, P7
1
, CNVss, BYTE
Input voltage
V
I
–0.3 to 6.5
Output voltageV
O
P7
0
, P7
1
V
–0.3 to 6.5 V
V
CC
= AV
CC
V
CC
= AV
CC
(Note 3)
(Note 3)
(Note 1, Note 3)
(Note 3)
(Note 2)
Note 1: When writing to EPROM ,only CNVSS is –0.3 to 13 (V) .
Note 2: Specify a product of –40 to 85°C to use it.
Note 3: –0.3V to 6.5V for M30610M8A, M30610MAA, M30610MCA, M30612M4A, M30612M8A, M30612MAA, M30612MCA,
M30610SA and M30612SA.
Otherwise, –0.3V to 7.0V is used.
144
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1,
P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be
80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max.
Note 3: Specify a product of –40 to 85°C to use it.
Note 4: The relationship between main clock input frequency and power supply voltage is as below.
Table 1.24.2. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = –20 to
85oC / –40 to 85oC (Note 3) unless otherwise specified)
2.7 5.5
Typ. Max. Unit
Parameter
Vcc 5.0
Supply voltage
Symbol Min Standard
Analog supply voltage
VccAVcc V
V0
0
Analog supply voltage
Supply voltage
V
IH
V
IL
Vss
AVss
0.8Vcc
V
V
V
V
V
0.8Vcc
0.5Vcc
Vcc
Vcc
Vcc
0.2Vcc0
LOW input voltage
HIGH input voltage P7
2
to P7
7
, P8
0
to P8
7
, P9
0
to P9
7
, P10
0
to P10
7
,
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
, P3
0
(during single-chip mode)
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
, P3
0
(data input function during memory expansion
and microprocessor modes)
P3
1
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7,
P6
0
to P6
7
,
V
X
IN
, RESET, CNV
SS
, BYTE
P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
7
, P10
0
to P10
7
,
P3
1
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7,
P6
0
to P6
7
,
X
IN
, RESET, CNV
SS
, BYTE
I
OH (avg)
HIGH average output
current
mA
mA
V
V
0.2Vcc0
00.16Vcc
I
OH (peak)
HIGH peak output
current
-5.0
-10.0
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
,P3
0
to P3
7
,
P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
,P7
2
to P7
7
,
P8
0
to P8
4,
P8
6,
P8
7,
P9
0
to P9
7,
P10
0
to P10
7
LOW peak output
current 10.0
5.0
mA
f
(X
IN
)
Main clock input oscillation
frequency
LOW average output
current
I
OL (peak)
mA
I
OL (avg)
10
f
(Xc
IN
)
Subclock oscillation frequency
kHz5032.768
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
, P3
0
(during single-chip mode)
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
, P3
0
(data input function during memory expansion
and microprocessor modes)
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
,P3
0
to P3
7
,
P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
,P7
2
to P7
7
,
P8
0
to P8
4,
P8
6,
P8
7,
P9
0
to P9
7,
P10
0
to P10
7
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
,P3
0
to P3
7
,
P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
,P7
0
to P7
7
,
P8
0
to P8
4,
P8
6,
P8
7,
P9
0
to P9
7,
P10
0
to P10
7
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
,P3
0
to P3
7
,
P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
,P7
0
to P7
7
,
P8
0
to P8
4,
P8
6,
P8
7,
P9
0
to P9
7,
P10
0
to P10
7
V
CC
=4.0V to 5.5V
V
CC
=2.7V to 4.0V 5 X V
CC
–10.000 MHz
0.8Vcc V6.5
P7
0
, P7
1
With wait
No wait
V
CC
=4.0V to 5.5V
V
CC
=2.7V to 4.0V
0
0
0
0
10
2.31
X
V
CC
+0.760
MHz
MHz
MHz
Main clock input oscillation frequency
(No wait)
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
10.0
3.5
0.0 2.7 4.2 5.5
Operating maximum
frequency
[MH
Z
]
Supply voltage
[V]
(BCLK: no division)
5 X V
CC
–10.000MH
Z
Main clock input oscillation frequency
(With wait)
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
10.0
7.0
0.0 2.7 4.2 5.5
Operating maximum
frequency
[MH
Z
]
Supply voltage
[V]
(BCLK: no division)
2.31 X V
CC
–0.760MH
Z
145
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Table 1.24.3.
Electrical characteristics (referenced to V
CC
= 5V, V
SS
= 0V at Ta = 25
o
C, f(X
IN
) =
10MH
Z
unless otherwise specified)
VCC = 5V
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
V
V4.7
V
X
OUT
3.0
3.0
V2.0
0.45 V
V
X
OUT
2.0
2.0
3.0I
OH
=-5mA
I
OH
=-1mA
I
OH
=-200µA
I
OH
=-0.5mA
I
OL
=5mA
I
OL
=1mA
I
OL
=200µA
I
OL
=0.5mA
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7
, P8
0
to P8
4
,
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7
, P8
0
to P8
4
,
HIGHPOWER
LOWPOWER
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
HIGHPOWER
LOWPOWER
P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
4
,
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
HIGHPOWER
LOWPOWER
X
COUT
3.0
1.6 V
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
4
,
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
V
T+-
V
T-
CLK
2
,TA2
OUT
to TA4
OUT
,NMI, 0.2 0.8 V
TB0
IN
to TB2
IN
, INT
0
to INT
2
,
AD
TRG
, CTS
0
to
CTS2
, CLK
0
to
HOLD, RDY, TA0
IN
to TA4
IN
,
V
X
COUT
0
0
HIGHPOWER
LOWPOWER
Symbol Parameter Unit
Standard
Min Typ. Max.
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
Hysteresis
With no load applied
With no load applied
With no load applied
With no load applied
I
IH
I
IL
V
RAM
Icc
V
T+-
V
T-
0.2 1.8 V
5.0 µA
2.0 V
1.0 µA
mA
RESET
20.0
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
,
P9
0
to P9
7
, P10
0
to P10
7,
X
IN
, RESET, CNVss, BYTE
V
I
=5V
V
I
=0V -5.0
19.0 38.0
f(X
IN
)=10MHz
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
,
P9
0
to P9
7
, P10
0
to P10
7,
X
IN
, RESET, CNVss, BYTE
4.0 µA
f(X
CIN
)=32kHz 90.0 µA
R
fXIN
R
fXCIN
X
IN
X
CIN
6.0
1.0
R
PULLUP
50.0
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7
, P8
0
to P8
4
,
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
V
I
=0V 30.0 167.0
Hysteresis
HIGH input
current
LOW input
current
Pull-up
resistance
Feedback resistance
Feedback resistance
RAM retention voltage
Power supply current
µA
When clock is stopped
In single-chip
mode, the
output pins
are open
and other
pins are V
SS
Square wave, no division
Square wave
f(X
CIN
)=32kHz
Ta=85°C
when clock is stopped
Ta=25°C
when clock is stopped
Measuring condition
KI
0
to KI
3
, RxD
0
to RxD
2
k
M
M
When a WAIT instruction is
executed(Note)
kΩ
MΩ
MΩ
Note: With one timer operated using fc32.
146
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Table 1.24.4.
A-D conversion characteristics (referenced to V
CC
= AV
CC
= V
REF
= 5V, V
SS
= AV
SS
=
0V
at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
VCC = 5V
µs
Standard
Min. Typ. Max.
Resolution
Absolute
accuracy
Bits
LSB
V
REF
=
V
CC
±3
10
Symbol Parameter Measuring condition Unit
V
REF
= V
CC
= 5V
R
LADDER
t
CONV
Ladder resistance
Conversion time
(10bit)
Reference voltage
Analog input voltage
k
V
V
IA
V
REF
V0
2
10
V
CC
V
REF
40
3.3
Conversion time
(8bit) 2.8
t
CONV
t
SAMP
Sampling time
0.3
V
REF
=
V
CC
Sample & hold function not available
Sample & hold function available(10bit)
AN
0
to AN
7
input
ANEX0, ANEX1 input,
External op-amp connection mode
V
REF
=V
CC
= 5V
LSB
LSB
±7
Sample & hold function available(8bit)
V
REF
= V
CC
= 5V
±2 LSB
Min. Typ. Max.
t
su
R
O
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Bits
%
k
mA
I
VREF
1.0
1.5
8
3
Symbol Parameter Measuring condition Unit
20104µs
(
Note
)
Standard
µs
µs
±3
Table 1.24.5. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V
at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
Note:
This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “00
16
”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
kΩ
kΩ
147
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.24.6. External clock input
f(BCLK) X 2
(Note)
(Note)
(Note)
40
30
0
0
40
0
Note: Calculated according to the BCLK frequency as follows:
40
Max.
External clock rise time
ns
t
r
Min.
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
f
ParameterSymbol Unit
Standard
15
100
40
40 15
Min.
Data input setup time
ns
t
su(DB-RD)
t
su(RDY-BCLK )
ParameterSymbol Unit
Max.
Standard
ns
RDY input setup time
Data input hold time
ns
t
h(RD-DB)
t
h(BCLK -RDY)
ns
RDY input hold time
ns
HOLD input setup time
t
su(HOLD-BCLK )
ns
HOLD input hold time
t
h(BCLK-HOLD )
Data input access time (no wait)
ns
t
ac1(RD-DB)
ns
ns
t
ac2(RD-DB)
t
ac3(RD-DB)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
ns
t
d(BCLK-HLDA )
HLDA output delay time
t
ac1(RD – DB) = f(BCLK) X 2 – 45
10
9
[ns]
t
ac2(RD – DB) = f(BCLK) X 2 – 45
3 X 10
9
[ns]
t
ac3(RD – DB) = – 45
3 X 10
9
[ns]
Table 1.24.7. Memory expansion and microprocessor modes
VCC = 5V
148
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Standard
Max.
ns
TAi
IN
input LOW pulse width
t
w(TAL)
Min. ns
ns
Unit
Standard
Max.
Min. ns
ns
ns
Unit
Standard
Max.
Min. ns
ns
ns
Unit
Standard
Max.
Min. ns
ns
Unit
Standard
Max.
Min. ns
ns
ns
Unit
ns
ns
TAi
IN
input HIGH pulse width
t
w(TAH)
ParameterSymbol
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
t
w(TAH)
t
w(TAL)
Symbol Parameter
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
Symbol Parameter
t
c(TA)
TAi
IN
input cycle time
TAi
OUT
input cycle time
TAi
OUT
input HIGH pulse width
TAi
OUT
input LOW pulse width
TAi
OUT
input setup time
TAi
OUT
input hold time
t
c(UP)
t
w(UPH)
t
w(UPL)
t
su(UP-T
IN
)
t
h(T
IN-
UP)
40
100
40
400
200
200
200
100
100
100
100
2000
1000
1000
400
400
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.24.8. Timer A input (counter input in event counter mode)
Table 1.24.9. Timer A input (gating input in timer mode)
Table 1.24.10. Timer A input (external trigger input in one-shot timer mode)
Table 1.24.11. Timer A input (external trigger input in pulse width modulation mode)
Table 1.24.12. Timer A input (up/down input in event counter mode)
VCC = 5V
149
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.24.13. Timer B input (counter input in event counter mode)
ns
ns
ns
ns
ns
ns
ns
Standard
Max.Min.
TBiIN input cycle time (counted on one edge)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
ns
ns
ns
tc(TB)
tw(TBH)
tw(TBL)
ParameterSymbol Unit
tc(TB)
tw(TBL)
tw(TBH)
ns
ns
ns
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
TBiIN input cycle time (counted on both edges)
Standard
Max.
Min. ns
ns
tc(TB)
tw(TBH)
Symbol Parameter Unit
tw(TBL) ns
TBiIN input HIGH pulse width
TBiIN input cycle time
TBiIN input LOW pulse width
Standard
Max.
Min. ns
ns
tc(TB)
Symbol Parameter Unit
tw(TBL) ns
tw(TBH) TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Standard
Max.
Min. ns
ns
tc(AD)
tw(ADL)
Symbol Parameter Unit
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
Standard
Max.
Min. ns
ns
tw(INH)
tw(INL)
Symbol Parameter Unit
INTi input LOW pulse width
INTi input HIGH pulse width
Standard
Max.Min.
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
tc(CK)
tw(CKH)
tw(CKL)
ParameterSymbol Unit
td(C-Q)
tsu(D-C)
th(C-Q) TxDi hold time
RxDi input setup time
TxDi output delay time
th(C-D) RxDi input hold time
100
40
40
80
80
200
400
200
200
400
200
200
1000
125
250
250
200
100
100
0
30
90
80
Table 1.24.14. Timer B input (pulse period measurement mode)
Table 1.24.15. Timer B input (pulse width measurement mode)
Table 1.24.16. A-D trigger input
Table 1.24.17. Serial I/O
_______
Table 1.24.18. External interrupt INTi inputs
VCC = 5V
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Electrical characteristics (Vcc = 5V)
Symbol Standard
Measuring condition Max.Min.
Parameter Unit
td(BCLK-AD) Address output delay time 25 ns
th(BCLK-AD) Address output hold time (BCLK standard) 4 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) 4 ns
td(BCLK-ALE) ALE signal output delay time 25 ns
th(BCLK-ALE) ALE signal output hold time – 4 ns
td(BCLK-RD) RD signal output delay time 25 ns
th(BCLK-RD) RD signal output hold time 0 ns
td(BCLK-WR) WR signal output delay time 25 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(BCLK-DB) Data output delay time (BCLK standard) 40 ns
th(BCLK-DB) Data output hold time (BCLK standard) 4ns
th(WR-DB) Data output hold time (WR standard)(Note2) 0 ns
td(DB-WR) Data output delay time (WR standard) ns
(Note1)
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK) X 2
10 9– 40 [ns]
td(BCLK-CS) Chip select output delay time 25 ns
th(RD-AD) Address output hold time (RD standard) 0ns
th(WR-AD) Address output hold time (WR standard) 0ns
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
DBi
R
C
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
VCC = 5V
Figure 1.24.1
Table 1.24.19. Memory expansion mode and microprocessor mode (no wait)
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Electrical characteristics (Vcc = 5V)
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
VCC = 5V
Figure 1.24.1
Table 1.24.20. Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Symbol Standard
Measuring condition
Max.Min.
Parameter Unit
t
d(BCLK-AD)
Address output delay time 25 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 4 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 4 ns
t
d(BCLK-ALE)
ALE signal output delay time 25 ns
t
h(BCLK-ALE)
ALE signal output hold time – 4 ns
t
d(BCLK-RD)
RD signal output delay time 25 ns
t
h(BCLK-RD)
RD signal output hold time 0 ns
t
d(BCLK-WR)
WR signal output delay time 25 ns
t
h(BCLK-WR)
WR signal output hold time 0 ns
t
d(BCLK-DB)
Data output delay time (BCLK standard) 40 ns
t
h(BCLK-DB)
Data output hold time (BCLK standard) 4ns
t
h(WR-DB)
Data output hold time (WR standard)(Note2) 0 ns
t
d(DB-WR)
Data output delay time (WR standard) ns
(Note1)
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK)
10
9
– 40 [ns]
t
d(BCLK-CS)
Chip select output delay time 25 ns
t
h(RD-AD)
Address output hold time (RD standard) 0ns
t
h(WR-AD)
Address output hold time (WR standard) 0ns
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – V
OL
/ V
CC
)
by a circuit of the right figure.
For example, when V
OL
= 0.2V
CC
, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2V
CC
/ V
CC
)
= 6.7ns.
DBi
R
C
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Electrical characteristics (Vcc = 5V)
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
VCC = 5V
Table 1.24.21. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Symbol Standard
Measuring condition
Max.Min.
Parameter Unit
t
d(BCLK-AD)
Address output delay time 25 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 4 ns
t
d(BCLK-CS)
Chip select output delay time 25 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 4 ns
nst
h(RD-AD)
Address output hold time (RD standard)
(Note)
t
d(BCLK-RD)
RD signal output delay time 25 ns
t
h(BCLK-RD)
RD signal output hold time 0 ns
nst
h(WR-AD)
Address output hold time (WR standard)
(Note)
t
d(BCLK-WR)
WR signal output delay time 25 ns
t
d(BCLK-DB)
Data output delay time (BCLK standard) 40 ns
t
h(BCLK-DB)
Data output hold time (BCLK standard) 4 ns
t
d(DB-WR)
Data output delay time (WR standard)
(Note)
ns
t
d(BCLK-ALE)
ALE signal output delay time (BCLK standard) 25 ns
t
h(BCLK-ALE)
ALE signal output hold time (BCLK standard) – 4 ns
t
h(ALE-AD)
ALE signal output hold time (Adderss standard) 50 ns
t
h(BCLK-WR)
WR signal output hold time 0 ns
nst
h(RD-CS)
Chip select output hold time (RD standard)
(Note)
t
h(WR-CS)
Chip select output hold time (WR standard)
(Note)
ns
t
d(AD-RD)
Post-address RD signal output delay time ns0
t
d(AD-WR)
Post-address WR signal output delay time ns0
t
dZ(RD-AD)
Address output floating start time ns8
t
h(WR-DB)
Data output hold time (WR standard) ns
(Note)
Note: Calculated according to the BCLK frequency as follows:
th(RD – AD) = f(BCLK) X 2
10
9
[ns]
th(WR – AD) = f(BCLK) X 2
10
9
[ns]
th(RD – CS) = f(BCLK) X 2
10
9
[ns]
th(WR – CS) = f(BCLK) X 2
10
9
[ns]
td(DB – WR) = f(BCLK) X 2
10
9
– 40 [ns]
X 3
td(AD – ALE) = f(BCLK) X 2
10
9
– 25 [ns]
th(WR – DB) = f(BCLK) X 2
10
9
[ns]
t
d(AD-ALE)
ALE signal output delay time (Address standard) ns
(Note)
Figure 1.24.1
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Electrical characteristics (Vcc = 5V)
Figure 1.24.1. Port P0 to P10 measurement circuit
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
30pF
Timing
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
VCC = 5V
t
su(D–C)
TAiIN input
TAiOUT input
During event counter mode
TBiIN input
CLKi
TxDi
RxDi
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(AD)
t
w(ADL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
t
h(T
IN
–UP)
t
su(UP–T
IN
)
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
TAiOUT input
(Up/down input)
INTi input
ADTRG input
Figure 1.24.2. VCC=5V timing diagram (1)
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Timing (Vcc = 5V)
VCC = 5V
Measuring conditions :
• V
CC
=5V
• Input timing voltage : Determined with V
IL
=1.0V, V
IH
=4.0V
• Output timing voltage : Determined with V
OL
=2.5V, V
OH
=2.5V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5
0
to P5
2
(Valid with or without wait)
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P4
0
to P4
3
.
t
h(BCLK–HOLD)
t
su(HOLD–BCLK)
(Valid only with wait)
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Hi–Z
RDY input
tsu(RDY–BCLK) th(BCLK–RDY)
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
Figure 1.24.3. VCC=5V timing diagram (2)
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Timing (Vcc = 5V)
BCLK
CSi
ALE
–4ns.min
RD
25ns.max 0ns.min
4ns.min
4ns.min
Hi–Z
DB
0ns.min
ADi
BHE
Read timing
BCLK
CSi
ALE
25ns.max 0ns.min
4ns.min
4ns.min
Hi-Z
DB
40ns.max 4ns.min
(tcyc/2–40)ns.min
ADi
BHE
Write timing
t
d(BCLK–AD)
t
d(BCLK–ALE)
t
h(BCLK–ALE)
t
SU(DB–RD)
t
h(BCLK-AD)
t
d(BCLK–WR)
t
h(BCLK–DB)
t
d(BCLK–RD)
t
d(BCLK–ALE)
40ns.min
t
ac1(RD–DB)
Memory Expansion Mode and Microprocessor Mode
(With no wait)
WR,WRL,
WRH
t
d(BCLK–CS)
25ns.max
tcyc
t
h(BCLK–CS)
t
h(RD–CS)
0ns.min
25ns.max
t
h(BCLK–AD)
t
h(RD–AD)
0ns.min
t
h(BCLK–RD)
25ns.max
t
h(RD–DB)
t
d(BCLK–CS)
25ns.max
t
h(BCLK–CS)
tcyc
t
h(WR–CS)
0ns.min
t
d(BCLK–AD)
25ns.max
25ns.max
t
h(BCLK–ALE)
–4ns.min
t
h(WR–AD) 0ns.min
t
h(BCLK–WR)
t
d(BCLK–DB)
t
d(DB–WR)
t
h(WR–DB)
0ns.min
VCC = 5V
Figure 1.24.4. VCC=5V timing diagram (3)
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Timing (Vcc = 5V)
BCLK
CSi
ALE
RD
4ns.min
Hi–Z
DB
40ns.min 0ns.min
ADi
BHE
Read timing
BCLK
CSi
ALE
4ns.min
th(WR–AD)
ADi
BHE
(tcyc–40)ns.min 0ns.min
DBi
Write timing
td(BCLK–RD)
0ns.min
0ns.min
th(RD–AD)
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with: VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with: VOL=0.8V, VOH=2.0V
WR,WRL,
WRH
td(BCLK–CS)
25ns.max
tcyc
th(BCLK–CS)
4ns.min
th(RD–CS)
0ns.min
th(BCLK–AD)
td(BCLK–AD)
25ns.max
td(BCLK–ALE) 25ns.max th(BCLK–ALE)
–4ns.min
th(BCLK–RD)
0ns.min
25ns.max
tac2(RD–DB)
th(RD–DB)
tSU(DB–RD)
td(BCLK–CS)
25ns.max
tcyc
th(BCLK–CS)
4ns.min
th(WR–CS)
0ns.min
th(BCLK–AD)
td(BCLK–AD)
25ns.max
td(BCLK–ALE)
25ns.max th(BCLK–ALE)
–4ns.min
th(BCLK–WR)
0ns.min
td(BCLK–WR)
25ns.max
th(BCLK–DB)
4ns.min
td(BCLK–DB)
40ns.max
td(DB–WR) th(WR–DB)
VCC = 5V
Figure 1.24.5. VCC=5V timing diagram (4)
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Timing (Vcc = 5V)
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
BCLK
CSi
ALE
RD
4ns.min
tcyc
ADi
BHE
ADi
/DBi
t
d(AD–ALE)
Read timing
0ns.min
BCLK
CSi
ALE
–4ns.min
4ns.min
4ns.min
tcyc
ADi
BHE
ADi
/DBi
Write timing
Address
Measuring conditions :
• V
CC
=5V
• Input timing voltage : Determined with
V
IL
=0.8V, V
IH
=2.5V
• Output timing voltage : Determined with V
OL
=0.8V, V
OH
=2.0V
(tcyc/2)ns.min
AddressData input
(tcyc/2)ns.min
t
d(BCLK–ALE)
(tcyc/2)ns.min
t
h(WR–CS)
Address
(tcyc*3/2–40)ns.min
t
d(BCLK–ALE) (tcyc/2)ns.min
(tcyc/2-25)ns.min
Address
25ns.max
t
SU(DB–RD)
tac3(RD–DB)
(tcyc/2)ns.min
t
h(ALE–AD)
50ns.min
t
d(AD–RD)
0ns.min
t
dz(RD–AD)
8ns.max
t
d(AD–WR)
0ns.min
Data output
WR,WRL,
WRH
t
d(BCLK–CS)
25ns.max
t
h(RD–CS)
t
h(BCLK–CS)
4ns.min
t
h(BCLK–AD)
t
h(RD–DB)
0ns.min
40ns.min
25ns.max
t
d(BCLK–AD)
–4ns.min
t
h(BCLK–ALE)
t
d(BCLK–RD)
25ns.max
t
h(RD–AD)
t
h(BCLK–RD)
0ns.min
t
d(BCLK–CS)
25ns.max
t
h(BCLK–CS)
t
h(BCLK–DB)
4ns.min
t
h(WR–DB)
t
d(DB–WR)
t
h(BCLK–AD)
t
d(AD–ALE)
(tcyc/2–25)ns.min
t
d(BCLK–AD)
25ns.max
25ns.max
t
h(BCLK–ALE)
25ns.max
t
d(BCLK–WR)
t
h(BCLK–WR)
t
h(WR–AD)
t
d(BCLK–DB)
40ns.max
VCC = 5V
Figure 1.24.6. VCC=5V timing diagram (5)
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Electrical characteristics (Vcc = 3V)
VCC = 3V
Table 1.24.22. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) =
7MHZ, with wait)
Note: With one timer operated using fc32.
Symbol
V
OH
HIGH output voltage
V
OH
V
OL
LOW output
voltage
LOW output voltage
V
OL
HIGH output
voltage
Standard
Typ. Unit
Measuring condition
V
V
X
OUT
2.5
2.5
V0.5
V
X
OUT
0.5
0.5
Min Max.
2.5
Parameter
I
OH
=-1mA
I
OH
=-0.1mA
I
OH
=-50µA
I
OL
=1mA
I
OL
=0.1mA
I
OL
=50µA
P0
0
to P0
7
,P1
0
to P1
7
,P2
0
to P2
7
,
P0
0
to P0
7
,P1
0
to P1
7
,P2
0
to P2
7
,
P3
0
to P3
7
,P4
0
to P4
7
,P5
0
to P5
7
,
P3
0
to P3
7
,P4
0
to P4
7
,P5
0
to P5
7
,
P6
0
to P6
7
,P7
2
to P7
7
,P8
0
to P8
4
,
HIGHPOWER
LOWPOWER
P8
6
,P8
7
,P9
0
to P9
7
,P10
0
to P10
7
HIGHPOWER
LOWPOWER
P6
0
to P6
7
,P7
0
to P7
7
,P8
0
to P8
4
,
P8
6
,P8
7
,P9
0
to P9
7
,P10
0
to P10
7
HIGHPOWER
LOWPOWER
HIGH output voltage X
COUT
With no load applied
With no load applied 3.0
1.6 V
Hysteresis
Hysteresis
HIGH input
current
I
IH
LOW input
current
I
IL
V
RAM
RAM retention voltage
Icc Power supply current
V
T+-
V
T-
V
T+-
V
T-
0.2 0.8 V
0.2 1.8 V
P0
0
to P0
7
,P1
0
to P1
7
,P2
0
to P2
7
,
P3
0
to P3
7
,P4
0
to P4
7
,P5
0
to P5
7
,
P6
0
to P6
7
,P7
0
to P7
7
,P8
0
to P8
7
,
P9
0
to P9
7
,P10
0
to P10
7,
4.0 µA
µA
When clock is stopped
2.0 V
Square wave, no division
1.0 µA
mA
20.0
RESET
X
IN
, RESET, CNVss, BYTE
V
I
=3V
V
I
=0V -4.0
6.0 15.0
f(X
IN
)=7MHz
P0
0
to P0
7
,P1
0
to P1
7
,P2
0
to P2
7
,
P3
0
to P3
7
,P4
0
to P4
7
,P5
0
to P5
7
,
P6
0
to P6
7
,P7
0
to P7
7
,P8
0
to P8
7
,
P9
0
to P9
7
,P10
0
to P10
7,
X
IN
, RESET, CNVss, BYTE
0.9 µA
Square wave
f(X
CIN
)=32kHz 40.0 µA
2.8 µA
R
fXIN
R
fXCIN
Feedback resistance X
IN
Feedback resistance X
CIN
10.0
3.0
M
M
R
PULLUP
120.0
k
P0
0
to P0
7
,P1
0
to P1
7
,P2
0
to P2
7
,
P3
0
to P3
7
,P4
0
to P4
7
,P5
0
to P5
7
,
P6
0
to P6
7
,P7
2
to P7
7
,P8
0
to P8
4
,
P8
6
,P8
7
,P9
0
to P9
7
,P10
0
to P10
7
LOW output voltage V
X
COUT
0
0
With no load applied
With no load applied
HIGHPOWER
LOWPOWER
V
I
=0V 66.0 500.0
In single-chip
mode, the
output pins
are open
and other
pins are V
SS
Pull-up
resistance
f(X
CIN
)=32kHz
f(X
CIN
)=32kHz
Ta=85°C
when clock is stopped
Ta=25°C
when clock is stopped
When a WAITinstruction is
executed.
Oscillation capacity High
(Note)
When a WAIT instruction is
executed.
Oscillation capacity Low
(Note)
CLK
2
,TA2
OUT
to TA4
OUT
,NMI,
TB0
IN
to TB2
IN
, INT
0
to INT
2
,
AD
TRG
, CTS
0
to CTS
2
, CLK
0
to
HOLD, RDY, TA0
IN
to TA4
IN
,
KI
0
to KI
3
, RxD
0
to RxD
2
kΩ
MΩ
MΩ
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Mitsubishi microcomputers
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Electrical characteristics (Vcc = 3V)
Table 1.24.23.
A-D conversion characteristics (referenced to V
CC
= AV
CC
= V
REF
= 3V, V
SS
= AV
SS
=
0V
at Ta = 25oC, f(XIN) = 7MHZ unless otherwise specified)
VCC = 3V
Standard
Min. Typ. Max
tsu
RO
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Bits
%
mAIVREF
1.0
1.0
8
3
Symbol Parameter Measuring condition Unit
20104
(Note)
RLADDER
Ladder resistance
Reference voltage
Analog input voltage
V
VIA
VREF
V0
2.7
10
VCC
VREF
40
Conversion time
(8bit) 14.0tCONV
VREF = VCC
Standard
Min. Typ. Max
Resolution
Absolute accuracy
Bits
LSB
VREF = VCC ±2
10
Symbol Parameter Measuring condition Unit
V
REF
= V
CC
= 3V, φ
AD
= f(X
IN
)/2
Sample & hold function not available (8 bit)
k
µs
k
µs
Table 1.24.24. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V
at Ta = 25oC, f(XIN) = 7MHZ unless otherwise specified)
Note:
This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “00
16
”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
kΩ
kΩ
161
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
9
10
Min.
Data input setup time
ns
t
su(DB-RD)
t
su(RDY-BCLK )
ParameterSymbol Unit
Max.
Standard
RDY input setup time
ns
Data input hold time
nst
h(RD-DB)
t
h(BCLK -RDY)
ns
RDY input hold time
ns
HOLD input setup time
t
su(HOLD-BCLK )
ns
HOLD input hold time
t
h(BCLK-HOLD )
Data input access time (no wait)
nst
ac1(RD-DB)
ns
ns
t
ac2(RD-DB)
t
ac3(RD-DB)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
ns
HLDA output delay time
t
d(BCLK-HLDA)
80
60
0
0
80
0
(Note)
(Note)
(Note)
Note: Calculated according to the BCLK frequency as follows:
100
ns
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
r
t
f
Max.Min.
ParameterSymbol Unit
Standard
External clock rise time
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
143
60
60 18
18
t
ac1(RD – DB) = f(BCLK) X 2 – 90 [ns]
t
ac2(RD – DB) = f(BCLK) X 2 – 90
3 X 10
9
[ns]
t
ac3(RD – DB) = f(BCLK) X 2 – 90
3 X 10
9
[ns]
VCC = 3V
Table 1.24.25. External clock input
Table 1.24.26. Memory expansion and microprocessor modes
162
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Electrical characteristics (Vcc = 3V)
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Standard
Max.Min. UnitParameterSymbol
nst
w(TAL)
TAi
IN
input LOW pulse width 60
nst
c(TA)
TAi
IN
input cycle time 150 nst
w(TAH)
TAi
IN
input HIGH pulse width 60
Standard
Max.Min. UnitParameterSymbol
nst
c(TA)
TAi
IN
input cycle time 600 nst
w(TAH)
TAi
IN
input HIGH pulse width 300 nst
w(TAL)
TAi
IN
input LOW pulse width 300
Standard
Max.Min. UnitParameterSymbol
nst
c(TA)
TAi
IN
input cycle time 300 nst
w(TAH)
TAi
IN
input HIGH pulse width 150 nst
w(TAL)
TAi
IN
input LOW pulse width 150
Standard
Max.Min. UnitParameterSymbol
nst
w(TAH)
TAi
IN
input HIGH pulse width 150 nst
w(TAL)
TAi
IN
input LOW pulse width 150
Standard
Max.Min. UnitParameterSymbol
nst
c(UP)
TAi
OUT
input cycle time 3000 nst
w(UPH)
TAi
OUT
input HIGH pulse width 1500 nst
w(UPL)
TAi
OUT
input LOW pulse width 1500 nst
su(UP-TIN)
TAi
OUT
input setup time 600 nst
h(TIN-UP)
TAi
OUT
input hold time 600
Table 1.24.28. Timer A input (gating input in timer mode)
Table 1.24.29. Timer A input (external trigger input in one-shot timer mode)
Table 1.24.30. Timer A input (external trigger input in pulse width modulation mode)
Table 1.24.31. Timer A input (up/down input in event counter mode)
Table 1.24.27. Timer A input (counter input in event counter mode)
163
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
VCC = 3V
Standard
Max.Min.
ParameterSymbol Unit
nst
c(TB)
TBi
IN
input cycle time (counted on one edge) 150 nst
w(TBH)
TBi
IN
input HIGH pulse width (counted on one edge) 60 nst
w(TBL)
TBi
IN
input LOW pulse width (counted on one edge) 60
t
w(TBH)
nsTBi
IN
input HIGH pulse width (counted on both edges) 160
t
w(TBL)
nsTBi
IN
input LOW pulse width (counted on both edges) 160
t
c(TB)
nsTBi
IN
input cycle time (counted on both edges) 300
Standard
Max.Min.
ParameterSymbol Unit
nst
c(TB)
TBi
IN
input cycle time 600 nst
w(TBH)
TBi
IN
input HIGH pulse width 300
t
w(TBL)
nsTBi
IN
input LOW pulse width 300
Standard
Max.Min.
ParameterSymbol Unit
nst
c(TB)
TBi
IN
input cycle time 600 nst
w(TBH)
TBi
IN
input HIGH pulse width 300
t
w(TBL)
nsTBi
IN
input LOW pulse width 300
Standard
Max.Min.
ParameterSymbol Unit
nst
c(AD)
AD
TRG
input cycle time (trigger able minimum) 1500 nst
w(ADL)
AD
TRG
input LOW pulse width 200
Standard
Max.Min.
ParameterSymbol Unit
nst
w(INH)
INTi input HIGH pulse width 380 nst
w(INL)
INTi input LOW pulse width 380
Standard
Max.Min.
ParameterSymbol Unit
nst
c(CK)
CLKi input cycle time 300 nst
w(CKH)
CLKi input HIGH pulse width 150 nst
w(CKL)
CLKi input LOW pulse width 150
t
h(C-Q)
nsTxDi hold time 0
t
su(D-C)
nsRxDi input setup time 50
t
h(C-D)
nsRxDi input hold time 90
t
d(C-Q)
nsTxDi output delay time 160
Table 1.24.32. Timer B input (counter input in event counter mode)
Table 1.24.33. Timer B input (pulse period measurement mode)
Table 1.24.34. Timer B input (pulse width measurement mode)
Table 1.24.35. A-D trigger input
Table 1.24.36. Serial I/O
_______
Table 1.24.37. External interrupt INTi inputs
164
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Electrical characteristics (Vcc = 3V)
t
d(BCLK-AD)
Address output delay time 60 ns
t
d(BCLK-CS)
Chip select output delay time 60 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 4 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 4 ns
t
d(BCLK-ALE)
ALE signal output delay time 60 ns
t
h(BCLK-ALE)
ALE signal output hold time — 4ns
t
d(BCLK-RD)
RD signal output delay time 60 ns
t
h(BCLK-RD)
RD signal output hold time 0 ns
t
h(RD-AD)
Address output hold time (RD standard) 0ns
t
d(BCLK-WR)
WR signal output delay time 60 ns
t
h(BCLK-WR)
WR signal output hold time 0 ns
t
h(WR-AD)
Address output hold time (WR standard) 0ns
t
d(BCLK-DB)
Data output delay time (BCLK standard) 80 ns
t
h(BCLK-DB)
Data output hold time (BCLK standard) 4ns
t
d(DB-WR)
Data output delay time (WR standard) (Note1) ns
t
h(WR-DB)
Data output hold time (WR standard)(Note2) 0 ns
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK) X 2
10
9
– 80 [ns]
Symbol
Standard
Measuring condition
Max.Min.
Parameter Unit
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – V
OL
/ V
CC
)
by a circuit of the right figure.
For example, when V
OL
= 0.2V
CC
, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2V
CC
/ V
CC
)
=
6
.7n
s
.
DBi
R
C
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
VCC = 3V
Figure 1.24.1
Table 1.24.38. Memory expansion and microprocessor modes (with no wait)
165
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
VCC = 3V
Table 1.24.39. Memory expansion and microprocessor modes
(when accessing external memory area with wait)
t
d(BCLK-AD)
Address output delay time 60 ns
t
d(BCLK-CS)
Chip select output delay time 60 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 4 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 4 ns
t
d(BCLK-ALE)
ALE signal output delay time 60 ns
t
h(BCLK-ALE)
ALE signal output hold time – 4 ns
t
d(BCLK-RD)
RD signal output delay time 60 ns
t
h(BCLK-RD)
RD signal output hold time 0 ns
t
h(RD-AD)
Address output hold time (RD standard) 0ns
t
d(BCLK-WR)
WR signal output delay time 60 ns
t
h(BCLK-WR)
WR signal output hold time 0 ns
t
h(WR-AD)
Address output hold time (WR standard) 0ns
t
d(BCLK-DB)
Data output delay time (BCLK standard) 80 ns
t
h(BCLK-DB)
Data output hold time (BCLK standard) 4ns
t
d(DB-WR)
Data output delay time (WR standard) (Note1) ns
t
h(WR-DB)
Data output hold time (WR standard)(Note2) 0 ns
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK)
10
9
– 80 [ns]
Symbol
Standard
Measuring condition
Max.Min.
Parameter Unit
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – V
OL
/ V
CC
)
by a circuit of the right figure.
For example, when V
OL
= 0.2V
CC
, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2V
CC
/ V
CC
)
= 6.7ns.
DBi
R
C
Figure 1.24.1
166
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
Table 1.24.40. Memory expansion and microprocessor modes
(when accessing external memory area with wait, and select multiplexed bus)
Symbol
Standard
Measuring condition
Max.Min.
Parameter Unit
t
d(BCLK-AD)
Address output delay time 60 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 4 ns
t
d(BCLK-CS)
Chip select output delay time 60 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 4 ns
nst
h(RD-AD)
Address output hold time (RD standard) (Note)
t
d(BCLK-RD)
RD signal output delay time 60 ns
t
h(BCLK-RD)
RD signal output hold time 0 ns
nst
h(WR-AD)
Address output hold time (WR standard) (Note)
t
d(BCLK-WR)
WR signal output delay time 60 ns
t
d(BCLK-DB)
Data output delay time (BCLK standard) 80 ns
t
h(BCLK-DB)
Data output hold time (BCLK standard) 4 ns
t
d(DB-WR)
Data output delay time (WR standard) (Note) ns
t
h(BCLK-ALE)
ALE signal output hold time (BCLK standard) – 4 ns
t
d(AD-ALE)
ALE signal output delay time (Address standard) (Note) ns
t
h(ALE-AD)
ALE signal output hold time(Address standard) 50 ns
t
h(BCLK-WR)
WR signal output hold time 0 ns
nst
h(RD-CS)
Chip select output hold time (RD standard) (Note)
t
h(WR-CS)
Chip select output hold time (WR standard) (Note) ns
t
d(AD-RD)
Post-address RD signal output delay time ns0
t
d(AD-WR)
Post-address WR signal output delay time ns0
t
dZ(RD-AD)
Address output floating start time ns8
t
d(BCLK-ALE)
ALE signal output delay time (BCLK standard) ns60
Note: Calculated according to the BCLK frequency as follows:
th(RD – AD) = f(BCLK) X 2
10
9
[ns]
th(WR – AD) = f(BCLK) X 2
10
9
[ns]
th(RD – CS) = f(BCLK) X 2
10
9
[ns]
th(WR – CS) = f(BCLK) X 2
10
9
[ns]
td(DB – WR) = f(BCLK) X 2
10
9
– 80 [ns]
X 3
td(AD – ALE) = f(BCLK) X 2
10
9
– 60 [ns]
th(WR – DB) = f(BCLK) X 2
10
9
[ns]
t
h(WR-DB)
Data output hold time (WR standard) ns(Note)
Figure 1.24.1
167
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
t
su(D–C)
TAi
IN
input
TAi
OUT
input
During event counter mode
TBi
IN
input
CLKi
TxDi
RxDi
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(AD)
t
w(ADL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
t
h(T
IN
–UP)
t
su(UP–T
IN
)
TAi
IN
input
(When count on falling
edge is selected)
TAi
IN
input
(When count on rising
edge is selected)
TAi
OUT
input
(Up/down input)
INTi input
AD
TRG
input
Figure 1.24.7. VCC=3V timing diagram (1)
168
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
Measuring conditions :
• VCC=3V
• Input timing voltage : Determined with VIL=0.6V, VIH=2.4V
• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P50 to P52
(Valid with or without wait)
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P40 to P43.
th(BCLK–HOLD)
tsu(HOLD–BCLK)
(Valid only with wait)
td(BCLK–HLDA)
td(BCLK–HLDA)
Hi–Z
RDY input
tsu(RDY–BCLK) th(BCLK–RDY)
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
Figure 1.24.8. VCC=3V timing diagram (2)
169
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
Read timing
Write timing
BCLK
CSi
ALE
RD
60ns.max
4ns.min
4ns.min
Hi–Z
DB
0ns.min
ADi
BHE
tcyc
80ns.min
BCLK
CSi
ALE
–4ns.min
60ns.max 0ns.min
4ns.min
Hi–Z
DB
4ns.min
ADi
BHE
tcyc
t
h(BCLK–ALE)
t
h(BCLK–DB)
t
d(BCLK–ALE)
t
d(BCLK–WR)
0ns.min
t
h(WR–AD)
Memory Expansion Mode and Microprocessor Mode
(With no wait)
WR,WRL,
WRH
t
d(BCLK–CS)
60ns.max
t
h(BCLK–CS)
t
h(RD–CS)
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
60ns.max
t
d(BCLK–ALE) –4ns.min
t
h(RD–AD) 0ns.min
t
d(BCLK–RD)
t
h(BCLK–RD)
t
ac1(RD–DB)
t
h(RD–DB)
0ns.min
t
SU(DB–RD)
t
d(BCLK–CS)
t
h(BCLK–CS)
4ns.min
60ns.max
0ns.min
t
h(WR–CS)
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
60ns.max
t
h(BCLK–ALE)
t
h(BCLK–WR)
t
d(BCLK–DB)
t
h(WR–DB)
t
d(DB–WR)
(
tc
y
c/2–80
)
ns.min 0ns.min
80ns.max
0ns.min
VCC = 3V
Figure 1.24.9. VCC=3V timing diagram (3)
170
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
Read timing
Write timing
BCLK
CSi
ALE
RD
4ns.min
4ns.min
Hi–Z
DB
80ns.min
0ns.min
ADi
BHE
t
d(BCLK–WR)
60ns.max
t
h(BCLK–WR)
0ns.min
BCLK
CSi
t
d(BCLK–CS)
60ns.max
t
d(BCLK–AD)
ALE
t
h(BCLK–ALE)
t
h(BCLK–CS)
4ns.min
tcyc 0ns.min
t
h(WR–CS)
0ns.min
t
h(WR–AD)
ADi
BHE
t
d(BCLK–DB) 4ns.min
t
h(BCLK–DB)
t
d(DB–WR)
(tcyc–80)ns.min 0ns.min
t
h(WR–DB)
DBi
t
h(RD–AD)
0ns.min
t
d(BCLK–ALE)
60ns.max
t
SU(DB–RD)
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Measuring conditions :
• VCC=3V
• Input timing voltage : Determined with VIL=0.48V, VIH=1.5V
• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
WR,WRL,
WRH
t
d(BCLK–CS)
60ns.max
t
h(RD–CS)
tcyc
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
–4ns.min
t
h(BCLK–ALE)
60ns.max
t
d(BCLK–RD)
t
h(BCLK–RD) 0ns.min
t
ac2(RD–DB)
t
h(RD–DB) 0ns.min
t
h(BCLK–AD)
60ns.max
t
d(BCLK–ALE) 60ns.max –4ns.min
80ns.max
t
h(BCLK–CS)
4ns.min
VCC = 3V
Figure 1.24.10. VCC=3V timing diagram (4)
171
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Measuring conditions :
• V
CC
=3V
• Input timing voltage : Determined with V
IL
=0.48V,V
IH
=1.5V
• Output timing voltage : Determined with V
OL
=1.5V,V
OH
=1.5V
Read timing
Write timing
0ns.min
BCLK
CSi
ALE
60ns.max –4ns.min
t
h(BCLK–CS)
4ns.min
tcyc
ADi
BHE
80ns.max
t
h(BCLK–DB)
4ns.min
t
d(DB–WR)
(tcyc*3/2–80)ns.min
ADi
/DBi
Address Data output
(tcyc/2)ns.min
Address
(tcyc/2–60)ns.min
t
d(BCLK–ALE)
t
d(BCLK–WR)
4ns.min
BCLK
CSi
t
d(BCLK–CS)
60ns.max
ALE
RD
4ns.min
t
h(BCLK–CS)
4ns.min
tcyc
ADi
BHE
ADi
/DBi t
h(RD–DB)
0ns.min
Address
(tcyc/2)ns.min
Data input
Address
tac3(RD–DB)
t
dz(RD–AD)
8ns.max
t
d(AD–RD)
0ns.min
t
d(AD–WR)
WR,WRL,
WRH
t
h(RD–CS)
t
d(AD–ALE) (tcyc/2–60)ns.min
t
SU(DB–RD)
80ns.min
t
h(ALE–AD)
50ns.min
t
d(BCLK–AD)
60ns.max
60ns.max
t
d(BCLK–ALE)
t
h(BCLK–ALE)
–4ns.min (tcyc/2)ns.min
t
h(RD–AD)
t
h(BCLK–AD)
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
60ns.max
t
d(BCLK–CS)
60ns.max
t
h(WR–CS)
(tcyc/2)ns.min
t
d(BCLK–DB)
t
d(AD–ALE)
t
d(BCLK–AD)
60ns.max
t
h(WR–DB)
(tcyc/2)ns.min
t
h(BCLK–AD)
t
h(WR–AD)
t
h(BCLK–WR)
t
h(BCLK–ALE) 0ns.min
60ns.max
VCC = 3V
Figure 1.24.11. VCC=3V timing diagram (5)
172
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 53B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
Note : Please complete all items marked .
Checksum code for total EPROM area : (hex)
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
The ASCII code for 'M30610M8A-' is shown at right.
The data in this table must be written to address
0000016 to 0000F16.
Both address and data are shown in hex.
'M '= 4D16
0000016
0000116
0000216
0000316
0000416
0000516
0000616
0000716
Address ' A ' = 4116
0000816
0000916
0000A16
0000B16
0000C16
0000D16
0000E16
0000F16
Address
EPROM type :
27C201
Address
0000016
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30610M8A -
ROM(64K)
0000F16
0001016
2FFFF16
3000016
3FFFF16
Microcomputer type No. : M30610M8A-XXXFP M30610M8A-XXXGP
'0 '= 3016
'6 '= 3616
'1 '= 3116
'0 '= 3016
'M '= 4D16
'8 '= 3816
' — ' = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
'3 '= 3316
Supervisor
signature
Receipt
Date :
Section head
signature
Customer
Company
name
Date
issued Date :
TEL
( )
Issuance
signature
Submitted by Supervisor
1. Check sheet
27C401
Address
0000016
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30610M8A -
ROM(64K)
0000F16
0001016
6FFFF16
7000016
7FFFF16
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
In the case of EPROMs
173
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 53B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
The ASCII code for the type No. can be written to EPROM addresses 00000
16
to 0000F
16
by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
EPROM type 27C201
Code entered in
source program .SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.BYTE ' M30610M8A- '
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
.BYTE ' M30610M8A- '
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30610M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30610M8A-XXXGP,
submit the 100P6Q mark specification sheet.
2. Mark specification
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of X
IN
-X
OUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
IN
) = MH
Z
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
In the case of floppy disks
File code : (hex)
Microcomputer type No. : M30610M8A-XXXFP
Mask file name : .MSK (alpha-numeric 8-digit)
M30610M8A-XXXGP
174
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 53B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
4. Special item (Indicate none if there is no specified item)
(2) Which kind of X
CIN
-X
COUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
CIN
) = kH
Z
(3) Which operation mode do you use?
Single-chip mode Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C –20 °C to 75 °C –40 °C to 75 °C
–10 °C to 85 °C –20 °C to 85 °C –40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V 3.2V to 3.7V 3.7V to 4.2V
4.2V to 4.7V 4.7V to 5.2V 5.2V to 5.5V
Thank you cooperation.
175
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
In the case of EPROMs
GZZ SH11 52B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
Note : Please complete all items marked .
Checksum code for total EPROM area : (hex)
(1) Write “FF
16
”
to the lined area.
(2) The area from 00000
16
to 0000F
16
is for storing
data on the product type name.
The ASCII code for 'M30610MAA-' is shown at right.
The data in this table must be written to address
00000
16
to 0000F
16
.
Both address and data are shown in hex.
'
M
'
= 4D
16
00000
16
00001
16
00002
16
00003
16
00004
16
00005
16
00006
16
00007
16
Address '
A
'
= 41
16
00008
16
00009
16
0000A
16
0000B
16
0000C
16
0000D
16
0000E
16
0000F
16
Address
EPROM type :
27C201
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30610MAA -
ROM(96K)
0000F
16
00010
16
27FFF
16
28000
16
3FFFF
16
Microcomputer type No. : M30610MAA-XXXFP M30610MAA-XXXGP
'
0
'
= 30
16
'
6
'
= 36
16
'
1
'
= 31
16
'
0
'
= 30
16
'
M
'
= 4D
16
'
A
'
= 41
16
'
—
'
= 2D
16
FF
16
FF
16
FF
16
FF
16
FF
16
FF
16
'
3
'
= 33
16
Supervisor
signature
Receipt
Date :
Section head
signature
Customer
Company
name
Date
issued Date :
TEL
( )
Issuance
signature
Submitted by Supervisor
1. Check sheet
27C401
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30610MAA -
ROM(96K)
0000F
16
00010
16
67FFF
16
68000
16
7FFFF
16
176
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 52B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
The ASCII code for the type No. can be written to EPROM addresses 00000
16
to 0000F
16
by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30610MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30610MAA-XXXGP,
submit the 100P6Q mark specification sheet.
2. Mark specification
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of X
IN
-X
OUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
IN
) = MH
Z
Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
EPROM type 27C201
Code entered in
source program .SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.BYTE ' M30610MAA- '
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
.BYTE ' M30610MAA- '
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
In the case of floppy disks
File code : (hex)
Microcomputer type No. : M30610MAA-XXXFP
Mask file name : .MSK (alpha-numeric 8-digit)
M30610MAA-XXXGP
177
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 52B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
4. Special item (Indicate none if there is no specified item)
(2) Which kind of X
CIN
-X
COUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
CIN
) = kH
Z
(3) Which operation mode do you use?
Single-chip mode Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C –20 °C to 75 °C –40 °C to 75 °C
–10 °C to 85 °C –20 °C to 85 °C –40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V 3.2V to 3.7V 3.7V to 4.2V
4.2V to 4.7V 4.7V to 5.2V 5.2V to 5.5V
Thank you cooperation.
178
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 51B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
Note : Please complete all items marked .
Checksum code for total EPROM area : (hex)
(1) Write “FF
16
”
to the lined area.
(2) The area from 00000
16
to 0000F
16
is for storing
data on the product type name.
The ASCII code for 'M30610MCA-' is shown at right.
The data in this table must be written to address
00000
16
to 0000F
16
.
Both address and data are shown in hex.
'
M
'
= 4D
16
00000
16
00001
16
00002
16
00003
16
00004
16
00005
16
00006
16
00007
16
Address '
A
'
= 41
16
00008
16
00009
16
0000A
16
0000B
16
0000C
16
0000D
16
0000E
16
0000F
16
Address
EPROM type :
27C201
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30610MCA -
ROM(128K)
0000F
16
00010
16
1FFFF
16
20000
16
3FFFF
16
Microcomputer type No. : M30610MCA-XXXFP M30610MCA-XXXGP
'
0
'
= 30
16
'
6
'
= 36
16
'
1
'
= 31
16
'
0
'
= 30
16
'
M
'
= 4D
16
'
C
'
= 43
16
'
—
'
= 2D
16
FF
16
FF
16
FF
16
FF
16
FF
16
FF
16
'
3
'
= 33
16
Supervisor
signature
Receipt
Date :
Section head
signature
Customer
Company
name
Date
issued Date :
TEL
( )
Issuance
signature
Submitted by Supervisor
1. Check sheet
27C401
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30610MCA -
ROM(128K)
0000F
16
00010
16
5FFFF
16
60000
16
7FFFF
16
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
In the case of EPROMs
179
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 51B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30610MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30610MCA-XXXGP,
submit the 100P6Q mark specification sheet.
2. Mark specification
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of X
IN
-X
OUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
IN
) = MH
Z
Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
The ASCII code for the type No. can be written to EPROM addresses 00000
16
to 0000F
16
by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
EPROM type 27C201
Code entered in
source program .SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.BYTE ' M30610MCA- '
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
.BYTE ' M30610MCA- '
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
In the case of floppy disks
File code : (hex)
Microcomputer type No. : M30610MCA-XXXFP
Mask file name : .MSK (alpha-numeric 8-digit)
M30610MCA-XXXGP
180
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 51B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
4. Special item (Indicate none if there is no specified item)
(2) Which kind of X
CIN
-X
COUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
CIN
) = kH
Z
(3) Which operation mode do you use?
Single-chip mode Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C –20 °C to 75 °C –40 °C to 75 °C
–10 °C to 85 °C –20 °C to 85 °C –40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V 3.2V to 3.7V 3.7V to 4.2V
4.2V to 4.7V 4.7V to 5.2V 5.2V to 5.5V
Thank you cooperation.
181
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
In the case of EPROMs
GZZ SH12 35B <79A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M4A-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
Note : Please complete all items marked .
Checksum code for total EPROM area : (hex)
(1) Write “FF
16
”
to the lined area.
(2) The area from 00000
16
to 0000F
16
is for storing
data on the product type name.
The ASCII code for 'M30612M4A-' is shown at right.
The data in this table must be written to address
00000
16
to 0000F
16
.
Both address and data are shown in hex.
'
M
'
= 4D
16
00000
16
00001
16
00002
16
00003
16
00004
16
00005
16
00006
16
00007
16
Address '
A
'
= 41
16
00008
16
00009
16
0000A
16
0000B
16
0000C
16
0000D
16
0000E
16
0000F
16
Address
EPROM type :
27C201
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30612M4A -
ROM(32K)
0000F
16
00010
16
37FFF
16
38000
16
3FFFF
16
Microcomputer type No. : M30612M4A-XXXFP M30612M4A-XXXGP
'
0
'
= 30
16
'
6
'
= 36
16
'
1
'
= 31
16
'
2
'
= 32
16
'
M
'
= 4D
16
'
4
'
= 34
16
'
—
'
= 2D
16
FF
16
FF
16
FF
16
FF
16
FF
16
FF
16
'
3
'
= 33
16
Supervisor
signature
Receipt
Date :
Section head
signature
Customer
Company
name
Date
issued Date :
TEL
( )
Issuance
signature
Submitted by Supervisor
1. Check sheet
27C401
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30612M4A -
ROM(32K)
0000F
16
00010
16
77FFF
16
78000
16
7FFFF
16
182
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 35B <79A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M4A-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30612M4A-XXXFP, submit the 100P6S mark specification sheet. For the M30612M4A-XXXGP,
submit the 100P6Q mark specification sheet.
2. Mark specification
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(XIN) = MHZ
Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
EPROM type 27C201
Code entered in
source program .SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.BYTE ' M30612M4A- '
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
.BYTE ' M30612M4A- '
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
In the case of floppy disks
File code : (hex)
Microcomputer type No. : M30612M4A-XXXFP
Mask file name : .MSK (alpha-numeric 8-digit)
M30612M4A-XXXGP
183
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 35B <79A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M4A-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
4. Special item (Indicate none if there is no specified item)
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(XCIN) = kHZ
(3) Which operation mode do you use?
Single-chip mode Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C –20 °C to 75 °C –40 °C to 75 °C
–10 °C to 85 °C –20 °C to 85 °C –40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V 3.2V to 3.7V 3.7V to 4.2V
4.2V to 4.7V 4.7V to 5.2V 5.2V to 5.5V
Thank you cooperation.
184
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
In the case of EPROMs
GZZ SH12 34B <79A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
Note : Please complete all items marked .
Checksum code for total EPROM area : (hex)
(1) Write “FF
16
”
to the lined area.
(2) The area from 00000
16
to 0000F
16
is for storing
data on the product type name.
The ASCII code for 'M30612M8A-' is shown at right.
The data in this table must be written to address
00000
16
to 0000F
16
.
Both address and data are shown in hex.
'
M
'
= 4D
16
00000
16
00001
16
00002
16
00003
16
00004
16
00005
16
00006
16
00007
16
Address '
A
'
= 41
16
00008
16
00009
16
0000A
16
0000B
16
0000C
16
0000D
16
0000E
16
0000F
16
Address
EPROM type :
27C201
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30612M8A -
ROM(64K)
0000F
16
00010
16
2FFFF
16
30000
16
3FFFF
16
Microcomputer type No. : M30612M8A-XXXFP M30612M8A-XXXGP
'
0
'
= 30
16
'
6
'
= 36
16
'
1
'
= 31
16
'
2
'
= 32
16
'
M
'
= 4D
16
'
8
'
= 38
16
'
—
'
= 2D
16
FF
16
FF
16
FF
16
FF
16
FF
16
FF
16
'
3
'
= 33
16
Supervisor
signature
Receipt
Date :
Section head
signature
Customer
Company
name
Date
issued Date :
TEL
( )
Issuance
signature
Submitted by Supervisor
1. Check sheet
27C401
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30612M8A -
ROM(64K)
0000F
16
00010
16
6FFFF
16
70000
16
7FFFF
16
185
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 34B <79A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30612M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30612M8A-XXXGP,
submit the 100P6Q mark specification sheet.
2. Mark specification
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of X
IN
-X
OUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
IN
) = MH
Z
Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
The ASCII code for the type No. can be written to EPROM addresses 00000
16
to 0000F
16
by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
EPROM type 27C201
Code entered in
source program .SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.BYTE ' M30612M8A- '
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
.BYTE ' M30612M8A- '
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
In the case of floppy disks
File code : (hex)
Microcomputer type No. : M30612M8A-XXXFP
Mask file name : .MSK (alpha-numeric 8-digit)
M30612M8A-XXXGP
186
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 34B <79A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
4. Special item (Indicate none if there is no specified item)
(2) Which kind of X
CIN
-X
COUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
CIN
) = kH
Z
(3) Which operation mode do you use?
Single-chip mode Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C –20 °C to 75 °C –40 °C to 75 °C
–10 °C to 85 °C –20 °C to 85 °C –40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V 3.2V to 3.7V 3.7V to 4.2V
4.2V to 4.7V 4.7V to 5.2V 5.2V to 5.5V
Thank you cooperation.
187
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
In the case of EPROMs
GZZ SH12 55B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
Note : Please complete all items marked .
Checksum code for total EPROM area : (hex)
(1) Write “FF
16
”
to the lined area.
(2) The area from 00000
16
to 0000F
16
is for storing
data on the product type name.
The ASCII code for 'M30612MAA-' is shown at right.
The data in this table must be written to address
00000
16
to 0000F
16
.
Both address and data are shown in hex.
'
M
'
= 4D
16
00000
16
00001
16
00002
16
00003
16
00004
16
00005
16
00006
16
00007
16
Address '
A
'
= 41
16
00008
16
00009
16
0000A
16
0000B
16
0000C
16
0000D
16
0000E
16
0000F
16
Address
EPROM type :
27C201
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30612MAA -
ROM(96K)
0000F
16
00010
16
27FFF
16
28000
16
3FFFF
16
Microcomputer type No. : M30612MAA-XXXFP M30612MAA-XXXGP
'
0
'
= 30
16
'
6
'
= 36
16
'
1
'
= 31
16
'
2
'
= 32
16
'
M
'
= 4D
16
'
A
'
= 41
16
'
—
'
= 2D
16
FF
16
FF
16
FF
16
FF
16
FF
16
FF
16
'
3
'
= 33
16
Supervisor
signature
Receipt
Date :
Section head
signature
Customer
Company
name
Date
issued Date :
TEL
( )
Issuance
signature
Submitted by Supervisor
1. Check sheet
27C401
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30612MAA -
ROM(96K)
0000F
16
00010
16
67FFF
16
68000
16
7FFFF
16
188
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 55B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30612MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30612MAA-XXXGP,
submit the 100P6Q mark specification sheet.
2. Mark specification
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of X
IN
-X
OUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
IN
) = MH
Z
Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
The ASCII code for the type No. can be written to EPROM addresses 00000
16
to 0000F
16
by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
EPROM type 27C201
Code entered in
source program .SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.BYTE ' M30612MAA- '
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
.BYTE ' M30612MAA- '
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
In the case of floppy disks
File code : (hex)
Microcomputer type No. : M30612MAA-XXXFP
Mask file name : .MSK (alpha-numeric 8-digit)
M30612MAA-XXXGP
189
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 55B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
4. Special item (Indicate none if there is no specified item)
(2) Which kind of X
CIN
-X
COUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
CIN
) = kH
Z
(3) Which operation mode do you use?
Single-chip mode Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C –20 °C to 75 °C –40 °C to 75 °C
–10 °C to 85 °C –20 °C to 85 °C –40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V 3.2V to 3.7V 3.7V to 4.2V
4.2V to 4.7V 4.7V to 5.2V 5.2V to 5.5V
Thank you cooperation.
190
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
In the case of EPROMs
GZZ SH11 54B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
Note : Please complete all items marked .
Checksum code for total EPROM area : (hex)
(1) Write “FF
16
”
to the lined area.
(2) The area from 00000
16
to 0000F
16
is for storing
data on the product type name.
The ASCII code for 'M30612MCA-' is shown at right.
The data in this table must be written to address
00000
16
to 0000F
16
.
Both address and data are shown in hex.
'M '= 4D16
0000016
0000116
0000216
0000316
0000416
0000516
0000616
0000716
Address ' A ' = 4116
0000816
0000916
0000A16
0000B16
0000C16
0000D16
0000E16
0000F16
Address
EPROM type :
27C201
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30612MCA -
ROM(128K)
0000F
16
00010
16
1FFFF
16
20000
16
3FFFF
16
Microcomputer type No. : M30612MCA-XXXFP M30612MCA-XXXGP
'0 '= 3016
'6 '= 3616
'1 '= 3116
'2 '= 3216
'M '= 4D16
'C '= 4316
' — ' = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
'3 '= 3316
Supervisor
signature
Receipt
Date :
Section head
signature
Customer
Company
name
Date
issued Date :
TEL
( )
Issuance
signature
Submitted by Supervisor
1. Check sheet
27C401
Address
00000
16
AAAAA
AAAAA
Product : Area
containing ASCII
code for M30612MCA -
ROM(128K)
0000F
16
00010
16
5FFFF
16
60000
16
7FFFF
16
191
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 54B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30612MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30612MCA-XXXGP,
submit the 100P6Q mark specification sheet.
2. Mark specification
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of X
IN
-X
OUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
IN
) = MH
Z
Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
The ASCII code for the type No. can be written to EPROM addresses 00000
16
to 0000F
16
by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
EPROM type 27C201
Code entered in
source program .SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.BYTE ' M30612MCA- '
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
.BYTE ' M30612MCA- '
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
In the case of floppy disks
File code : (hex)
Microcomputer type No. : M30612MCA-XXXFP
Mask file name : .MSK (alpha-numeric 8-digit)
M30612MCA-XXXGP
192
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 54B <71A1>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
Mask ROM number
4. Special item (Indicate none if there is no specified item)
(2) Which kind of X
CIN
-X
COUT
oscillation circuit is used?
Ceramic resonator Quartz-crystal oscillator
External clock input Other ( )
What frequency do you use?
f(X
CIN
) = kH
Z
(3) Which operation mode do you use?
Single-chip mode Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C –20 °C to 75 °C –40 °C to 75 °C
–10 °C to 85 °C –20 °C to 85 °C –40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V 3.2V to 3.7V 3.7V to 4.2V
4.2V to 4.7V 4.7V to 5.2V 5.2V to 5.5V
Thank you cooperation.
193
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
QFP100-P-1420-0.65 1.58
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
100P6S-A
Plastic 100pin 14✕20mm body QFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.35 ––
I
2
1.3 ––
M
D
14.6 ––
M
E
20.6
10°0°0.1
1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8
03.05
e
e
e
E
c
H
E
1
30
31
81
50
80
51
H
D
D
M
D
M
E
A
F
b
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
LQFP100-P-1414-0.50 Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ––
I
2
1.0 ––
M
D
14.4 ––
M
E
14.4
10°0°0.1
1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
e
E
c
H
E
1
76
75
51
50
26
25
H
D
D
M
D
M
E
A
F
b
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
194
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Differences between M16C/61 group and M30600M8
Type name M16C/61 group M30600M8
Internal memory
size ROM
RAM See Figure 4. ROM Expansion
4 K to 10 K bytes 64 K bytes
10 K bytes
Chip select CS0 30000
16
to FFFFF
16
(besides internal area)
CS1 28000
16
to 2FFFF
16
CS2 08000
16
to 27FFF
16
CS3 04000
16
to 07FFF
16
CS0 90000
16
to FFFFF
16
(besides internal area)
CS1 10000
16
to 8FFFF
16
CS2 08000
16
to 0FFFF
16
CS3 04000
16
to 07FFF
16
Serial I/O 3 channel
(clocked SIO / UART) :2 channel
(clocked SIO / UART / SIM)
2 channel
(clocked SIO / UART)
Port P7
0
to P7
3
function Port P7
0
TA0
OUT
Port P7
1
TA0
IN
Port P7
2
TA1
OUT
Port P7
3
TA1
IN
Port output
style Port P7
0
and Port P7
1
are N-channel
open drain
Others are CMOS
All Ports are CMOS
Interrupt
sources Internal 20 sources
External 5 sources
Software 4 sources
Internal 17 sources
External 5 sources
Software 4 sources
Add 3 sources -trans., recv. and
arbit. for UART2
DMA request DMA0 DMA1
1100 UART2 trans. UART2 trans.
1101 UART2 recv. UART2 recv.
1110 A-D A-D
1111 UART1 trans. UART1 recv.
DMA0 DMA1
1100 UART1 trans. UART1 trans.
1101 UART1 recv. UART1 recv.
1110 A-D A-D
1111 prohibited prohibited
Port P7
0
T
X
D
2
/ TA0
OUT
Port P7
1
R
X
D
2
/ TA0
IN
Port P7
2
CLK
2
/ TA1
OUT
Port P7
3
CTS
2
/ RTS
2
/ TA1
IN
Internal area on memory
expansion mode SFR area 00000
16
to 003FF
16
RAM area 00400
16
to 03FFF
16
ROM area D0000
16
to FFFFF
16
(PM16=0)
ROM area F8000
16
to FFFFF
16
(PM16=1) (Note)
SFR area 00000
16
to 003FF
16
RAM area 00400
16
to 03FFF
16
ROM area D0000
16
to FFFFF
16
(FIX)
Note: M30612M4A/E4 only.
Port P9
3
and P9
4
pull-up set up condition All of the following:
• Pull-up is selected.
• DA output is enabled.
• Input port is selected.
Both of the following:
• Pull-up is selected.
• Input port is selected.
195
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Internal area
AAAA
AAAA
External area(possible to use for external devices)
AAAA
AAAA
Inhibited
M
Me
em
mo
or
ry
y
m
ma
ap
p
C
Co
om
mp
pa
ar
ri
is
so
on
n
00000
16
013FF
16
F8000
16
FFFFF
16
00400
16
Internal RAM
Internal ROM
Memory expansion
mode
SFR area
Microprocessor
mode
10000
16
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Single-chip
mode
003FF
16
F7FFF
16
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
04000
16
Internally
reserved
07FFF
16
08000
16
27FFF
16
28000
16
2FFFF
16
30000
16
FFFFF
16
CS3(16K)
CS2(128K)
CS1(32K)
CS0
(800K:Memory expansion)
(832K:Microprocessor)
M30612M4AMemory area ( ROM 32K bytes, RAM 4K bytes)
CS3(16K)
CS2(32K)
CS1(512K)
CS0
(256K:Memory expansion)
(448K:Microprocessor)
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
00000
16
02BFF
16
F0000
16
FFFFF
16
00400
16
10000
16
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
02C00
16
003FF
16
EFFFF
16
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
M30600M8
90000
16
FFFFF
16
10000
16
8FFFF
16
0FFFF
16
08000
16
07FFF
16
04000
16
D0000
16
CFFFF
16
AAAAA
AAAAA
CFFFF
16
D0000
16
AAAA
AAAA
Internally reserved for ROM(possible to use for external devices under PM16=1)
Internal RAM
SFR area
Internal RAM
SFR area
Internally
reserved
Internally reserved
Internal ROM
External
memory
area
External
memory
area
External
memory
area
Internal ROM Internal ROM
Internally reserved
Internally reserved
Internally reserved
SFR area SFR area SFR area
Internal RAM Internal RAM Internal RAM
Inhibited
Microprocessor
mode Memory expansion
mode Single-chip
mode
Memory area ( ROM 64K bytes, RAM 10K bytes)
External
memory
area
01400
16
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Inhibited
Keep safety first in your circuit designs!
Notes regarding these materials
●Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire
or property damage. Remember to give due consideration to safety when making
your circuit designs, with appropriate measures such as (i) placement of substitutive,
auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.
●These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights, or
any other rights, belonging to Mitsubishi Electric Corporation or a third party.
●Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product data,
diagrams, charts or circuit application examples contained in these materials.
●All information contained in these materials, including product data, diagrams and
charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical
errors. Mitsubishi Electric Corporation assumes no responsibility for any damage,
liability or other loss rising from these inaccuracies or errors.
●
Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Mitsubishi Electric Corporation or an autho-
rized Mitsubishi Semiconductor product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems
for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
●The prior written approval of Mitsubishi Electric Corporation is necessary to reprint
or reproduce in whole or in part these materials.
●If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of
Japan and/or the country of destination is prohibited.
●Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.
MITSUBISHI SEMICONDUCTORS
M16C/61 Group Specification REV.E
Apr. First Edition 1999
Editioned by
Committee of editing of Mitsubishi Semiconductor
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©1999 MITSUBISHI ELECTRIC CORPORATION
