MAX4364/MAX4365
The increase in power delivered by the BTL configura-
tion directly results in an increase in internal power dis-
sipation over the single-ended configuration. The
maximum power dissipation for a given VCC and load is
given by the following equation:
If the power dissipation for a given application exceeds
the maximum allowed for a given package, reduce
VCC, increase load impedance, decrease the ambient
temperature or add heat sinking to the device. Large
output, supply, and ground PC board traces improve
the maximum power dissipation in the package.
Thermal-overload protection limits total power dissipa-
tion in the MAX4364/MAX4365. When the junction tem-
perature exceeds +160°C, the thermal protection
circuitry disables the amplifier output stage. The ampli-
fiers are enabled once the junction temperature cools
by 15°C. This results in a pulsing output under continu-
ous thermal overload conditions as the device heats
and cools.
The MAX4365 TDFN package features an exposed
thermal pad on its underside. This pad lowers the ther-
mal resistance of the package by providing a direct
heat conduction path from the die to the PC board.
Connect the exposed thermal pad to circuit ground by
using a large pad, ground plane, or multiple vias to the
ground plane.
Efficiency
The efficiency of the MAX4364/MAX4365 is calculated
by taking the ratio of the power delivered to the load to
the power consumed from the power supply. Output
power is calculated by the following equations:
where VPEAK is half the peak-to-peak output voltage. In
BTL amplifiers, the supply current waveform is a full-
wave rectified sinusoid with the magnitude proportional
to the peak output voltage and load. Calculate the sup-
ply current and power drawn from the power supply by
the following:
The efficiency of the MAX4364/MAX4365 is:
The device efficiency values in Table 1 are calculated
based on the previous equation and do include the
effects of quiescent current. Note that efficiency is low
at low output-power levels, but remains relatively con-
stant at normal operating, output-power levels.
Component Selection
Gain-Setting Resistors
External feedback components set the gain of both
devices. Resistors RFand RIN (see
Typical Application
Circuit/Functional Diagram
) set the gain of the amplifier
as follows:
Optimum output offset is achieved when RF= 20kΩ.
Vary the gain by changing the value of RIN. When using
the MAX4364/MAX4365 in a high-gain configuration
(greater than 8V/V), a feedback capacitor may be
required to maintain stability (see Figure 2). CFand RF
limit the bandwidth of the device, preventing high-fre-
quency oscillations. Ensure that the pole created by CF
and RFis not within the frequency band of interest.
Input Filter
The input capacitor (CIN), in conjunction with RIN forms
a highpass filter that removes the DC bias from an
incoming signal. The AC-coupling capacitor allows the
amplifier to bias the signal to an optimum DC level.
Assuming zero source impedance, the -3dB point of
the highpass filter is given by:
Choose RIN according to the
Gain-Setting Resistors
section. Choose CIN such that f-3dB is well below the
lowest frequency of interest. Setting f-3dB too high
affects the low-frequency response of the amplifier. Use
capacitors whose dielectrics have low-voltage coeffi-