25AA010A-E/SN - Microchip Technology

25AA010A/25LC010A

Device Selection Table

Features:

• 10 MHz max. Clock Frequency

• Low-Power CMOS Technology:

- Max. Write Current: 5 mA at 5.5V, 10 MHz

- Read Current: 5 mA at 5.5V, 10 MHz

- Standby Current: 5 μA at 5.5V

• 128 x 8-bit Organization

• Write Page mode (up to 16 bytes)

• Sequential Read

• Self-Timed Erase and Write Cycles (5 ms max.)

• Block Write Protection:

- Protect none, 1/4, 1/2 or all of array

• Built-In Write Protection:

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• High Reliability:

- Endurance: 1,000,000 Erase/Write cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• Temperature Ranges Supported:

• Pb-Free and RoHS Compliant

Pin Function Table

Description:

The Microchip Technology Inc. 25XX010A* is a 1 Kbit

Serial Electrically Erasable Programmable Read-Only

Memory (EEPROM). The memory is accessed via a

simple Serial Peripheral Interface (SPI) compatible

serial bus. The bus signals required are a clock input

(SCK) plus separate data in (SI) and data out (SO)

lines. Access to the device is controlled through a Chip

Select (CS) input.

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused,

transitions on its inputs will be ignored, with the

exception of Chip Select, allowing the host to service

higher priority interrupts.

The 25XX010A is available in standard packages

including 8-lead PDIP and SOIC, and advanced

packages including 8-lead MSOP, 8-lead TSSOP and

rotated TSSOP, 8-lead 2x3 DFN, and 6-lead SOT-23.

Package Types (not to scale)

Part Number VCC Range Page Size Temp. Ranges Packages

25AA010A 1.8-5.5V 16 Bytes I P, MS, SN, ST, MC, OT

25LC010A 2.5-5.5V 16 Bytes I, E P, MS, SN, ST, MC, OT

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°Cto+125°C

Name Function

CS Chip Select Input

SO Serial Data Output

WP Write-Protect

VSS Ground

SI Serial Data Input

SCK Serial Clock Input

HOLD Hold Input

VCC Supply Voltage

HOLD

SCK

(P, SN)

(OT)

PDIP/SOIC

X-Rotated TSSOP

HOLD

SCK

(X/ST)

HOLD

SCK

HOLD

SCK

(ST, MS)

TSSOP/MSOP

SOT-23

SCK

HOLD

SCK

(MC)

DFN

1K SPI Bus Serial EEPROM

*25XX010A is used in this document as a generic part number for the

25AA010A and the 25LC010A.

25AA010A/25LC010A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): T

A = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

D001 VIH1High-level Input

Voltage

0.7 VCC VCC+1 V

D002 VIL1Low-level Input

Voltage

-0.3 0.3 VCC VVCC ≥ 2.7V (Note)

D003 VIL2-0.3 0.2 VCC VVCC < 2.7V (Note)

D004 VOL Low-level Output

Voltage

—0.4VIOL = 2.1 mA

D005 VOL —0.2VIOL = 1.0 mA, VCC < 2.5V

D006 VOH High-level Output

Voltage

VCC -0.5 — V IOH = -400 μA

D007 ILI Input Leakage

Current

—±1μACS = VCC, VIN = VSS TO VCC

D008 ILO Output Leakage

Current

—±1μACS = VCC, VOUT = VSS TO VCC

D009 CINT Internal Capacitance

(all inputs and

outputs)

—7pFTA = 25°C, CLK = 1.0 MHz,

VCC = 5.0V (Note)

D010 ICC Read

Operating Current

—

2.5

VCC = 5.5V; FCLK = 10.0 MHz;

SO = Open

VCC = 2.5V; FCLK = 5.0 MHz;

SO = Open

D011 ICC Write —

—

VCC = 5.5V

VCC = 2.5V

D012 ICCS

Standby Current

—

μA

CS = VCC = 5.5V, Inputs tied to VCC or

VSS, TA = +125°C

CS = VCC = 2.5V, Inputs tied to VCC or

VSS, TA = +85°C

Note: This parameter is periodically sampled and not 100% tested.

25AA010A/25LC010A

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

CLK Clock Frequency —

—

MHz

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

CSS CS Setup Time 50

100

150

—

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

CSH CS Hold Time 100

200

250

—

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

CSD CS Disable Time 50 — ns —

5 Tsu Data Setup Time 10

—

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

HD Data Hold Time 20

—

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

RCLK Rise Time — 2 μs(Note 1)

FCLK Fall Time — 2 μs(Note 1)

HI Clock High Time 0.05

0.1

0.15

1000

μs

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

10 TLO Clock Low Time 0.05

0.1

0.15

1000

μs

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

11 TCLD Clock Delay Time 50 — ns —

12 TCLE Clock Enable Time 50 — ns —

13 TVOutput Valid from Clock

Low

—

100

160

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

14 THO Output Hold Time 0 — ns (Note 1)

15 TDIS Output Disable Time —

—

160

4.5V ≤ VCC < 5.5V (Note 1)

2.5V ≤ VCC < 4.5V (Note 1)

1.8V ≤ VCC < 2.5V (Note 1)

16 THS HOLD Setup Time 20

—

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site:

www.microchip.com.

3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete.

25AA010A/25LC010A

TABLE 1-3: AC TEST CONDITIONS

17 THH HOLD Hold Time 20

—

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

18 THZ HOLD Low to Output

High-Z

160

—

4.5V ≤ VCC < 5.5V (Note 1)

2.5V ≤ VCC < 4.5V (Note 1)

1.8V ≤ VCC < 2.5V (Note 1)

19 THV HOLD High to Output

Valid

160

—

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

20 TWC Internal Write Cycle Time

(byte or page)

—5ms(NOTE 3)

21 — Endurance 1M — E/W

Cycles

(NOTE 2)

TABLE 1-2: AC CHARACTERISTICS (CONTINUED)

AC CHARACTERISTICS Industrial (I): T

A = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site:

www.microchip.com.

3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete.

AC Waveform:

VLO = 0.2V —

VHI = VCC - 0.2V (Note 1)

VHI = 4.0V (Note 2)

CL = 100 pF —

Timing Measurement Reference Level

Input 0.5 VCC

Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For VCC > 4.0V

25AA010A/25LC010A

FIGURE 1-1: HOLD TIMING

FIGURE 1-2: SERIAL INPUT TIMING

FIGURE 1-3: SERIAL OUTPUT TIMING

SCK

HOLD

16 16 17

Don’t Care 5

High-Impedance

n + 2 n + 1 n n - 1

n + 2 n + 1 n nn - 1

SCK

711

LSB in

MSB in

High-Impedance

Mode 1,1

Mode 0,0

SCK

MSB out ISB out

Don’t Care

Mode 1,1

Mode 0,0

25AA010A/25LC010A

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 25XX010A is a 128 byte Serial EEPROM designed

to interface directly with the Serial Peripheral Interface

(SPI) port of many of today’s popular microcontroller

families, including Microchip’s PIC® microcontrollers. It

may also interface with microcontrollers that do not

have a built-in SPI port by using discrete I/O lines

programmed properly in firmware to match the SPI

protocol.

The 25XX010A contains an 8-bit instruction register.

The device is accessed via the SI pin, with data being

clocked in on the rising edge of SCK. The CS pin must

be low and the HOLD pin must be high for the entire

operation.

Table 2-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses, and data are transferred MSb first, LSb last.

Data (SI) is sampled on the first rising edge of SCK

after CS goes low. If the clock line is shared with other

peripheral devices on the SPI bus, the user can assert

the HOLD input and place the 25XX010A in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.

2.2 Read Sequence

The device is selected by pulling CS low. The 8-bit

READ instruction is transmitted to the 25XX010A

followed by an 8-bit address. See Figure 2-1 for more

details.

After the correct READ instruction and address are sent,

the data stored in the memory at the selected address

is shifted out on the SO pin. Data stored in the memory

at the next address can be read sequentially by

continuing to provide clock pulses to the slave. The

internal Address Pointer automatically increments to

the next higher address after each byte of data is

shifted out. When the highest address is reached

(7Fh), the address counter rolls over to address 00h

allowing the read cycle to be continued indefinitely. The

read operation is terminated by raising the CS pin

(Figure 2-1).

2.3 Write Sequence

Prior to any attempt to write data to the 25XX010A, the

write enable latch must be set by issuing the WREN

instruction (Figure 2-4). This is done by setting CS low

and then clocking out the proper instruction into the

25XX010A. After all eight bits of the instruction are

transmitted, CS must be driven high to set the write

enable latch. If the write operation is initiated immedi-

ately after the WREN instruction without CS driven high,

data will not be written to the array since the write

enable latch was not properly set.

After setting the write enable latch, the user may

proceed by driving CS low, issuing a WRITE instruction,

followed by the remainder of the address, and then the

data to be written. Up to 16 bytes of data can be sent to

the device before a write cycle is necessary. The only

restriction is that all of the bytes must reside in the

same page. Additionally, a page address begins with

XXXX 0000 and ends with XXXX 1111. If the internal

address counter reaches XXXX 1111 and clock signals

continue to be applied to the chip, the address counter

will roll back to the first address of the page and over-

write any data that previously existed in those

locations.

For the data to be actually written to the array, the CS

must be brought high after the Least Significant bit (D0)

of the nth data byte has been clocked in. If CS is driven

high at any other time, the write operation will not be

completed. Refer to Figure 2-2 and Figure 2-3 for more

detailed illustrations on the byte write sequence and

the page write sequence, respectively. While the write

is in progress, the STATUS register may be read to

check the status of the WIP, WEL, BP1 and BP0 bits

(Figure 2-6). Attempting to read a memory array

location will not be possible during a write cycle. Polling

the WIP bit in the STATUS register is recommended in

order to determine if a write cycle is in progress. When

the write cycle is completed, the write enable latch is

reset.

Note: Page write operations are limited to writing

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page size’) and, end at addresses that are

integer multiples of page size – 1. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

25AA010A/25LC010A

BLOCK DIAGRAM

FIGURE 2-1: READ SEQUENCE

SCK

HOLD

STATUS

I/O Control Memory

Control

Logic

Dec

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp.

R/W Control

Logic

VCC

VSS

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ 0000 x011 Read data from memory array beginning at selected address

WRITE 0000 x010 Write data to memory array beginning at selected address

WRDI 0000 x100 Reset the write enable latch (disable write operations)

WREN 0000 x110 Set the write enable latch (enable write operations)

RDSR 0000 x101 Read STATUS register

WRSR 0000 x001 Write STATUS register

x = don’t care

SCK

0 2345678910111

01000001 XA6A5A4A1A0

76543210

Data Out

High-Impedance

A3A2

Address Byte

12 13 14 15 16 17 18 19 20 21 22 23

Instruction

25AA010A/25LC010A

FIGURE 2-2: BYTE WRITE SEQUENCE

X = don’t care

FIGURE 2-3: PAGE WRITE SEQUENCE

X = don’t care

0 2345678910111

00000001 XA6A5A4A1

A3A2

Address Byte

12 13 14 15 16 17 18 19 20 21 22 23

Instruction Data Byte

A06

7543 210

High-Impedance

Twc

SCK

91011

00000001 76543210

Data Byte 1

SCK

0 23456718

33 34 35 38 39

76543210

Data Byte n (16 max)

SCK

24 26 27 28 29 30 3125 32

76543210

Data Byte 3

76543210

Data Byte 2

36 37

Instruction Address Byte

XA6A5A4A3A1A0

12 13 14 15 16 17 18 19 20 21 22 23

25AA010A/25LC010A

2.4 Write Enable (WREN) and Write

Disable (WRDI)

The 25XX010A contains a write enable latch. See

Table 2-4 for the Write-Protect Functionality Matrix.

This latch must be set before any write operation will be

completed internally. The WREN instruction will set the

latch, and the WRDI will reset the latch.

The following is a list of conditions under which the

write enable latch will be reset:

• Power-up

•WRDI instruction successfully executed

•WRSR instruction successfully executed

•WRITE instruction successfully executed

•WP

pin is brought low

FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)

FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)

SCK

0 2345671

High-Impedance

010000 01

SCK

0 2345671

High-Impedance

010000 0

25AA010A/25LC010A

2.5 Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provides

access to the STATUS register. See Figure 2-6 for the

RDSR timing sequence. The STATUS register may be

read at any time, even during a write cycle. The

STATUS register is formatted as follows:

TABLE 2-2: STATUS REGISTER

The Write-In-Process (WIP) bit indicates whether the

25XX010A is busy with a write operation. When set to

a ‘1’, a write is in progress, when set to a ‘0’, no write

is in progress. This bit is read-only.

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch and is read-only. When set to

a ‘1’, the latch allows writes to the array, when set to a

‘0’, the latch prohibits writes to the array. The state of

this bit can always be updated via the WREN or WRDI

commands regardless of the state of write protection

on the STATUS register. These commands are shown

in Figure 2-4 and Figure 2-5.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user issuing the WRSR instruction, which

is shown in Figure 2-7. These bits are nonvolatile and

are described in more detail in Table 2-3.

FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)

7 654 3 2 1 0

– –––W/RW/R R R

X XXXBP1 BP0 WEL WIP

W/R = writable/readable. R = read-only.

9101112131415

11000000

7654 2 10

Instruction

Data from STATUS Register

High-Impedance

SCK

0 23456718

25AA010A/25LC010A

2.6 Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the

user to write to the nonvolatile bits in the STATUS

WRSR timing sequence. Four levels of protection for the

array are selectable by writing to the appropriate bits in

the STATUS register. The user has the ability to write-

protect none, one, two or all four of the segments of the

array as shown in Table 2-3.

TABLE 2-3: ARRAY PROTECTION

FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

BP1 BP0 Array Addresses

Write-Protected

00 none

01 upper 1/4

(60h-7Fh)

10 upper 1/2

(40h-7Fh)

11 all

(00h-7Fh)

9101112131415

01000000

7654 210

Instruction Data to STATUS Register

High-Impedance

SCK

0 23456718

Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register

sequence.

25AA010A/25LC010A

2.7 Data Protection

The following protection has been implemented to

prevent inadvertent writes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

•CS

must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

2.8 Power-On State

The 25XX010A powers on in the following state:

• The device is in low-power Standby mode

(CS =1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter active state

TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX

(pin 3)

WEL

(SR bit 1) Protected Blocks Unprotected Blocks Status Register

0 (low) xProtected Protected Protected

1 (high) 0Protected Protected Protected

1 (high) 1Protected Writable Writable

x = don’t care

25AA010A/25LC010A

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in progress will be completed, regardless of

the CS input signal. If CS is brought high during a

program cycle, the device will go into Standby mode as

soon as the programming cycle is complete. When the

device is deselected, SO goes to the high-impedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low level on CS is required prior to any sequence

being initiated.

3.2 Serial Output (SO)

The SO pin is used to transfer data out of the

25XX010A. During a read cycle, data is shifted out on

this pin after the falling edge of the serial clock.

3.3 Write-Protect (WP)

The WP pin is a hardware write-protect input pin.

When it is low, all writes to the array or STATUS reg-

ister are disabled, but any other operations function

normally. When WP is high, all functions, including

nonvolatile writes operate normally. At any time, when

WP is low, the write enable Reset latch will be reset

and programming will be inhibited. However, if a write

cycle is already in progress, WP going low will not

change or disable the write cycle. See Table 2-4 for

the Write-Protect Functionality Matrix.

3.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

3.5 Serial Clock (SCK)

The SCK is used to synchronize the communication

between a master and the 25XX010A. Instructions,

addresses or data present on the SI pin are latched on

the rising edge of the clock input, while data on the SO

pin is updated after the falling edge of the clock input.

3.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the

25XX010A while in the middle of a serial sequence

without having to retransmit the entire sequence again.

It must be held high any time this function is not being

used. Once the device is selected and a serial

sequence is underway, the HOLD pin may be pulled

low to pause further serial communication without

resetting the serial sequence. The HOLD pin must be

brought low while SCK is low, otherwise the HOLD

function will not be invoked until the next SCK high-to-

low transition. The 25XX010A must remain selected

during this sequence. The SI, SCK and SO pins are in

a high-impedance state during the time the device is

paused and transitions on these pins will be ignored. To

resume serial communication, HOLD must be brought

high while the SCK pin is low, otherwise serial

communication will not resume. Lowering the HOLD

line at any time will tri-state the SO line.

Name

PDIP, SOIC,

MSOP,

TSSOP,

DFN

Rotated

TSSOP

SOT-

23 Function

CS 1 3 5 Chip Select Input

SO 2 4 4 Serial Data Output

WP 3 5 — Write-Protect Pin

VSS 4 6 2 Ground

SI 5 7 3 Serial Data Input

SCK 6 8 1 Serial Clock Input

HOLD 7 1 — Hold Input

VCC 8 2 6 Supply Voltage

25AA010A/25LC010A

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

T/XXXNNN

XXXXXXXX

YYWW

8-Lead PDIP

8-Lead SOIC

XXXXYYWW

XXXXXXXT

NNN

XXXX

TYWW

8-Lead TSSOP

NNN

I/P 1L7

25AA010A

0627

Example:

SN 0627

25AA01AI

1L7

5A1A

I627

Example:

1st Line Marking Codes

25AA010A 5A1A

8-Lead MSOP (150 mil) Example:

XXXXXT

YWWNNN

5L1AI

6271L7

25LC010A

A1AX

5L1A L1AX

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Part Number TSSOP

Standard Rotated

MSOP SOT-23 DFN

5A1AT

5L1AT

12NN

15NN 16NN

401

404 405

——

I Temp.E Temp.I Te mp . E Te mp .

Note: T = Temperature grade (I, E) NN = Alphanumeric traceability code

25AA010A/25LC010A

Package Marking Information (continued)

6-Lead SOT-23

XXNN

Example:

12L7

XXX

8-Lead 2X3 DFN

YWW

Example:

401

627

25AA010A/25LC010A

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 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV ,1&+(6

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

7RSWR6HDWLQJ3ODQH $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

%DVHWR6HDWLQJ3ODQH $  ± ±

6KRXOGHUWR6KRXOGHU:LGWK (   

0ROGHG3DFNDJH:LGWK (   

2YHUDOO/HQJWK '   

7LSWR6HDWLQJ3ODQH /   

/HDG7KLFNQHVV F   

8SSHU/HDG:LGWK E   

/RZHU/HDG:LGWK E   

2YHUDOO5RZ6SDFLQJ H% ± ± 

NOTE 1

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

25AA010A/25LC010A

/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 6LJQLILFDQW&KDUDFWHULVWLF

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $  ± ±

6WDQGRII$  ± 

2YHUDOO:LGWK ( %6&

0ROGHG3DFNDJH:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

&KDPIHURSWLRQDO K  ± 

)RRW/HQJWK /  ± 

)RRWSULQW / 5()

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

0ROG'UDIW$QJOH7RS  ± 

0ROG'UDIW$QJOH%RWWRP  ± 

NOTE 1

12 3

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

25AA010A/25LC010A

/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

25AA010A/25LC010A

/HDG3ODVWLF7KLQ6KULQN6PDOO2XWOLQH67±PP%RG\>76623@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

6WDQGRII $  ± 

2YHUDOO:LGWK ( %6&

0ROGHG3DFNDJH:LGWK (   

0ROGHG3DFNDJH/HQJWK '   

)RRW/HQJWK /   

)RRWSULQW / 5()

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

NOTE 1

L1 L

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

25AA010A/25LC010A

/HDG3ODVWLF0LFUR6PDOO2XWOLQH3DFNDJH06>0623@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

6WDQGRII $  ± 

2YHUDOO:LGWK ( %6&

0ROGHG3DFNDJH:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

)RRW/HQJWK /   

)RRWSULQW / 5()

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

NOTE 1

L1 L

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

25AA010A/25LC010A

/HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0&±[[PP%RG\>')1@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 3DFNDJHPD\KDYHRQHRUPRUHH[SRVHGWLHEDUVDWHQGV

 3DFNDJHLVVDZVLQJXODWHG

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $   

6WDQGRII $   

&RQWDFW7KLFNQHVV $ 5()

2YHUDOO/HQJWK ' %6&

2YHUDOO:LGWK ( %6&

([SRVHG3DG/HQJWK '  ± 

([SRVHG3DG:LGWK (  ± 

&RQWDFW:LGWK E   

&RQWDFW/HQJWK /   

&RQWDFWWR([SRVHG3DG .  ± ±

NOTE 1

EXPOSED PAD

NOTE 1

A3 A1

NOTE 2

BOTTOM VIEW

TOP VIEW

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

25AA010A/25LC010A

/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU27>627@

1RWHV

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2XWVLGH/HDG3LWFK H %6&

2YHUDOO+HLJKW $  ± 

0ROGHG3DFNDJH7KLFNQHVV $  ± 

6WDQGRII $  ± 

2YHUDOO:LGWK (  ± 

0ROGHG3DFNDJH:LGWK (  ± 

2YHUDOO/HQJWK '  ± 

)RRW/HQJWK /  ± 

)RRWSULQW /  ± 

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

PIN1IDBY

LASER MARK

123

A2 c

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

25AA010A/25LC010A

APPENDIX A: REVISION HISTORY

Revision B

Corrections to Section 1.0, Electrical Characteristics.

Revision C

Added Packages SOT-23, DFN and X-rotated TSSOP;

Revised AC Char., Params. 9, 10; Revised Package

Legend.

Revision D

Revised Pb-free in Features section; Replaced

Package Drawings; Revised Product ID System.

25AA010A/25LC010A

NOTES:

25AA010A/25LC010A

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical support is available through the web site

at: http://support.microchip.com

25AA010A/25LC010A

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response

Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21832D25AA010A/25LC010A

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

25AA010A/25LC010A

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTape & Reel

Device

Device: 25AA010A

25LC010A

1k-Bit, 1.8V, 16 Byte Page, SPI Serial EEPROM

1k-Bit, 2.5V, 16 Byte Page, SPI Serial EEPROM

Tape & Reel: Blank =

Standard packaging

Tape & Reel

Temperature

Range:

-40°C to+85°C

-40°C to+125°C

Package: MS =

SN =

ST =

MC =

OT =

Plastic MSOP (Micro Small Outline), 8-lead

Plastic DIP (300 mil body), 8-lead

Plastic SOIC (3.90 mm body), 8-lead

TSSOP, 8-lead

2x3 DFN, 8-lead

SOT-23, 6-lead (Tape and Reel only)

Examples:

a) 25AA010A-I/MS = 1k-bit, 16-byte page, 1.8V

Serial EEPROM, Industrial temp., MSOP

package

b) 25AA010AT-I/SN = 1k-bit, 16-byte page, 1.8V

Serial EEPROM, Industrial temp., Tape & Reel,

SOIC package

c) 25LC010AT-I/SN = 1k-bit, 16-byte page, 2.5V

Serial EEPROM, Industrial temp., Tape & Reel,

SOIC package

d) 25LC010AT-I/ST = 1k-bit, 16-byte page, 2.5V

Serial EEPROM, Industrial temp., Tape & Reel,

TSSOP package

e) 25LC010AT-E/SN = 1k-bit, 16-byte page, 2.5V

serial EEPROM, Extended temp., Tape & Reel,

SOIC Package

–X

Temperature

25AA010A/25LC010A

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The

Embedded Control Solutions Company are registered

trademarks of Microchip Technology Incorporated in the

U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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09/10/07