S i 5 3 0 / 5 31 REVISION D C R Y S TA L O S C I L L A T O R (XO) (10 M H Z T O 1.4 G H Z ) Features Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz 3rd generation DSPLL(R) with superior jitter performance 3x better frequency stability than SAW-based oscillators Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant Si5602 Ordering Information: Applications See page 7. SONET/SDH Networking SD/HD video Test and measurement Clock and data recovery FPGA/ASIC clock generation Pin Assignments: See page 6. Description The Si530/531 XO utilizes Silicon Laboratories' advanced DSPLL(R) circuitry to provide a low jitter clock at high frequencies. The Si530/531 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si530/531 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si530/531 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Functional Block Diagram V DD CLK- CLK+ (Top View) NC 1 6 VDD OE 2 5 CLK- GND 3 4 CLK+ Si530 (LVDS/LVPECL/CML) OE 1 6 VDD NC 2 5 NC GND 3 4 CLK Si530 (CMOS) Fixed Frequency XO Any-rate 10-1400 MHz DSPLL(R) Clock Synthesis OE 1 6 VDD NC 2 5 CLK- GND 3 4 CLK+ Si531 (LVDS/LVPECL/CML) OE Rev. 1.1 6/07 GND Copyright (c) 2007 by Silicon Laboratories Si530/531 Si530/531 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Supply Current Symbol Test Condition Min Typ Max VDD 3.3 V option 2.97 3.3 3.63 2.5 V option 2.25 2.5 2.75 1.8 V option 1.71 1.8 1.89 Output enabled LVPECL CML LVDS CMOS -- -- -- -- 111 99 90 81 121 108 98 88 Tristate mode -- 60 75 VIH 0.75 x VDD -- -- VIL -- -- 0.5 -40 -- 85 IDD Output Enable (OE)2 Operating Temperature Range TA Units V mA V C Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details. 2. OE pin includes a 17 k pullup resistor to VDD. Table 2. CLK Output Frequency Characteristics Parameter Nominal Frequency1,2 Initial Accuracy Symbol Test Condition Min Typ Max fO LVPECL/LVDS/CML 10 -- 945 CMOS 10 -- 160 Measured at +25 C at time of shipping -- 1.5 -- ppm -7 -20 -50 -- -- -- +7 +20 +50 ppm Frequency drift over first year -- -- 3 ppm Frequency drift over 15 year life -- -- 10 ppm fi Temperature Stability1,3 Aging fa Units MHz Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. 2 Rev. 1.1 Si530/531 Table 2. CLK Output Frequency Characteristics (Continued) Parameter Symbol Total Stability Powerup Time4 Test Condition Min Typ Max Units Temp stability = 7 ppm -- -- 20 ppm Temp stability = 20 ppm -- -- 31.5 ppm Temp stability = 50 ppm -- -- 61.5 ppm -- -- 10 ms tOSC Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. Table 3. CLK Output Levels and Symmetry Parameter LVPECL Output Option Symbol Test Condition Min Typ Max Units VO mid-level VDD - 1.42 -- VDD - 1.25 V VOD swing (diff) 1.1 -- 1.9 VPP VSE swing (single-ended) 0.55 -- 0.95 VPP VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP VO mid-level -- VDD - 0.75 -- V VOD swing (diff) 0.70 0.95 1.20 VPP VOH IOH = 32 mA 0.8 x VDD -- VDD VOL IOL = 32 mA -- -- 0.4 tR, tF LVPECL/LVDS/CML -- -- 350 ps CMOS with CL = 15 pF -- 1 -- ns 45 -- 55 % 1 LVDS Output Option2 CML Output Option2 CMOS Output Option3 Rise/Fall time (20/80%) Symmetry (duty cycle) SYM LVPECL: LVDS: CMOS: VDD - 1.3 V (diff) 1.25 V (diff) VDD/2 V Notes: 1. 50 to VDD - 2.0 V. 2. Rterm = 100 (differential). 3. CL = 15 pF Rev. 1.1 3 Si530/531 Table 4. CLK Output Phase Jitter Parameter Symbol Test Condition Min Typ Max Units Phase Jitter (RMS)* for FOUT > 500 MHz J 12 kHz to 20 MHz (OC-48) -- 0.25 0.40 ps 50 kHz to 80 MHz (OC-192) -- 0.26 0.37 Phase Jitter (RMS)* for FOUT of 125 to 500 MHz J 12 kHz to 20 MHz (OC-48) -- 0.36 0.50 50 kHz to 20 MHz (OC-192) -- 0.34 0.42 ps *Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information. Table 5. CLK Output Period Jitter Parameter Period Jitter* Symbol Test Condition Min Typ Max Units JPER RMS -- 2 -- ps Peak-to-Peak -- 14 -- *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. Table 6. CLK Output Phase Noise (Typical) Offset Frequency (f) 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 4 120.00 MHz 156.25 MHz 622.08 MHz LVDS LVPECL LVPECL -112 -122 -132 -137 -144 -150 n/a -105 -122 -128 -135 -144 -147 n/a -97 -107 -116 -121 -134 -146 -148 Rev. 1.1 Units dBc/Hz Si530/531 Table 7. Absolute Maximum Ratings1 Parameter Symbol Rating Units TAMAX 85 C VDD -0.5 to +3.8 Volts Input Voltage (any input pin) VI -0.5 to VDD + 0.3 Volts Storage Temperature TS -55 to +125 C ESD 2500 Volts TPEAK 260 C tP 20-40 seconds Maximum Operating Temperature Supply Voltage ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile)2 Soldering Temperature Time @ TPEAK (Pb-free profile)2 Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. Table 8. Environmental Compliance The Si530/531 meets the following qualification test requirements. Parameter Conditions/Test Method Mechanical Shock MIL-STD-883F, Method 2002.3 B Mechanical Vibration MIL-STD-883F, Method 2007.3 A Solderability MIL-STD-883F, Method 203.8 Gross & Fine Leak MIL-STD-883F, Method 1014.7 Resistance to Solvents MIL-STD-883F, Method 2016 Rev. 1.1 5 Si530/531 2. Pin Descriptions (Top View) NC 1 6 VDD OE 1 6 VDD OE 1 6 VDD OE 2 5 CLK- NC 2 5 NC NC 2 5 CLK- GND 3 4 CLK+ GND 3 4 CLK GND 3 4 CLK+ Si530 Si530 Si531 LVDS/LVPECL/CML CMOS LVDS/LVPECL/CML Table 9. Pinout for Si530 Series Pin Symbol LVDS/LVPECL/CML Function CMOS Function 1 OE (CMOS only)* No connection Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 2 OE (LVPECL,LVDS, CML)* Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled No connection 3 GND Electrical and Case Ground Electrical and Case Ground 4 CLK+ Oscillator Output Oscillator Output 5 CLK- Complementary Output No connection 6 VDD Power Supply Voltage Power Supply Voltage *Note: OE includes a 17 k pullup resistor to VDD. Table 10. Pinout for Si531 Series Pin Symbol LVDS/LVPECL/CML Function 1 OE (LVPECL, LVDS, CML)* Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 2 No connection No connection 3 GND Electrical and Case Ground 4 CLK+ Oscillator Output 5 CLK- Complementary output 6 VDD Power Supply Voltage *Note: OE includes a 17 k pullup resistor to VDD. 6 Rev. 1.1 Si530/531 3. Ordering Information The Si530/531 XO supports a variety of options including frequency, temperature stability, output format, and VDD. Specific device configurations are programmed into the Si530/531 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si530 and Si531 XO series are supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm package. The Si531 Series supports an alternate OE pinout (pin #1) for the LVPECL, LVDS, and CML output formats. See Tables 9 and 10 for the pinout differences between the Si530 and Si531 series. 53x X X XXXMXXX D G R Tape & Reel Packaging Blank = Trays 530 or 531 XO Product Family Operating Temp Range (C) G -40 to +85C Part Revision Letter 1st Option Code A B C D E F G H J K M N P Q R S T U V W VDD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format Output Enable Polarity LVPECL High LVDS High CMOS High CML High LVPECL High LVDS High CMOS High CML High CMOS High CML High LVPECL Low LVDS Low CMOS Low CML Low LVPECL Low LVDS Low CMOS Low CML Low CMOS Low CML Low Frequency (e.g., 622M080 is 622.080 MHz) Available frequency range is 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. The position of "M" shifts to denote higher or lower frequencies. If the frequency of interest requires greater than 6 digit resolution, a six digit code will be assigned for the specific frequency. 2nd Option Code Code Temperature Stability (ppm, max, ) A 50 B 20 C 7 Total Stablility (ppm, max, ) 61.5 31.5 20 Note: CMOS available to 160 MHz. Example P/N: 530AB622M080DGR is a 5 x 7 XO in a 6 pad package. The frequency is 622.080 MHz, with a 3.3 V supply, LVPECL output, and Output Enable active high polarity. Temperature stability is specifed as 20 ppm. The part is specified for -40 to +85 C ambient temperature range operation and is shipped in tape and reel format. Figure 1. Part Number Convention Rev. 1.1 7 Si530/531 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si530/531. Table 11 lists the values for the dimensions shown in the illustration. Figure 2. Si530/531 Outline Diagram Table 11. Package Diagram Dimensions (mm) Dimension Min Nom Max A 1.45 1.65 1.85 b 1.2 1.4 1.6 c 0.60 TYP. D 7.00 BSC. D1 8 6.10 6.2 e 2.54 BSC. E 5.00 BSC. 6.30 E1 4.30 4.40 4.50 L 1.07 1.27 1.47 S 1.815 BSC. R 0.7 REF. aaa -- -- 0.15 bbb -- -- 0.15 ccc -- -- 0.10 ddd -- -- 0.10 Rev. 1.1 Si530/531 5. Si530/Si531 Mark Specification Figure 3 illustrates the mark specification for the Si530/Si531. Table 12 lists the line information. 6 4 5 SiLabs 123 1234567890 R T T T T Y WW+ 1 2 3 Figure 3. Mark Specification Table 12. Si53x Top Mark Description Line Position 1 1-10 "SiLabs"+ Part Family Number, 5xx (First 3 characters in part number) 2 1-10 Si530, Si531: Option1 + Option2 + Freq(7) + Temp Si532, Si533, Si534, Si530/Si531 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp 3 Description Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3-6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7) Position 8-9 Calendar Work Week number (1-53), to be assigned by assembly site Position 10 "+" to indicate Pb-Free and RoHS-compliant Rev. 1.1 9 Si530/531 6. 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si530/531. Table 13 lists the values for the dimensions shown in the illustration. Figure 4. Si530/531 PCB Land Pattern Table 13. PCB Land Pattern Dimensions (mm) Dimension Min Max D2 5.08 REF e 2.54 BSC E2 4.15 REF GD 0.84 -- GE 2.00 -- VD 8.20 REF VE 7.30 REF X 1.70 TYP Y 2.15 REF ZD -- 6.78 ZE -- 6.30 Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). 10 Rev. 1.1 Si530/531 DOCUMENT CHANGE LIST Revision 0.4 to Revision 0.5 Updated Table 1, "Recommended Operating Conditions," on page 2. Added maximum supply current specifications. Specified relationship between temperature at startup and operation temperature. Updated Table 4, "CLK Output Phase Jitter," on page 4 to include maximum rms jitter generation specifications and updated typical rms jitter specifications. Added Table 6, "CLK Output Phase Noise (Typical)," on page 4. Added Output Enable active polarity as an option in Figure 1, "Part Number Convention," on page 7. Revision 0.5 to Revision 1.0 Updated Note 3 in Table 1, "Recommended Operating Conditions," on page 2. Updated Figure 1, "Part Number Convention," on page 7. Revision 1.0 to Revision 1.1 Updated Table 1, "Recommended Operating Conditions," on page 2. Device maintains stable operation over -40 to +85 C operating temperature range. Supply current specifications updated for revision D. Updated Table 2, "CLK Output Frequency Characteristics," on page 2. Added specification for 20 ppm lifetime stability (7 ppm temperature stability) XO. Updated Table 3, "CLK Output Levels and Symmetry," on page 3. Updated LVDS differential peak-peak swing specifications. Updated Table 4, "CLK Output Phase Jitter," on page 4. Updated Table 5, "CLK Output Period Jitter," on page 4. Revised period jitter specifications. Updated Table 7, "Absolute Maximum Ratings1," on page 5 to reflect the soldering temperature time at 260 C is 20-40 sec per JEDEC J-STD-020C. Updated 3. "Ordering Information" on page 7. Changed ordering instructions to revision D. Added 5. "Si530/Si531 Mark Specification" on page 9. Rev. 1.1 11 Si530/531 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 12 Rev. 1.1