DP83849I DP83849I PHYTER DUAL Industrial Temperature with Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver Literature Number: SNOSAX1D DP83849I PHYTER(R) DUAL Industrial Temperature with Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver General Description Features The number of applications requiring Ethernet Connectivity continues to expand. Along with this increased market demand is a change in application requirements. Where single channel Ethernet used to be sufficient, many applications such as wireless remote base stations and industrial networking now require DUAL Port functionality for redundancy or system management. The DP83849I is a highly reliable, feature rich device perfectly suited for industrial applications enabling Ethernet on the factory floor. The DP83849I features two fully independent 10/100 ports for multi-port applications. NATIONAL's unique port switching capability also allows the two ports to be configured to provide fully integrated range extension, media conversion, hardware based failover and port monitoring. The DP83849I provides optimum flexibility in MPU selection by supporting both MII and RMII interfaces. In addition this device includes a powerful new diagnostics tool to ensure initial network operation and maintenance. In addition to the TDR scheme, commonly used for detecting faults during installation, NATIONAL's innovative cable diagnostics provides for real time continuous monitoring of the link quality. This allows the system designer to implement a fault prediction mechanism to detect and warn of changing or deteriorating link conditions. With the DP83849I, National Semiconductor continues to build on its Ethernet expertise and leadership position by providing a powerful combination of features and flexibility, easing Ethernet implementation for the system designer. * * * * * * * * * * * * * * * * * * * * * * * * Low-power 3.3V, 0.18m CMOS technology Low power consumption <600mW Typical 3.3V MAC Interface Auto-MDIX for 10/100 Mb/s Energy Detection Mode Flexible MII Port Assignment Dynamic Integrity Utility Dynamic Link Quality Monitoring TDR based Cable Diagnostic and Cable Length Detection Optimized Latency for Real Time Ethernet Operation Reference Clock out RMII Rev. 1.2 Interface (configurable) SNI Interface (configurable) MII Serial Management Interface (MDC and MDIO) IEEE 802.3u MII IEEE 802.3u Auto-Negotiation and Parallel Detection IEEE 802.3u ENDEC, 10BASE-T transceivers and filters IEEE 802.3u PCS, 100BASE-TX transceivers and filters IEEE 1149.1 JTAG Integrated ANSI X3.263 compliant TP-PMD physical sub-layer with adaptive equalization and Baseline Wander compensation Programmable LED support for Link, 10 /100 Mb/s Mode, Activity, Duplex and Collision Detect Single register access for complete PHY status 10/100 Mb/s packet BIST (Built in Self Test) 80-pin TQFP package (12mm x 12mm) Applications * * * * * Medical Instrumentation Factory Automation Motor & Motion Control Wireless Remote Base Station General Embedded Applications MAC Magnetics DP83849I MPU/CPU Port A MII/RMII/SNI 25 MHz Clock Source RJ-45 MII/RMII/SNI RJ-45 Port B Magnetics MAC System Diagram 10BASE-T or 100BASE-TX 10BASE-T or 100BASE-TX Status LEDs Typical Application PHYTER is a registered trademark of National Semiconductor Corporation (c) 2008 National Semiconductor Corporation www.national.com 1 DP83849I PHYTER(R) DUAL Industrial Temperature with Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver May 2008 DP83849I MII MANAGEMENT INTERFACE PORT A MII/RMII/SNI TX RX MDC PORT B MII/RMII/SNI TX MDIO RX MANAGEMENT INTERFACE 10/100 PHY CORE 10/100 PHY CORE PORT A PORT B BOUNDARY SCAN LED DRIVERS LEDS TPTD TPRD JTAG LED DRIVERS LEDS TPTD TPRD Figure 1. DP83849I Functional Block Diagram www.national.com 2 1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.2 MAC Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.5 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.6 Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.7 Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.8 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.9 Special Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.10 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.11 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 Auto-Negotiation Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Negotiation Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Negotiation Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Auto-Negotiation via Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Negotiation Complete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 19 19 19 19 2.2 Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.3 PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.3.1 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.4.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.2 LED Direct Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.5 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.6 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.7 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.0 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.1.1 Nibble-wide MII Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.2 Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.3 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 3.3 3.4 3.5 Reduced MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 10 Mb Serial Network Interface (SNI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Single Clock MII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Flexible MII Port Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 RX MII Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX MII Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Flexible MII Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Strapped Extender Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 28 28 29 29 3.6 802.3u MII Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.6.1 3.6.2 3.6.3 3.6.4 Serial Management Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Management Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Management Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simultaneous Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 31 4.0 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4.1.1 4.1.2 4.1.3 4.1.4 Code-group Encoding and Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary to MLT-3 Convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 34 34 4.2 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3 www.national.com DP83849I Table of Contents DP83849I 4.2.1 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2.1 Digital Adaptive Equalization and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2.2 Base Line Wander Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.7 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.8 Code-group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.9 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.10 100BASE-TX Link Integrity Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.11 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 36 37 37 37 37 37 38 38 38 38 38 4.3 10BASE-T TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.3.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Collision Detection and SQE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 Normal Link Pulse Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 Automatic Link Polarity Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 38 40 40 40 40 40 40 40 40 5.0 Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 5.2 5.3 5.4 5.5 TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Clock In (X1) Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Power Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Power Down/Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.5.1 Power Down Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5.2 Interrupt Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6 Energy Detect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.7 Link Diagnostic Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.7.1 Linked Cable Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1.1 Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1.2 Cable Swap Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1.3 100MB Cable Length Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1.4 Frequency Offset Relative to Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1.5 Cable Signal Quality Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Link Quality Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2.1 Link Quality Monitor Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2.2 Checking Current Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2.3 Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 TDR Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3.1 TDR Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3.2 TDR Pulse Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3.3 TDR Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3.4 TDR Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 44 44 45 45 45 45 45 45 45 46 46 46 46 47 6.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.2 Full Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.3 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 7.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 www.national.com Basic Mode Control Register (BMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Mode Status Register (BMSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY Identifier Register #1 (PHYIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY Identifier Register #2 (PHYIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Negotiation Advertisement Register (ANAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 54 56 57 57 57 59 60 61 62 63 65 65 66 7.2 Extended Registers - Page 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.2.1 False Carrier Sense Counter Register (FCSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 RMII and Bypass Register (RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.5 LED Direct Control Register (LEDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.6 PHY Control Register (PHYCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.7 10 Base-T Status/Control Register (10BTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.8 CD Test and BIST Extensions Register (CDCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.9 Phy Control Register 2 (PHYCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.10 Energy Detect Control (EDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 67 67 69 71 72 73 75 75 76 7.3 Link Diagnostics Registers - Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 7.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h . . . . . . . . . . . . . . . . . 7.3.2 100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h . . . . . . . . . 7.3.3 TDR Control Register (TDR_CTRL), Page 2, address 16h . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.4 TDR Window Register (TDR_WIN), Page 2, address 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.5 TDR Peak Register (TDR_PEAK), Page 2, address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.6 TDR Threshold Register (TDR_THR), Page 2, address 19h . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.7 Variance Control Register (VAR_CTRL), Page 2, address 1Ah . . . . . . . . . . . . . . . . . . . . . . 7.3.8 Variance Data Register (VAR_DATA), Page 2, address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . 7.3.9 Link Quality Monitor Register (LQMR), Page 2, address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . 7.3.10 Link Quality Data Register (LQDR), Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 77 78 79 79 79 80 80 81 82 8.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.1 DC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 8.2 AC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 8.2.1 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.2.3 MII Serial Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.2.4 100 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.2.5 100 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.2.6 100BASE-TX MII Transmit Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.2.7 100BASE-TX MII Transmit Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.2.9 100BASE-TX MII Receive Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.2.10 100BASE-TX MII Receive Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.2.13 10 Mb/s Serial Mode Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.2.14 10 Mb/s Serial Mode Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.2.15 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.2.16 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.2.17 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.2.18 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.2.19 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.2.20 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.2.21 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.2.23 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.2.24 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.2.25 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.2.26 RMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.2.27 RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.2.28 Single Clock MII (SCMII) Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5 www.national.com DP83849I 7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) . . . . . . . . . . . . . . . . 7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) . . . . . . . . . . . . . . . . . 7.1.8 Auto-Negotiate Expansion Register (ANER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.10 PHY Status Register (PHYSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.11 MII Interrupt Control Register (MICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.12 MII Interrupt Status and Misc. Control Register (MISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.13 Page Select Register (PAGESEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DP83849I 8.2.29 8.2.30 8.2.31 8.2.32 Single Clock MII (SCMII) Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK2MAC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Mb/s X1 to TX_CLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 104 104 105 9.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 www.national.com 6 Figure 1. DP83849I Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4. MII Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 5. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 6. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 9. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . . 36 Figure 10. 100BASE-TX BLW Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 11. 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. 10/100 Mb/s Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 13. Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 14. Power Feeback Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 www.national.com DP83849I List of Figures DP83849I List of Table Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 2. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 3. LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 4. Supported packet sizes at +/-50ppm frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 5. Supported SCMII packet sizes at +/-50ppm frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 6. RX MII Port Mapping Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 7. RX MII Port Mapping Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 8. TX MII Port Mapping Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 9. TX MII Port Mapping Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 10. Common Flexible MII Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 11. Common Strapped Extender Mode Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 12. Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 13. 4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 14. 25 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Table 15. 50 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Table 16. 25 MHz Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Table 17. Link Quality Monitor Parameter Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 18. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 19. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 20. Basic Mode Control Register (BMCR), address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 21. Basic Mode Status Register (BMSR), address 01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Table 22. PHY Identifier Register #1 (PHYIDR1), address 02h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 23. PHY Identifier Register #2 (PHYIDR2), address 03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 24. Negotiation Advertisement Register (ANAR), address 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 25. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 05h . . . . . . . . .59 Table 26. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 05h . . . . . . . . . .60 Table 27. Auto-Negotiate Expansion Register (ANER), address 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Table 28. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 07h . . . . . . . . . . . . . . . . . . . .62 Table 29. PHY Status Register (PHYSTS), address 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Table 30. MII Interrupt Control Register (MICR), address 11h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h . . . . . . . . . . . . . . . . . . . . . . .65 Table 32. Page Select Register (PAGESEL), address 13h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Table 33. False Carrier Sense Counter Register (FCSCR), address 14h . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Table 34. Receiver Error Counter Register (RECR), address 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Table 35. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h . . . . . . . . . . . . . . . . . . . . .67 Table 36. RMII and Bypass Register (RBR), addresses 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Table 37. LED Direct Control Register (LEDCR), address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 38. PHY Control Register (PHYCR), address 19h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 40. CD Test and BIST Extensions Register (CDCTRL1), address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . . .75 Table 41. Phy Control Register 2 (PHYCR2), address 1Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Table 42. Energy Detect Control (EDCR), address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Table 43. 100Mb Length Detect Register (LEN100_DET), address 14h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 44. 100Mb Frequency Offset Indication Register (FREQ100), address 15h . . . . . . . . . . . . . . . . . . . . . .77 Table 45. TDR Control Register (TDR_CTRL), address 16h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 46. TDR Window Register (TDR_WIN), address 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Table 47. TDR Peak Register (TDR_PEAK), address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Table 48. TDR Threshold Register (TDR_THR), address 19h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Table 49. Variance Control Register (VAR_CTRL), address 1Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table 50. Variance Data Register (VAR_DATA), address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table 51. Link Quality Monitor Register (LQMR), address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 52. Link Quality Data Register (LQDR), address 1Eh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 www.national.com 8 11 12 13 14 15 16 17 18 19 20 TX_CLK_A TX_EN_A TXD0_A TXD1_A TXD2_A TXD3_A/SNI_MODE_A PWRDOWN_INT_A LED_LINK_A/AN0_A LED_SPEED_A/AN1_A 10 IOVDD1 IOGND1 9 6 COREGND1 RXD3_A/ED_EN_A 5 RXD1_A/PHYAD2 8 4 RXD0_A/PHYAD1 7 3 COL_A RXD2_A/CLK2MAC_DIS 2 PFBIN1 1 RX_ER_A/MDIX_EN_A o CRS_A/CRS_DV_A/LED_CFG_A RX_ER_B/MDIX_EN_B COL_B RXD0_B/PHYAD3 RXD1_B/PHYAD4 RXD2_B/EXTENDER_EN COREGND2 PFBIN4 RXD3_B/ED_EN_B IOGND2 IOVDD2 TX_CLK_B TX_EN_B TXD0_B TXD1_B TXD2_B TXD3_B/SNI_MODE_B PWRDOWN_INT_B LED_LINK_B/AN0_B LED_SPEED_B/AN1_B LED_ACT/LED_COL/AN_EN_B 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DP83849I Pin Layout CRS_B/CRS_DV_B/LED_CFG_B 61 40 ANAGND4 RX_DV_B/MII_MODE_B 62 39 TPRDM_B RX_CLK_B 63 38 TPRDP_B IOGND3 64 37 CDGND2 IOVDD3 65 36 TPTDM_B MDIO 66 35 TPTDP_B MDC 67 34 PFBIN3 CLK2MAC 68 33 ANAGND3 X2 69 32 RBIAS X1 70 31 PFBOUT RESET_N 71 30 ANA33VDD TCK 72 29 ANAGND2 TDO 73 28 PFBIN2 TMS 74 27 TPTDP_A TRSTN 75 26 TPTDM_A TDI 76 25 CDGND1 IOGND4 77 24 TPRDP_A IOVDD4 78 23 TPRDM_A RX_CLK_A 79 22 ANAGND1 RX_DV_A/MII_MODE_A 80 21 LED_ACT/LED_COL/AN_EN_A DP83849IVS Top View NS Package Number VHB80A 9 www.national.com DP83849I 1.0 Pin Descriptions The DP83849I pins are classified into the following interface categories (each interface is described in the sections that follow): Note: Strapping pin option. Please see Section 1.7 for strap definitions. -- -- -- -- -- -- -- -- -- -- Type: I Type: O Type: I/O Type OD Type: PD,PU Type: S Serial Management Interface MAC Data Interface Clock Interface LED Interface JTAG Interface Reset and Power Down Strap Options 10/100 Mb/s PMD Interface Special Connect Pins Power and Ground pins All DP83849I signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin. Input Output Input/Output Open Drain Internal Pulldown/Pullup Strapping Pin (All strap pins have weak internal pull-ups or pull-downs. If the default strap value is to be changed then an external 2.2 k resistor should be used. Please see Section 1.7 for details.) 1.1 Serial Management Interface Type Pin # Description MDC Signal Name I 67 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MDIO I/O 66 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 k pullup resistor. Type Pin # Description O 12 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock. 1.2 MAC Data Interface Signal Name TX_CLK_A TX_CLK_B 50 Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb SNI mode. The MAC should source TX_EN and TXD_0 using this clock. TX_EN_A I TX_EN_B 13 49 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0]. RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0]. SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0. TXD[3:0]_A TXD[3:0]_B I 17,16,15,14 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that 45,46,47,48 accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50 MHz reference clock. SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI mode). www.national.com 10 RX_CLK_A Type Pin # Description O 79 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode. RX_CLK_B 63 Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode. RX_DV_A O RX_DV_B 80 62 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0]. RMII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[1:0]. This signal is not required in RMII mode, since CRS_DV includes the RX_DV signal, but is provided to allow simpler recovery of the Receive data. This pin is not used in SNI mode. RX_ER_A O RX_ER_B 2 60 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode. RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s mode. This pin is also asserted on detection of a False Carrier event. This pin is not required to be used by a MAC in RMII mode, since the Phy is required to corrupt data on a receive error. This pin is not used in SNI mode. RXD[3:0]_A O RXD[3:0]_B 9,8,5,4 MII RECEIVE DATA: Nibble wide receive data signals driven syn53,56,57,58 chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted. RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz. SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode. CRS_A/CRS_DV_A O CRS_B/CRS_DV_B 1 61 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification. SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to frame valid receive data on the RXD_0 signal. COL_A COL_B O 3 59 MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes. While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1s at the end of transmission to indicate heartbeat (SQE test). In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation. RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision. SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s SNI mode. 11 www.national.com DP83849I Signal Name DP83849I 1.3 Clock Interface Signal Name X1 Type Pin # Description I 70 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83849I and must be connected to a 25 MHz 0.005% (+50 ppm) clock source. The DP83849I supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50 MHz 0.005% (+50 ppm) CMOS-level oscillator source. X2 O 69 CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used. CLK2MAC O 68 CLOCK TO MAC: In MII mode, this pin provides a 25 MHz clock output to the system. In RMII mode, this pin provides a 50 MHz clock output to the system. This allows other devices to use the reference clock from the DP83849I without requiring additional clock sources. If the system does not require the CLK2MAC signal, the CLK2MAC output should be disabled via the CLK2MAC disable strap. 1.4 LED Interface The DP83849I supports three configurable LED pins. The LEDs support two operational modes which are selected by the LED mode strap and a third operational mode which Signal Name LED_LINK_A is register configurable. The definitions for the LEDs for each mode are detailed below. Since the LEDs are also used as strap options, the polarity of the LED output is dependent on whether the pin is pulled up or down. Type Pin # Description I/O 19 LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good. LED_LINK_B 43 LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active. LED_SPEED_A I/O LED_SPEED_B LED_ACT/LED_COL_A LED_ACT/LED_COL_B www.national.com 20 42 I/O 21 41 SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in 10 Mb/s. Functionality of this LED is independent of mode selected. ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or Receive. COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be programmed to indicate Full-duplex status instead of Collision. 12 DP83849I 1.5 JTAG Interface Signal Name TCK Type Pin # I, PU 72 Description TEST CLOCK This pin has a weak internal pullup. TDO O 73 TEST OUTPUT TMS I, PU 74 TEST MODE SELECT TRSTN I, PU 75 This pin has a weak internal pullup. TEST RESET Active low test reset. This pin has a weak internal pullup. TDI I, PU 76 TEST DATA INPUT This pin has a weak internal pullup. 1.6 Reset and Power Down Signal Name Type Pin # Description RESET_N I, PU 71 RESET: Active Low input that initializes or re-initializes the DP83849I. Asserting this pin low for at least 1 s will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Register Block section. All strap options are re-initialized as well. PWRDOWN_INT_A I, PU 18 The default function of this pin is POWER DOWN. 44 POWER DOWN: The pin is an active low input in this mode and should be asserted low to put the device in a Power Down mode. PWRDOWN_INT_B INTERRUPT: The pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs. Although the pin has a weak internal pull-up, some applications may require an external pull-up resister. Register access is required for the pin to be used as an interrupt mechanism. See Section 5.5.2 Interrupt Mechanism for more details on the interrupt mechanisms. 1.7 Strap Options The DP83849I uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses. Signal Name A 2.2 k resistor should be used for pull-down or pull-up to change the default strap option. If the default option is required, then there is no need for external pull-up or pull down resistors. Since these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND. Type Pin # Description PHYAD1 (RXD0_A) S, O, PD 4 PHYAD2 (RXD1_A) S, O, PD 5 PHYAD3 (RXD0_B) S, O, PD 58 PHY ADDRESS [4:1]: The DP83849I provides four PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset. Phy Address[0] selects between ports A and B. PHYAD4 (RXD1_B) S, O, PD 57 The DP83849I supports PHY Address strapping for Port A even values 0 (<0000_0>) through 30 (<1111_0>). Port B will be strapped to odd values 1 (<0000_1>) through 31 (<1111_1>). PHYAD[4:1] pins have weak internal pull-down resistors. 13 www.national.com DP83849I Signal Name AN_EN (LED_ACT/LED_COL_A) Type Pin # Description S, O, PU 21 Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins. 20 AN1_A (LED_SPEED_A) 19 AN0_A (LED_LINK_A) 41 AN_EN (LED_ACT/LED_COL_B) 42 43 AN1_B (LED_SPEED_B) AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83849I according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2 k resistors. These pins should NEVER be connected directly to GND or VCC. The value set at this input is latched into the DP83849I at Hardware-Reset. AN0_B (LED_LINK_B) The float/pull-down status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default is 111 since these pins have internal pull-ups. AN_EN AN1 AN0 Forced Mode 0 0 0 10BASE-T, Half-Duplex 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex AN_EN AN1 AN0 Advertised Mode 1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 100BASE-TX, Half/Full-Duplex 1 1 0 10BASE-T Half-Duplex 1 1 1 10BASE-T, Half/Full-Duplex 100BASE-TX, Half-Duplex 100BASE-TX, Half/Full-Duplex MII_MODE_A (RX_DV_A) S, O, PD 80 SNI_MODE_A (TXD3_A) 17 MII_MODE_B (RX_DV_B) 62 SNI_MODE_B (TXD3_B) 45 MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default operation (No pull-ups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII or SNI modes of operation, determined by the status of the SNI_MODE strap. Since the pins include internal pull-downs, the default values are 0. Both MAC Data Interfaces must have their RMII Mode settings the same, i.e. both in RMII mode or both not in RMII mode. The following table details the configurations: MII_MODE LED_CFG_A (CRS_A/CRS_DV_A) LED_CFG_B (CRS_B/CRS_DV_B) S, O, PU 1 61 SNI_MODE MAC Interface Mode 0 X MII Mode 1 0 RMII Mode 1 1 10 Mb SNI Mode LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option. All modes are configurable via register access. See Table 3 on page 21 for LED Mode Selection. www.national.com 14 Type Pin # Description 2 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pull-down will disable AutoMDIX mode. MDIX_EN_A (RX_ER_A) MDIX_EN_B (RX_ER_B) S, O, PU ED_EN_A (RXD3_A) ED_EN_B (RXD3_B) S, O, PD CLK2MAC_DIS (RXD2_A) S, O, PD 8 Clock to MAC Disable: This strapping option disables (floats) the CLK2MAC pin. Default is to enable CLK2MAC output. An external pullup will disable (float) the CLK2MAC pin. If the system does not require the CLK2MAC signal, the CLK2MAC output should be disabled via this strap option. EXTENDER_EN (RXD2_B) S, O, PD 56 Extender Mode Enable: This strapping option enables Extender Mode for both ports. When enabled, the strap will enable Single Clock MII TX and RX modes unless RMII Mode is also strapped. SNI Mode cannot be strapped if Extender Mode is strapped. 60 9 53 Energy Detect ENABLE: Default is to disable Energy Detect mode. This strapping option enables Energy Detect mode for the port. In Energy Detect mode, the device will initially be in a lowpower state until detecting activity on the wire. An external pull-up will enable Energy Detect mode. 15 www.national.com DP83849I Signal Name DP83849I 1.8 10 Mb/s and 100 Mb/s PMD Interface Signal Name Type Pin # I/O 26 10BASE-T or 100BASE-TX Transmit Data TPTDP_A 27 TPTDM_B 36 TPTDP_B 35 In 10BASE-T or 100BASE-TX: Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. TPTDM_A Description In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation. TPRDM_A I/O 23 10BASE-T or 100BASE-TX Receive Data TPRDP_A 24 TPRDM_B 39 TPRDP_B 38 In 10BASE-T or 100BASE-TX: Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling. In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require 3.3V bias for operation. 1.9 Special Connections Signal Name Type Pin # Description RBIAS I 32 Bias Resistor Connection: A 4.87 k 1% resistor should be connected from RBIAS to GND. PFBOUT O 31 Power Feedback Output: Parallel caps, 10 F and 0.1F, should be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 13), PFBIN2 (pin 27), PFBIN3 (pin35), PFBIN4 (pin 49). See Section 5.4 for proper placement pin. PFBIN1 I 7 Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor of 0.1F should be connected close to each pin. PFBIN2 28 PFBIN3 34 PFBIN4 54 Note: Do not supply power to these pins other than from PFBOUT. 1.10 Power Supply Pins Signal Name Pin # Description IOVDD1, IOVDD2, IOVDD3, IOVDD4 11,51,65,78 I/O 3.3V Supply IOGND1, IOGND2, IOGND3, IOGND4 10,52,64,77 I/O Ground COREGND1, COREGND2 6,55 Core Ground CDGND1, CDGND2 25,37 CD Ground ANA33VDD ANAGND1, ANAGND2, ANAGND3, ANAGND4 www.national.com 30 22,29,33,40 Analog 3.3V Supply Analog Ground 16 VHB80A Pin Pin Name # VHB80A Pin Pin Name # 1 CRS_A/CRS_DV_A/LED_CFG_A 2 RX_ER_A/MDIX_EN_A 3 COL_A 4 RXD0_A/PHYAD1 5 RXD1_A/PHYAD2 6 COREGND1 7 PFBIN1 8 RXD2_A/CLK2MAC_DIS 9 RXD3_A/ED_EN_A 10 IOGND1 11 IOVDD1 12 TX_CLK_A 13 TX_EN_A 14 TXD0_A 15 TXD1_A 16 TXD2_A 17 TXD3_A/SNI_MODE_A 18 PWRDOWN_INT_A 19 LED_LINK_A/AN0_A 20 LED_SPEED_A/AN1_A 21 LED_ACT/LED_COL/AN_EN_A 22 ANAGND1 23 TPRDM_A 24 TPRDP_A 25 CDGND1 26 TPTDM_A 27 TPTDP_A 28 PFBIN2 29 ANAGND2 30 ANA33VDD 31 PFBOUT 32 RBIAS 33 ANAGND3 34 PFBIN3 35 TPTDP_B 36 TPTDM_B 37 CDGND2 38 TPRDP_B 39 TPRDM_B 40 ANAGND4 41 LED_ACT/LED_COL/AN_EN_B 42 LED_SPEED_B/AN1_B DP83849I 1.11 Package Pin Assignments 17 43 LED_LINK_B/AN0_B 44 PWRDOWN_INT_B 45 TXD3_B/SNI_MODE_B 46 TXD2_B 47 TXD1_B 48 TXD0_B 49 TX_EN_B 50 TX_CLK_B 51 IOVDD2 52 IOGND2 53 RXD3_B/ED_EN_B 54 PFBIN4 55 COREGND2 56 RXD2_B/EXTENDER_EN 57 RXD1_B/PHYAD4 58 RXD0_B/PHYAD3 59 COL_B 60 RX_ER_B/MDIX_EN_B 61 CRS_B/CRS_DV_B/LED_CFG_B 62 RX_DV_B/MII_MODE_B 63 RX_CLK_B 64 IOGND3 65 IOVDD3 66 MDIO 67 MDC 68 CLK2MAC 69 X2 70 X1 71 RESET_N 72 TCK 73 TDO 74 TMS 75 TRSTN 76 TDI 77 IOGND4 78 IOVDD4 79 RX_CLK_A 80 RX_DV_A/MII_MODE_A www.national.com DP83849I 2.0 Configuration This section includes information on the various configuration options available with the DP83849I. The configuration options described below include: -- -- -- -- -- -- -- Table 1. Auto-Negotiation Modes Media Configuration Auto-Negotiation PHY Address and LEDs Half Duplex vs. Full Duplex Isolate mode Loopback mode BIST 2.1 Auto-Negotiation AN_EN AN1 AN0 0 0 0 10BASE-T, Half-Duplex Forced Mode 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 100BASE-TX, Full-Duplex 0 1 1 AN_EN AN1 AN0 1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 100BASE-TX, Half/Full-Duplex 1 1 0 10BASE-T Half-Duplex Advertised Mo0e 100BASE-TX, Half-Duplex The Auto-Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide the signalling used to communicate Auto-Negotiation abilities between two devices at each end of a link segment. For further detail regarding Auto-Negotiation, refer to Clause 28 of the IEEE 802.3u specification. The DP83849I supports four different Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the highest performance protocol will be selected based on the advertised ability of the Link Partner. The Auto-Negotiation function within the DP83849I can be controlled either by internal register access or by the use of the AN_EN, AN1 and AN0 pins. 1 1 1 10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex 2.1.2 Auto-Negotiation Register Control When Auto-Negotiation is enabled, the DP83849I transmits the abilities programmed into the Auto-Negotiation Advertisement register (ANAR) at address 04h via FLP Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full Duplex modes may be selected. Auto-Negotiation Priority Resolution: The state of AN_EN, AN0 and AN1, upon power-up/reset, determines the state of bits [8:5] of the ANAR register. -- (1) 100BASE-TX Full Duplex (Highest Priority) -- (2) 100BASE-TX Half Duplex -- (3) 10BASE-T Full Duplex -- (4) 10BASE-T Half Duplex (Lowest Priority) The Basic Mode Control Register (BMCR) at address 00h provides control for enabling, disabling, and restarting the Auto-Negotiation process. When Auto-Negotiation is disabled, the Speed Selection bit in the BMCR controls switching between 10 Mb/s or 100 Mb/s operation, and the Duplex Mode bit controls switching between full duplex operation and half duplex operation. The Speed Selection and Duplex Mode bits have no effect on the mode of operation when the Auto-Negotiation Enable bit is set. The Auto-Negotiation function selected at power-up or reset can be changed at any time by writing to the Basic Mode Control Register (BMCR) at address 00h. The Link Speed can be examined through the PHY Status Register (PHYSTS) at address 10h after a Link is achieved. 2.1.1 Auto-Negotiation Pin Control The state of AN_EN, AN0 and AN1 determines whether the DP83849I is forced into a specific mode or Auto-Negotiation will advertise a specific ability (or set of abilities) as given in Table 1. These pins allow configuration options to be selected without requiring internal register access. The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, Auto-Negotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83849I (only the 100BASE-T4 bit is not set since the DP83849I does not support that function). The BMSR also provides status on: -- Whether or not Auto-Negotiation is complete -- Whether or not the Link Partner is advertising that a remote fault has occurred -- Whether or not valid link has been established -- Support for Management Frame Preamble suppression The Auto-Negotiation Advertisement Register (ANAR) indicates the Auto-Negotiation abilities to be advertised by the DP83849I. All available abilities are transmitted by default, but any ability can be suppressed by writing to the ANAR. www.national.com 18 The Auto-Negotiation Link Partner Ability Register (ANLPAR) at address 05h is used to receive the base link code word as well as all next page code words during the negotiation. Furthermore, the ANLPAR will be updated to either 0081h or 0021h for parallel detection to either 100 Mb/s or 10 Mb/s respectively. 2.1.5 Enabling Auto-Negotiation via Software It is important to note that if the DP83849I has been initialized upon power-up as a non-auto-negotiating device (forced technology), and it is then required that Auto-Negotiation or re-Auto-Negotiation be initiated via software, bit 12 (Auto-Negotiation Enable) of the Basic Mode Control Register (BMCR) must first be cleared and then set for any Auto-Negotiation function to take effect. The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER provides status on: 2.1.6 Auto-Negotiation Complete Time -- Whether or not a Parallel Detect Fault has occurred -- Whether or not the Link Partner supports the Next Page function -- Whether or not the DP83849I supports the Next Page function -- Whether or not the current page being exchanged by Auto-Negotiation has been received -- Whether or not the Link Partner supports Auto-Negotiation Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to Auto-Negotiation. Parallel detection and Auto-Negotiation take approximately 2-3 seconds to complete. In addition, Auto-Negotiation with next page should take approximately 2-3 seconds to complete, depending on the number of next pages sent. 2.2 Auto-MDIX When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for transmission and 2.1.3 Auto-Negotiation Parallel Detection reception of data and subsequently selects the appropriate The DP83849I supports the Parallel Detection function as MDI pair for MDI/MDIX operation. The function uses a randefined in the IEEE 802.3u specification. Parallel Detection dom seed to control switching of the crossover circuitry. requires both the 10 Mb/s and 100 Mb/s receivers to moni- This implementation complies with the corresponding IEEE tor the receive signal and report link status to the Auto- 802.3 Auto-Negotiation and Crossover Specifications. Negotiation function. Auto-Negotiation uses this informa- Auto-MDIX is enabled by default and can be configured via tion to configure the correct technology in the event that the strap or via PHYCR (19h) register, bits [15:14]. Link Partner does not support Auto-Negotiation but is Neither Auto-Negotiation nor Auto-MDIX is required to be transmitting link signals that the 100BASE-TX or 10BASEenabled in forcing crossover of the MDI pairs. Forced T PMAs recognize as valid link signals. crossover can be achieved through the FORCE_MDIX bit, If the DP83849I completes Auto-Negotiation as a result of bit 14 of PHYCR (19h) register. Parallel Detection, bits 5 and 7 within the ANLPAR register Note: Auto-MDIX will not work in a forced mode of operawill be set to reflect the mode of operation present in the tion. Link Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field. Software may determine that negotiation completed via Parallel Detection by 2.3 PHY Address reading a zero in the Link Partner Auto-Negotiation Able bit The 4 PHY address inputs pins are shown below. once the Auto-Negotiation Complete bit is set. If configured for parallel detect mode and any condition other than a sinTable 2. PHY Address Mapping gle good link occurs then the parallel detect fault bit will be set. Pin # PHYAD Function RXD Function 2.1.4 Auto-Negotiation Restart 4 PHYAD1 RXD0_A 5 PHYAD2 RXD1_A Once Auto-Negotiation has completed, it may be restarted 58 PHYAD3 RXD0_B at any time by setting bit 9 (Restart Auto-Negotiation) of the 57 PHYAD4 RXD1_B BMCR to one. If the mode configured by a successful AutoNegotiation loses a valid link, then the Auto-Negotiation process will resume and attempt to determine the configu- The DP83849I provides four address strap pins for deterration for the link. This function ensures that a valid config- mining the PHY addresses for ports A and B of the device. The 4 address strap pins provide the upper four bits of the uration is maintained if the cable becomes disconnected. PHY address. The lowest bit of the PHY address is depenA renegotiation request from any entity, such as a manage- dent on the port. Port A has a value of 0 for the PHY ment agent, will cause the DP83849I to halt any transmit address bit 0 while port B has a value of 1. The PHY data and link pulse activity until the break_link_timer address strap input pins are shown in Table 2. expires (~1500 ms). Consequently, the Link Partner will go into link fail and normal Auto-Negotiation resumes. The The PHY address strap information is latched into the DP83849I will resume Auto-Negotiation after the PHYCR register (address 19h, bits [4:0]) at device powerbreak_link_timer has expired by issuing FLP (Fast Link up and hardware reset. The PHY Address pins are shared with the RXD pins. Each DP83849I or port sharing an Pulse) bursts. 19 www.national.com DP83849I Updating the ANAR to suppress an ability is one way for a management agent to change (restrict) the technology that is used. The DP83849I supports PHY Address strapping of Port A to even values 0 (<0000_0>) through 30 (<1111_0>). Port B is strapped to odd values 1 (<0000_1>) through 31 (<1111_1>). Note that Port B address is always 1 greater than Port A address. For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other hardware configuration pins, refer to the Reset summary in Section 6.0. 2.3.1 MII Isolate Mode The DP83849I can be put into MII Isolate mode by writing to bit 10 of the BMCR register. When in the MII isolate mode, the DP83849I does not respond to packet data present at TXD[3:0], TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in Isolate mode, the DP83849I will continue to respond to all management transactions. While in Isolate mode, the PMD output pair will not transmit packet data but will continue to source 100BASE-TX scrambled idles or 10BASE-T normal link pulses. RXD0_A The DP83849I can Auto-Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the DP83849I is in Isolate mode. RXD1_A RXD0_B Refer to Figure 2 for an example of a PHYAD connection to external components. In this example, the PHYAD strapping results in address 00010 (02h) for Port A and address 00011 (03h) for Port B. RXD1_B PHYAD4= 0 PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 2.2k DP83849I MDIO bus in a system must have a unique physical address. VCC Figure 2. PHYAD Strapping Example www.national.com 20 The DP83849I supports three configurable Light Emitting Diode (LED) pins for each port. Several functions can be multiplexed onto the three LEDs using three different modes of operation. The LED operation mode can be selected by writing to the LED_CFG[1:0] register bits in the PHY Control Register (PHYCR) at address 19h, bits [6:5]. In addition, LED_CFG[0] for each port can be set by a strap option on the CRS_A and CRS_B pins. LED_CFG[1] is only controllable through register access and cannot be set by as strap pin. See Table 3 for LED Mode selection. Table 3. LED Mode Select Mode LED_CFG[1] LED_CFG[0] 1 don't care 1 2 3 0 1 0 0 LED_LINK LED_SPEED ON for Good Link ON in 100 Mb/s ON for Activity OFF for No Link OFF in 10 Mb/s OFF for No Activity ON for Good Link ON in 100 Mb/s ON for Collision BLINK for Activity OFF in 10 Mb/s OFF for No Collision ON for Good Link ON in 100 Mb/s ON for Full Duplex BLINK for Activity OFF in 10 Mb/s OFF for Half Duplex The LED_LINK pin in Mode 1 indicates the link status of the port. In 100BASE-T mode, link is established as a result of input receive amplitude compliant with the TPPMD specifications which will result in internal generation of signal detect. A 10 Mb/s Link is established as a result of the reception of at least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause the assertion of LED_LINK. LED_LINK will deassert in accordance with the Link Loss Timer as specified in the IEEE 802.3 specification. LED_ACT/LED_COL The LED_ACT/LED_COL pin in Mode 3 indicates Duplex status for 10 Mb/s or 100 Mb/s operation. The LED will be ON for Full Duplex and OFF for Half Duplex. In 10 Mb/s half duplex mode, the collision LED is based on the COL signal. Since these LED pins are also used as strap options, the polarity of the LED is dependent on whether the pin is pulled up or down. The LED_LINK pin in Mode 1 will be OFF when no LINK is present. 2.4.1 LEDs The LED_LINK pin in Mode 2 and Mode 3 will be ON to indicate Link is good and BLINK to indicate activity is present on activity. The BLINK frequency is defined in BLINK_FREQ, bits [7:6] of register LEDCR (18h). Since the Auto-Negotiation (AN) strap options share the LED output pins, the external components required for strapping and LED usage must be considered in order to avoid contention. Activity is defined as configured in LEDACT_RX, bit 8 of register LEDCR (18h). If LEDACT_RX is 0, Activity is signaled for either transmit or receive. If LEDACT_RX is 1, Activity is only signaled for receive. Specifically, when the LED outputs are used to drive LEDs directly, the active state of each output driver is dependent on the logic level sampled by the corresponding AN input upon power-up/reset. For example, if a given AN input is resistively pulled low then the corresponding output will be configured as an active high driver. Conversely, if a given AN input is resistively pulled high, then the corresponding output will be configured as an active low driver. The LED_SPEED pin indicates 10 or 100 Mb/s data rate of the port. The LED is ON when operating in 100Mb/s mode and OFF when operating in 10Mb/s mode. The functionality of this LED is independent of mode selected. The LED_ACT/LED_COL pin in Mode 1 indicates the presence of either transmit or receive activity. The LED will be ON for Activity and OFF for No Activity. In Mode 2, this pin indicates the Collision status of the port. The LED will be ON for Collision and OFF for No Collision. Refer to Figure 3 for an example of AN connections to external components at port A. In this example, the AN strapping results in Auto-Negotiation disabled with 100 Full-Duplex forced. The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose pins. 21 www.national.com DP83849I 2.4 LED Interface AN_EN_A =0 It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can interpret and configure to full-duplex operation, parallel detection can not recognize the difference between full and halfduplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the 802.3u specification, if a far-end link partner is configured to a forced full duplex 100BASE-TX ability, the parallel detection state machine in the partner would be unable to detect the full duplex capability of the far-end link partner. This link segment would negotiate to a half duplex 100BASE-TX configuration (same scenario for 10Mb/s). LED_LINK_A LED_SPEED_A LED_ACT/LED_COL_A DP83849I CRS and Collision reporting, all remaining MII signaling remains the same regardless of the selected duplex mode. AN1_A = 1 AN0_A = 1 165 165 165 2.2k 2.6 Internal Loopback The DP83849I includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto the media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled before selecting the Loopback mode. VCC GND Figure 3. AN Strapping and LED Loading Example 2.7 BIST 2.4.2 LED Direct Control The DP83849I provides another option to directly control any or all LED outputs through the LED Direct Control Register (LEDCR), address 18h. The register does not provide read access to LEDs. 2.5 Half Duplex vs. Full Duplex The DP83849I supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds. Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to maintain compliance with the IEEE 802.3 specification. Since the DP83849I is designed to support simultaneous transmit and receive activity it is capable of supporting fullduplex switched applications with a throughput of up to 200 Mb/s per port when operating in 100BASE-TX. Because the CSMA/CD protocol does not apply to full-duplex operation, the DP83849I disables its own internal collision sensing and reporting functions and modifies the behavior of Carrier Sense (CRS) such that it indicates only receive activity. This allows a full-duplex capable MAC to operate properly. The DP83849I incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be utilized to test the integrity of the transmit and receive data paths. BIST testing can be performed with the part in the internal loopback mode or externally looped back using a loopback cable fixture. The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continuous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit. For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (1Bh). The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (1Bh), bits [15:8]. All modes of operation (100BASE-TX, 10BASE-T) can run either half-duplex or full-duplex. Additionally, other than www.national.com 22 The DP83849I supports several modes of operation using the MII interface pins. The options are defined in the following sections and include: -- MII Mode -- RMII Mode -- 10 Mb Serial Network Interface (SNI) -- Single Clock MII Mode (SCMII) In addition, the DP83849I supports the standard 802.3u MII Serial Management Interface and a Flexible MII Port Assignment scheme. The modes of operation can be selected by strap options or register control. For RMII mode, it is required to use the strap option, since it requires a 50 MHz clock instead of the normal 25 MHz. In each of these modes, the IEEE 802.3 serial management interface is operational for device configuration and status. The serial management interface of the MII allows for the configuration and control of multiple PHY devices, gathering of status, error information, and the determination of the type and capabilities of the attached PHY(s). The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal TX_EN, and a transmit clock TX_CLK which runs at either 2.5 MHz or 25 MHz. Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-duplex operation when both a transmit and receive operation occur simultaneously. 3.1.2 Collision Detect For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. If the DP83849I is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network. The COL signal remains set for the duration of the collision. 3.1 MII Interface If a collision occurs during a receive operation, it is immediately reported by the COL signal. The DP83849I incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u standard. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems. This section describes the nibble wide MII data interface. When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1s after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. The nibble wide MII data interface consists of a receive bus and a transmit bus each with control signals to facilitate data transfer between the PHY and the upper layer (MAC). 3.1.3 Carrier Sense Carrier Sense (CRS) is asserted due to receive activity, once valid data is detected via the squelch function during Clause 22 of the IEEE 802.3u specification defines the 10 Mb/s operation. During 100 Mb/s operation CRS is Media Independent Interface. This interface includes a asserted when a valid link (SD) and two non-contiguous dedicated receive bus and a dedicated transmit bus. These zeros are detected on the line. two data buses, along with various control and status sig- For 10 or 100 Mb/s Half Duplex operation, CRS is asserted nals, allow for the simultaneous exchange of data between during either packet transmission or reception. the DP83849I and the upper layer agent (MAC). For 10 or 100 Mb/s Full Duplex operation, CRS is asserted The receive interface consists of a nibble wide data bus only due to receive activity. RXD[3:0], a receive error signal RX_ER, a receive data valid flag RX_DV, and a receive clock RX_CLK for syn- CRS is deasserted following an end of packet. chronous transfer of the data. The receive clock operates at either 2.5 MHz to support 10 Mb/s operation modes or at 25 MHz to support 100 Mb/s operational modes. 3.1.1 Nibble-wide MII Data Interface 23 www.national.com DP83849I 3.0 MAC Interface DP83849I 3.2 Reduced MII Interface The DP83849I incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits at a time using the 50 MHz RMII_REF clock for both transmit and receive. The following pins are used in RMII mode: -- TX_EN -- TXD[1:0] -- RX_ER (optional for Mac) -- CRS_DV -- RXD[1:0] -- X1 (RMII Reference clock is 50 MHz) In addition, the RMII mode supplies an RX_DV signal which allows for a simpler method of recovering receive data without having to separate RX_DV from the CRS_DV indication. This is especially useful for diagnostic testing where it may be desirable to externally loop Receive MII data directly to the transmitter. The RX_ER output may be used by the MAC to detect error conditions. It is asserted for symbol errors received during a packet, False Carrier events, and also for FIFO underrun or overrun conditions. Since the Phy is required to corrupt receive data on an error, a MAC is not required to use RX_ER. It is important to note that since both digital channels in the DP83849I share the X1/RMII_REF input, both channels must have RMII mode enabled or both channels must have RMII mode disabled. Either channel may be in 10Mb or 100Mb mode in RMII or non-RMII mode. Since the reference clock operates at 10 times the data rate for 10 Mb/s operation, transmit data is sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached device can sample the data every 10 clocks. RMII mode requires a 50 MHz oscillator be connected to the device X1 pin. A 50 MHz crystal is not supported. To tolerate potential frequency differences between the 50 MHz reference clock and the recovered receive clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is programmable to minimize propagation delay based on expected packet size and clock accuracy. This allows for supporting a range of packet sizes including jumbo frames. The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO. Underrun and Overrun conditions can be reported in the RMII and Bypass Register (RBR). The following table indicates how to program the elasticity buffer fifo (in 4-bit increments) based on expected max packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter clock) have the same accuracy. Packet lengths can be scaled linearly based on accuracy (+/- 25ppm would allows packets twice as large). If the threshold setting must support both 10Mb and 100Mb operation, the setting should be made to support both speeds. Table 4. Supported packet sizes at +/-50ppm frequency accuracy Start Threshold Latency Tolerance Recommended Packet Size RBR[1:0] at +/- 50ppm 100Mb 10Mb 100Mb 10Mb 01 (default) 2 bits 8 bits 2,400 bytes 9,600 bytes 10 6 bits 4 bits 7,200 bytes 4,800 bytes 11 10 bits 8 bits 12,000 bytes 9,600 bytes 00 14 bits 12 bits 16,800 bytes 14,400 bytes www.national.com 24 3.4 Single Clock MII Mode The DP83849I incorporates a 10 Mb Serial Network Interface (SNI) which allows a simple serial data interface for 10 Mb only devices. This is also referred to as a 7-wire interface. While there is no defined standard for this interface, it is based on early 10 Mb physical layer devices. Data is clocked serially at 10 MHz using separate transmit and receive paths. The following pins are used in SNI mode: Single Clock MII (SCMII) Mode allows MII operation using a single 25MHz reference clock. Normal MII Mode requires three clocks, a reference clock for physical layer functions, a Transmit MII clock, and a Receive MII clock. Similar to RMII mode, Single Clock MII mode requires only the reference clock. In addition to reducing the number of pins required, this mode allows the attached MAC device to use only the reference clock domain. Since the DP83849I has two ports, this actually reduces the number of clocks from 6 to 1. A/C Timing requirements for SCMII operation are similar to the RMII timing requirements. -- -- -- -- -- -- -- TX_CLK TX_EN TXD[0] RX_CLK RXD[0] CRS COL For 10Mb operation, as in RMII mode, data is sampled and driven every 10 clocks since the reference clock is at 10x the data rate. Separate control bits allow enabling the Transmit and Receive Single Clock modes separately, allowing just transmit or receive to operate in this mode. Control of Single Clock MII mode is through the RBR register. Single Clock MII mode incorporates the use of the RMII elasticity buffer, which is required to tolerate potential frequency differences between the 25MHz reference clock and the recovered receive clock. Settings for the Elasticity Buffer for SCMII mode are detailed in the following table. Table 5. Supported SCMII packet sizes at +/-50ppm frequency accuracy Start Threshold Latency Tolerance Recommended Packet Size RBR[1:0] at +/- 50ppm 100Mb 10Mb 100Mb 10Mb 01 (default) 4 bits 8 bits 4,000 bytes 9,600 bytes 10 4 bits 8 bits 4,000 bytes 9,600 bytes 11 12 bits 8 bits 9.600 bytes 9,600 bytes 00 12 bits 8 bits 9,600 bytes 9,600 bytes 25 www.national.com DP83849I 3.3 10 Mb Serial Network Interface (SNI) DP83849I 3.5 Flexible MII Port Assignment The DP83849I supports a flexible assignment scheme for each of the channels to the MII/RMII interface. Either of the MII ports may be assigned to the internal channels A/B. These values are controlled by the RMII and Bypass Register (RBR), address 17h. Transmit assignments and Receive assignments can be made separately to allow even more flexibility (i.e. both channels could transmit from MII A while still allowing separate receive paths for the channels). In addition, the opposite receive channel may be used as the transmit source for each channel. As shown in Figure 4, Channel A receive data may be used as the Channel B transmit data source while Channel B receive data may be used as the Channel A transmit data source. For proper clock synchronization, this function requires the device be in RMII mode or Single Clock MII mode of operation. A configuration strap is provided on pin 56, RXD2_B/EXTENDER_EN to enable this mode. TX TX MII Port A RX Channel A 10BASE-T or 100BASE-TX Channel B 10BASE-T or 100BASE-TX RX TX TX MII Port B RX RX Figure 4. MII Port Mapping www.national.com 26 Note that Channel A is the master of MII Port A, and Chan- RX MII Port Mapping controls and configurations are nel B is the master of MII Port B. This means that in order shown in the following tables: for Channel B to control MII Port A, Channel A must be configured to either control MII Port B or be Disabled; the reverse is also true. Table 6. RX MII Port Mapping Controls RBR[12:11] Desired RX Channel Destination 00 Normal Port 01 Opposite Port 10 Both Ports 11 Disabled Table 7. RX MII Port Mapping Configurations Channel A RBR[12:11] Channel B RBR[12:11] RX MII Port A Source RX MII Port B Source 00 00 Channel A Channel B 00 01 Channel A Channel B 00 10 Channel A Channel B 00 11 Channel A Disabled 01 00 Channel A Channel B 01 01 Channel B Channel A 01 10 Channel B Channel A 01 11 Disabled Channel A 10 00 Channel A Channel B 10 01 Channel B Channel A 10 10 Channel A Channel B 10 11 Channel A Channel A 11 00 Disabled Channel B 11 01 Channel B Disabled 11 10 Channel B Channel B 11 11 Disabled Disabled 27 www.national.com DP83849I 3.5.1 RX MII Port Mapping DP83849I 3.5.2 TX MII Port Mapping TX MII Port Mapping controls and configurations are shown in the following tables: Table 8. TX MII Port Mapping Controls RBR[10:9] TX Channel Source 00 Normal Port 01 Opposite Port 10 Opposite RX Port 11 Disabled Table 9. TX MII Port Mapping Configurations Channel A RBR[10:9] Port A TX Source Channel B RBR[10:9] Port B TX Source 00 MII Port A 00 MII Port B 01 MII Port B 01 MII Port A 10 RX Channel B 10 RX Channel A 11 Disabled 11 Disabled 3.5.3 Common Flexible MII Port Configurations Table 10. Common Flexible MII Port Configurations Mode Channel A RBR[12:9] Channel B RBR[12:9] Description Normal 0000 0000 MII port A assigned to Channel A, MII Port B assigned to Channel B Full Port Swap 0101 0101 MII port A assigned to Channel B, MII Port B assigned to Channel A Extender 1110 1110 MII RX disabled, Channel A transmits from Channel B RX data, Channel B transmits from Channel A RX data Broadcast TX MII Port A xx00 xx01 Both Channels transmit from TX MII Port A Broadcast TX MII Port B xx01 xx00 Both Channels transmit from TX MII Port B Mirror RX Channel A 10xx 11xx Channel A RX traffic appears on both Ports. Mirror RX Channel B 11xx 10xx Channel B RX traffic appears on both Ports. Disable Port A 1111 xxxx MII Port A is disabled Disable Port B xxxx 1111 MII Port B is disabled www.national.com 28 The DP83849I provides a simple strap option to automatically configure both channels for Extender Mode with no device register configuration necessary. The EXTENDER_EN Strap can be used in conjunction with the Auto-Negotiation Straps (AN_EN, AN0, AN1), the RMII Mode Strap to allow many possible configurations. If Extender Mode is strapped but RMII Mode is not, both channels will automatically be configured for Single Clock MII Receive and Transmit Modes. The optional use of RMII Mode in conjunction with Extender Mode allows flexibility in the system design. Several common configurations are shown in Table 11. Table 11. Common Strapped Extender Mode Configurations Mode Auto-Negotiation Straps 100Mb Copper Extender Both channels are forced to 100Mb Full Duplex 10Mb Copper Extender Both channels are forced to 10Mb Full Duplex 3.5.5 Notes and Restrictions -- Extender: Both channels must be operating at the same speed (10 or 100Mb). This can be accomplished using straps or channel register controls. Both channels must be in Full Duplex mode. Both channels must either be in RMII Mode (RBR:RMII_EN = 1) or full Single Clock MII Mode (RBR:SCMII_RX = 1 and RBR:SCMII_TX = 1) to ensure synchronous operation. If only one RX to TX path is enabled, SCMII_RX in the RX channel (RBR register 17h bit 7) and SCMII_TX in the TX channel (RBR register 17h bit 6) must be set to 1. -- Broadcast TX MII Port Mode: To ensure synchronous operation, both channels must be in RMII Mode (RBR register 17h bit 5 = 1) or in Single Clock TX MII Mode (RBR register 17h bit 6 = 1). Both channels must be operating at the same speed (10 or 100Mb). Both channels must be in Full Duplex mode to ensure no collisions are seen. This is because in Single Clock TX MII Mode, a collision on one PHY channel would cause both channels to send the Jam pattern. -- RMII Mode: Both Channels must have RMII Mode enabled or disabled concurrently due to the internal reference clocking scheme. In Full Port Swap Mode, Channels are not required to have a common speed. -- 10Base-T Serial Mode: This MAC-side mode, also known as Serial Network Interface (SNI), may not be used when both channels share data connections (Extender or Broadcast TX MII Port). This is due to the requirement of synchronous operation between channels, which is not supported in SNI Mode. -- CRS Assignment: When a channel is not in RMII Mode, its associated CRS pin is sourced from the transmitter and controlled by the TX MII Port Assignment, bits [10:9] of RBR (17h). When a channel is in RMII Mode, the as- -- -- -- -- -- -- 29 sociated CRS pin is sourced from the receiver and controlled by the RX MII Port Assignment, bits [12:11] of RBR (17h). Output Enables: Flexible MII Port Assignment does not control signal output enables. Test Modes: Test modes are not designed to be compatible with Flexible MII Port Selection, which assumes default MII pin directions. LED Assignment: LEDs are associated with their respective digital channels, and therefore do not get mapped to alternate channels. For example, assertion of LED_LINK_A indicates valid link status for Channel A independent of the MII Port Assignment. Straps: Strap pins are always associated with their respective channel, i.e. a strap on RX_ER_A is used by Channel A. Port Isolate Mode: Each MII port's Isolate function, bit 10 of BMCR (00h) is always associated with its respective channel, i.e. the Isolate function for Port A is always controlled by Channel A's BMCR (00h). Due to the various possible combinations of TX and RX port selection, it may not be advisable to place a port in Isolate mode. Energy Detect and Powerdown Modes: The output enables for each MII port are always controlled by the respective channel Energy Detect and Powerdown functions. These functions should be disabled whenever an MII port is in use but not assigned to its default channel. Note that Extender/Media Converter modes allow the use of Energy Detect and Powerdown modes if the RX MII ports are not in use. www.national.com DP83849I 3.5.4 Strapped Extender Mode DP83849I 3.6 802.3u MII Serial Management Interface The DP83849I waits until it has received this preamble sequence before responding to any other transaction. Once the DP83849I serial management port has been initialized no further preamble sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit has occurred. 3.6.1 Serial Management Register Access The serial management MII specification defines a set of thirty-two 16-bit status and control registers that are accessible through the management interface pins MDC and MDIO. The DP83849I implements all the required MII registers as well as several optional registers. These registers are fully described in Section 7.0. A description of the serial management access protocol follows. The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the first bit of Turnaround. The addressed DP83849I drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 5 shows the timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the DP83849I (PHY) for a typical register read access. 3.6.2 Serial Management Access Protocol The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in Table 12. For write transactions, the station management entity writes data to the addressed DP83849I thus eliminating the In addition, the MDIO pin requires a pull-up resistor (1.5 requirement for MDIO Turnaround. The Turnaround time is k) which, during IDLE and turnaround, will pull MDIO filled by the management entity by inserting <10>. Figure 6 high. In order to initialize the MDIO interface, the station shows the timing relationship for a typical MII register write management entity sends a sequence of 32 contiguous access. logic ones on MDIO to provide the DP83849I with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device if an invalid start, opcode, or turnaround bit is detected. Table 12. Typical MDIO Frame Format MII Management Serial Protocol <idle><start><op code><device addr><reg addr><turnaround><data><idle> Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle> Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle> MDC MDIO Z Z (STA) Z MDIO Z (PHY) Z Idle 0 1 1 0 0 1 1 0 0 0 0 0 0 0 Start Opcode (Read) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 TA Register Data Figure 5. Typical MDC/MDIO Read Operation www.national.com 30 Z Idle DP83849I MDC MDIO Z Z (STA) Z Idle 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Start Opcode (Write) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) TA Register Data Z Idle Figure 6. Typical MDC/MDIO Write Operation 3.6.3 Serial Management Preamble Suppression The DP83849I supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management controller) determines that all PHYs in the system support Preamble Suppression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction. The DP83849I requires a single initialization sequence of 32 bits of preamble following hardware/software reset. This requirement is generally met by the mandatory pull-up resistor on MDIO in conjunction with a continuous MDC, or the management access made to determine whether Preamble Suppression is supported. While the DP83849I requires an initial preamble sequence of 32 bits for management initialization, it does not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit between management transactions is required as specified in the IEEE 802.3u specification. 3.6.4 Simultaneous Register Write The DP83849I incorporates a mode which allows simultaneous write access to both Port A and B register blocks at the same time. This mode is selected by setting bit 15 of RMII and Bypass Register (RBR, address 17h) in Port A. As long as this bit remains set, subsequent writes to Port A will write to registers in both ports. Register reads are unaffected. Each port must still be read individually. 31 www.national.com DP83849I 4.0 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following: The block diagram in Figure 7. provides an overview of each functional block within the 100BASE-TX transmit section. The Transmitter section consists of the following functional blocks: -- Code-group Encoder and Injection block -- Scrambler block (bypass option) -- NRZ to NRZI encoder block -- Binary to MLT-3 converter / Common Driver The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for applications 4.1 100BASE-TX TRANSMITTER where data conversion is not always required. The The 100BASE-TX transmitter consists of several functional DP83849I implements the 100BASE-TX transmit state blocks which convert synchronous 4-bit nibble data, as pro- machine diagram as specified in the IEEE 802.3u Stanvided by the MII, to a scrambled MLT-3 125 Mb/s serial dard, Clause 24. data stream. Because the 100BASE-TX TP-PMD is integrated, the differential output pins, PMD Output Pair, can be directly routed to the magnetics. -- 100BASE-TX Transmitter -- 100BASE-TX Receiver -- 10BASE-T Transceiver Module TX_CLK TXD[3:0] / TX_EN DIVIDE BY 5 4B5B CODEGROUP ENCODER & 5B PARALLEL TO SERIAL 125MHZ CLOCK SCRAMBLER MUX BP_SCR 100BASE-TX LOOPBACK MLT[1:0] NRZ TO NRZI ENCODER BINARY TO MLT-3 / COMMON DRIVER PMD OUTPUT PAIR Figure 7. 100BASE-TX Transmit Block Diagram www.national.com 32 DP83849I Table 13. 4B5B Code-Group Encoding/Decoding DATA CODES 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111 IDLE AND CONTROL CODES H 00100 HALT code-group - Error code I 11111 Inter-Packet IDLE - 0000 (Note 1) J 11000 First Start of Packet - 0101 (Note 1) K 10001 Second Start of Packet - 0101 (Note 1) T 01101 First End of Packet - 0000 (Note 1) R 00111 Second End of Packet - 0000 (Note 1) INVALID CODES V 00000 V 00001 V 00010 V 00011 V 00101 V 00110 V 01000 V 01100 Note: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted. 33 www.national.com DP83849I 4.1.1 Code-group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer to Table 13 for 4B to 5B code-group mapping details. The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of Transmit Enable signal from the MAC, the code-group encoder injects the T/R code-group pair (01101 00111) indicating the end of the frame. After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream until the next transmit packet is detected (reassertion of Transmit Enable). 4.1.2 Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels at the PMD and on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (i.e., continuous transmission of IDLEs). transmit transformer primary winding, resulting in a MLT-3 signal. The 100BASE-TX MLT-3 signal sourced by the PMD Output Pair common driver is slew rate controlled. This should be considered when selecting AC coupling magnetics to ensure TP-PMD Standard compliant transition times (3 ns < Tr < 5 ns). The 100BASE-TX transmit TP-PMD function within the DP83849I is capable of sourcing only MLT-3 encoded data. Binary output from the PMD Output Pair is not possible in 100 Mb/s mode. 4.2 100BASE-TX RECEIVER The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125 Mb/s serial data stream to synchronous 4-bit nibble data that is provided to the MII. Because the 100BASE-TX TP-PMD is integrated, the differential input pins, RD, can be directly routed from the AC coupling magnetics. See Figure 8 for a block diagram of the 100BASE-TX receive function. This provides an overview of each functional block within the 100BASE-TX receive section. The Receive section consists of the following functional blocks: -- -- -- -- The scrambler is configured as a closed loop linear feed-- back shift register (LFSR) with an 11-bit polynomial. The output of the closed loop LFSR is X-ORd with the serial -- NRZ data from the code-group encoder. The result is a -- scrambled data stream with sufficient randomization to -- decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83849I uses the PHY_ID (pins -- -- PHYAD [4:1]) to set a unique seed value. -- Analog Front End Digital Signal Processor Signal Detect MLT-3 to Binary Decoder NRZI to NRZ Decoder Serial to Parallel Descrambler Code Group Alignment 4B/5B Decoder Link Integrity Monitor Bad SSD Detection 4.1.3 NRZ to NRZI Encoder After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 Unshielded twisted pair cable. 4.2.1 Analog Front End In addition to the Digital Equalization and Gain Control, the DP83849I includes Analog Equalization and Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization required in the DSP. 4.1.4 Binary to MLT-3 Convertor The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams are then fed to the twisted pair output driver which converts the voltage to current and alternately drives either side of the www.national.com 4.2.2 Digital Signal Processor The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation. 34 DP83849I RX_DV/CRS RX_CLK RXD[3:0] / RX_ER 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT RX_DATA VALID SSD DETECT LINK INTEGRITY MONITOR DESCRAMBLER NRZI TO NRZ DECODER MLT-3 TO BINARY DECODER SIGNAL DETECT DIGITAL SIGNAL PROCESSOR ANALOG FRONT END RD +/- Figure 8. 100BASE-TX Receive Block Diagram 35 www.national.com DP83849I 4.2.2.1 Digital Adaptive Equalization and Gain Control When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated to ensure the integrity of the transmission. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will over-compensate for shorter, less attenuating lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. The compensation or equalization must be adap- tive to ensure proper conditioning of the received signal independent of the cable length. The DP83849I utilizes an extremely robust equalization scheme referred as `Digital Adaptive Equalization.' The Digital Equalizer removes ISI (inter symbol interference) from the receive data stream by continuously adapting to provide a filter with the inverse frequency response of the channel. Equalization is combined with an adaptive gain control stage. This enables the receive 'eye pattern' to be opened sufficiently to allow very reliable data recovery. The curves given in Figure 9 illustrate attenuation at certain frequencies for given cable lengths. This is derived from the worst case frequency vs. attenuation figures as specified in the EIA/TIA Bulletin TSB-36. These curves indicate the significant variations in signal attenuation that must be compensated for by the receive adaptive equalization circuit. Figure 9. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable www.national.com 36 DP83849I 4.2.2.2 Base Line Wander Compensation Figure 10. 100BASE-TX BLW Event The DP83849I is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TPPMD defined "killer" pattern. PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters. Note that the reception of normal 10BASE-T link pulses BLW can generally be defined as the change in the aver- and fast link pulses per IEEE 802.3u Auto-Negotiation by age DC content, relatively short period over time, of an AC the 100BASE-TX receiver do not cause the DP83849I to coupled digital transmission over a given transmission assert signal detect. medium. (i.e., copper wire). BLW results from the interaction between the low frequency components of a transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission system. If the low frequency content of the digital bit stream goes below the low frequency pole of the AC coupling transformers then the droop characteristics of the transformers will dominate resulting in potentially serious BLW. The digital oscilloscope plot provided in Figure 10 illustrates the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately 800 mV of DC offset for a period of 120 s. Left uncompensated, events such as this can cause packet loss. 4.2.3 Signal Detect The signal detect function of the DP83849I is incorporated to meet the specifications mandated by the ANSI FDDI TP- 4.2.4 MLT-3 to NRZI Decoder The DP83849I decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data. 4.2.5 NRZI to NRZ In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the descrambler. 4.2.6 Serial to Parallel The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols to the PCS Rx state machine. 37 www.national.com DP83849I 4.2.7 Descrambler Signal detect must be valid for 395us to allow the link monitor to enter the 'Link Up' state, and enable the transmit and receive functions. A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) 4.2.11 Bad SSD Detection as represented in the equations: SD = ( UD N ) UD = ( SD N ) Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5B code-groups. In order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer starts a 722 s countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722 s period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the line state monitor does not recognize sufficient unscrambled IDLE code-groups within the 722 s period, the entire descrambler will be forced out of the current state of synchronization and reset in order to reacquire synchronization. 4.2.8 Code-group Alignment The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5 bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. 4.2.9 4B/5B Decoder The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups. 4.2.10 100BASE-TX Link Integrity Monitor The 100 Base TX Link monitor ensures that a valid and stable link is established before enabling both the Transmit and Receive PCS layer. www.national.com A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /J/K. If this condition is detected, the DP83849I will assert RX_ER and present RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the False Carrier Sense Counter register (FCSCR) will be incremented by one. Once at least two IDLE code groups are detected, RX_ER and CRS become de-asserted. 4.3 10BASE-T TRANSCEIVER MODULE The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not required on the 10BASE-T interface since this is integrated inside the DP83849I. This section focuses on the general 10BASE-T system level operation. 4.3.1 Operational Modes The DP83849I has two basic 10BASE-T operational modes: -- Half Duplex mode -- Full Duplex mode Half Duplex Mode In Half Duplex mode the DP83849I functions as a standard IEEE 802.3 10BASE-T transceiver supporting the CSMA/CD protocol. Full Duplex Mode In Full Duplex mode the DP83849I is capable of simultaneously transmitting and receiving without asserting the collision signal. The DP83849I's 10 Mb/s ENDEC is designed to encode and decode simultaneously. 4.3.2 Smart Squelch The smart squelch is responsible for determining when valid data is present on the differential receive inputs. The DP83849I implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted pair inputs (refer to Figure 11). The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will 38 the circuitry that valid data is present. At this time, the smart squelch circuitry is reset. Valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection. Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of <150 ns >150 ns <150 ns VSQ+ VSQ+(reduced) VSQ-(reduced) VSQend of packet start of packet Figure 11. 10BASE-T Twisted Pair Smart Squelch Operation 39 www.national.com DP83849I be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will not be rejected. This checking procedure results in the loss of typically three preamble bits at the beginning of each packet. DP83849I 4.3.3 Collision Detection and SQE When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. Collisions are also reported when a jabber condition is detected. The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected it is reported immediately (through the COL pin). When heartbeat is enabled, approximately 1 s after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10-bit times is generated to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. The SQE test is inhibited when the PHY is set in full duplex mode. SQE can also be inhibited by setting the HEARTBEAT_DIS bit in the 10BTSCR register. Once disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted. This signal has to be deasserted for approximately 500 ms (the "unjab" time) before the Jabber function re-enables the transmit outputs. The Jabber function is only relevant in 10BASE-T mode. 4.3.7 Automatic Link Polarity Detection and Correction The DP83849I's 10BASE-T transceiver module incorporates an automatic link polarity detection circuit. When three consecutive inverted link pulses are received, bad polarity is reported. A polarity reversal can be caused by a wiring error at either end of the cable, usually at the Main Distribution Frame (MDF) or patch panel in the wiring closet. 4.3.4 Carrier Sense The bad polarity condition is latched in the 10BTSCR register. The DP83849I's 10BASE-T transceiver module corrects for this error internally and will continue to decode received data correctly. This eliminates the need to correct the wiring error immediately. Carrier Sense (CRS) may be asserted due to receive activity once valid data is detected via the squelch function. 4.3.8 Transmit and Receive Filtering For 10 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10 Mb/s Full Duplex operation, CRS is asserted only during receive activity. CRS is deasserted following an end of packet. 4.3.5 Normal Link Pulse Detection/Generation External 10BASE-T filters are not required when using the DP83849I, as the required signal conditioning is integrated into the device. Only isolation transformers and impedance matching resistors are required for the 10BASE-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30 dB. The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the 4.3.9 Transmitter absence of transmit data. The encoder begins operation when the Transmit Enable Link pulses are used to check the integrity of the connec- input (TX_EN) goes high and converts NRZ data to pretion with the remote end. If valid link pulses are not emphasized Manchester data for the transceiver. For the received, the link detector disables the 10BASE-T twisted duration of TX_EN, the serialized Transmit Data (TXD) is encoded for the transmit-driver pair (PMD Output Pair). pair transmitter, receiver and collision detection functions. TXD must be valid on the rising edge of Transmit Clock When the link integrity function is disabled (TX_CLK). Transmission ends when TX_EN deasserts. (FORCE_LINK_10 of the 10BTSCR register), a good link is The last transition is always positive; it occurs at the center forced and the 10BASE-T transceiver will operate regard- of the bit cell if the last bit is a one, or at the end of the bit less of the presence of link pulses. cell if the last bit is a zero. 4.3.6 Jabber Function 4.3.10 Receiver The jabber function monitors the DP83849I's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 85 ms. The decoder detects the end of a frame when no additional mid-bit transitions are detected. Within one and a half bit times after the last bit, carrier sense is de-asserted. Receive clock stays active for five more bit times after CRS goes low, to guarantee the receive timings of the controller. www.national.com 40 5.1 TPI Network Circuit Figure 12 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. Below is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application. Pulse H1102 Pulse H2019 Belfuse S558-5999-U7 Halo TG110-S050N2RL Vdd TPRDM Vdd COMMON MODE CHOKES MAY BE REQUIRED. 49.9 0.1F 1:1 49.9 TDRDP RD- 0.1F* RD+ TD- TPTDM TD+ 0.1F* Vdd 49.9 RJ45 1:1 0.1F T1 NOTE: CENTER TAP IS PULLED TO VDD 49.9 *PLACE CAPACITORS CLOSE TO THE TRANSFORMER CENTER TAPS TPTDP All values are typical and are +/- 1% PLACE RESISTORS AND CAPACITORS CLOSE TO THE DEVICE. Figure 12. 10/100 Mb/s Twisted Pair Interface 41 www.national.com DP83849I 5.0 Design Guidelines DP83849I 5.2 ESD Protection Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is assembled, internal components are less sensitive from ESD events. capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of 100W and a maximum of 500W. If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between X2 and the crystal. As a starting point for evaluating an oscillator circuit, if the The network interface pins are more susceptible to ESD requirements for the crystal are not known, CL1 and CL2 should be set at 33 pF, and R1 should be set at 0. events. Specification for 25 MHz crystal are listed in Table 16. 5.3 Clock In (X1) Requirements The DP83849I supports an external CMOS level oscillator source or a crystal resonator device. X2 X1 Oscillator R1 If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating. Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 14 and Table 15. CL1 Crystal CL2 Figure 13. Crystal Oscillator Circuit A 25 MHz, parallel, 20 pF load crystal resonator should be used if a crystal source is desired. Figure 13 shows a typical connection for a crystal resonator circuit. The load Table 14. 25 MHz Oscillator Specification Parameter Min Frequency Typ Max 25 Units Condition MHz Frequency +50 ppm Operational Temperature +50 ppm 1 year aging Rise / Fall Time 6 nsec 20% - 80% Jitter 8001 psec Short term Jitter 8001 psec Long term Tolerance Frequency Stability Symmetry 40% 60% 1 This Duty Cycle limit is provided as a guideline for component selection and to guaranteed by production testing. Refer to AN-1548, "PHYTER 100 Base-TX Reference Clock Jitter Tolerance," for details on jitter performance. www.national.com 42 Parameter Min Typ Frequency Max Units 50 Condition MHz Frequency +50 ppm Operational Temperature +50 ppm Operational Temperature Rise / Fall Time 6 nsec 20% - 80% Jitter 8001 psec Short term Jitter 8001 psec Long term Tolerance Frequency Stability Symmetry 1 40% 60% Duty Cycle This limit is provided as a guideline for component selection and to guaranteed by production testing. Refer to AN-1548, "PHYTER 100 Base-TX Reference Clock Jitter Tolerance," for details on jitter performance. Table 16. 25 MHz Crystal Specification Parameter Min Typ Frequency Max Units 25 Condition MHz Frequency +50 ppm +50 ppm 40 pF Tolerance Operational Temperature Frequency 1 year aging Stability Load Capacitance 25 5.4 Power Feedback Circuit To ensure correct operation for the DP83849I, parallel caps with values of 10 F and 0.1 F should be placed close to pin 31 (PFBOUT) of the device. Pin 7 (PFBIN1), pin 28 (PFBIN2), pin 34 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (.1 F). See Figure 14 below for proper connections. Pin 31 (PFBOUT) 10 F + Pin 7 (PFBIN1) .1 F Pin 28 (PFBIN2) .1 F - .1 F Pin 34 (PFBIN3) Pin 54 (PFBIN4) .1 F .1 F Figure 14. Power Feeback Connection 43 www.national.com DP83849I Table 15. 50 MHz Oscillator Specification DP83849I 5.5 Power Down/Interrupt 5.6 Energy Detect Mode The Power Down and Interrupt functions are multiplexed on pin 18 and pin 44 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR (11h) will configure the pin as an active low interrupt output. Ports A and B can be powered down individually, using the separate PWRDOWN_INT_A and PWRDOWN_INT_B pins. When Energy Detect is enabled and there is no activity on the cable, the DP83849I will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83849I to go through a normal power up sequence. Regardless of cable activity, the DP83849I will occasionally wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible. Energy detect functionality is controlled via register Energy Detect Control (EDCR), address 1Dh. 5.5.1 Power Down Control Mode The PWRDOWN_INT pins can be asserted low to put the device in a Power Down mode. This is equivalent to setting bit 11 (Power Down) in the Basic Mode Control Register, BMCR (00h). An external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the device can be configured to initialize into a Power Down state by use of an external pulldown resistor on the PWRDOWN_INT pin. Since the device will still respond to management register accesses, setting the INT_OE bit in the MICR register will disable the PWRDOWN_INT input, allowing the device to exit the Power Down state. 5.7 Link Diagnostic Capabilities 5.5.2 Interrupt Mechanisms 5.7.1 Linked Cable Status Since each port has a separate interrupt pin, the interrupts can be connected individually or may be combined in a wired-OR fashion. If the interrupts share a single connection, each port status should be checked following an interrupt. In an active connection with a valid link status, the following diagnostic capabilities are available: The DP83849I contains several system diagnostic capabilities for evaluating link quality and detecting potential cabling faults in Twisted Pair cabling. Software configuration is available through the Link Diagnostics Registers Page 2 which can be selected via Page Select Register (PAGESEL), address 13h. These capabilities include: -- Linked Cable Status -- Link Quality Monitor -- TDR (Time Domain Reflectometry) Cable Diagnostics -- Polarity reversal -- Cable swap (MDI vs MDIX) detection The interrupt function is controlled via register access. All -- 100Mb Cable Length Estimation interrupt sources are disabled by default. Setting bit 1 -- Frequency offset relative to link partner (INTEN) of MICR (11h) will enable interrupts to be output, -- Cable Signal Quality Estimation dependent on the interrupt mask set in the lower byte of the MISR (12h). The PWRDOWN_INT pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading 5.7.1.1 Polarity Reversal the upper byte of the MISR. One or more bits in the MISR The DP83849I detects polarity reversal by detecting negawill be set, denoting all currently pending interrupts. Read- tive link pulses. The Polarity indication is available in bit 12 ing of the MISR clears ALL pending interrupts. of the PHYSTS (10h) or bit 4 of the 10BTSCR (1Ah). Example: To generate an interrupt on a change of link sta- Inverted polarity indicates the positive and negative contus or on a change of energy detect power state, the steps ductors in the receive pair are swapped. Since polarity is corrected by the receiver, this does not necessarily indicate would be: a functional problem in the cable. -- Write 0003h to MICR to set INTEN and INT_OE Since the polarity indication is dependent on link pulses -- Write 0060h to MISR to set ED_INT_EN and from the link partner, polarity indication is only valid in LINK_INT_EN 10Mb modes of operation, or in 100Mb Auto-Negotiated -- Monitor PWRDOWN_INT pin mode. Polarity indication is not available in 100Mb forced mode of operation or in a parallel detected 100Mb mode. When PWRDOWN_INT pin asserts low, the user would read the MISR register to see if the ED_INT or LINK_INT bits are set, i.e. which source caused the interrupt. After reading the MISR, the interrupt bits should clear and the PWRDOWN_INT pin will deassert. www.national.com 5.7.1.2 Cable Swap Indication As part of Auto-Negotiation, the DP83849I has the ability (using Auto-MDIX) to automatically detect a cable with swapped MDI pairs and select the appropriate pairs for transmitting and receiving data. Normal operation is termed MDI, while crossed operation is MDIX. The MDIX status can be read from bit 14 of the PHYSTS (10h). 44 The DP83849I provides a method of estimating cable length based on electrical characteristics of the 100Mb Link. This essentially provides an effective cable length rather than a measurement of the physical cable length. The cable length estimation is only available in 100Mb mode of operation with a valid Link status. The cable length estimation is available at the Link Diagnostics Registers - Page 2, register 100Mb Length Detect (LEN100_DET), address 14h. Software is expected to read initial adapted values and then program the thresholds based on an expected valid range. This mechanism takes advantage of the fact that the DSP adaption should remain in a relatively small range once a valid link has been established. 5.7.2.1 Link Quality Monitor Control and Status Control of the Link Quality Monitor is done through the Link Quality Monitor Register (LQMR), address 1Dh and the Link Quality Data Register (LQDR), address 1Bh of the Link Diagnostics Registers - Page 2. The LQMR register 5.7.1.4 Frequency Offset Relative to Link Partner includes a global enable to enable the Link Quality Monitor function. In addition, it provides warning status from both As part of the 100Mb clock recovery process, the DSP high and low thresholds for each of the monitored parameimplementation provides a frequency control parameter. ters. Note that individual low or high parameter threshold This value may be used to indicate the frequency offset of comparisons can be disabled by setting to the minimum or the device relative to the link partner. This operation is only maximum values. available in 100Mb operation with a valid link status. The frequency offset can be determined using the register To allow the Link Quality Monitor to interrupt the system, 100Mb Frequency Offset Indication (FREQ100), address the Interrupt must be enabled through the interrupt control registers, MICR (11h) and MISR (12h). 15h, of the Link Diagnostics Registers - Page 2. Two different versions of the Frequency Offset may be monitored through bits [7:0] of register FREQ100 (15h). The first is the long-term Frequency Offset. The second is the current Frequency Control value, which includes shortterm phase adjustments and can provide information on the amount of jitter in the system. 5.7.1.5 Cable Signal Quality Estimation 5.7.2.2 Checking Current Parameter Values Prior to setting Threshold values, it is recommended that software check current adapted values. The thresholds may then be set relative to the adapted values. The current adapted values can be read using the LQDR register by setting the Sample_Param bit [13] of LQDR, address (1Eh). The cable signal quality estimator keeps a simple tracking of results of the DSP and can be used to generate an approximate Signal-to-Noise Ratio for the 100Mb receiver. This information is available to software through the Link Diagnostics Registers - Page 2: Variance Control (VAR_CTRL), address 1Ah and Data (VAR_DATA), address 1Bh. For example, to read the DBLW current value: The variance computation times (VAR_TIMER) can be chosen from the set of {2, 4, 6, 8} ms. The 32-bit variance sum can be read by two consecutive reads of the VAR_DATA register. This sum can be used to compute an SNR estimate by software using the following equation: 5.7.2.3 Threshold Control SNR = 10log10((37748736 * VAR_TIMER) / Variance). 5.7.2 Link Quality Monitor The Link Quality Monitor allows a method to generate an alarm when the DSP adaption strays from a programmable window. This could occur due to changes in the cable which could indicate a potential problem. Software can program thresholds for the following DSP parameters to be used to interrupt the system: -- -- -- -- -- Digital Equalizer C1 Coefficient (DEQ C1) Digital Adaptive Gain Control (DAGC) Digital Base-Line Wander Control (DBLW) Recovered Clock Long-Term Frequency Offset (FREQ) Recovered Clock Frequency Control (FC) 1. Write 2400h to LQDR (1Eh) to set the Sample_Param bit and set the LQ_PARAM_SEL[2:0] to 010. 2. Read LQDR (1Eh). Current DBLW value is returned in the low 8 bits. The LQDR (1Eh) register also provides a method of programming high and low thresholds for each of the four parameters that can be monitored. The register implements an indirect read/write mechanism. Writes are accomplished by writing data, address, and a write strobe to the register. Reads are accomplished by writing the address to the register, and reading back the value of the selected threshold. Setting thresholds to the maximum or minimum values will disable the threshold comparison since values have to exceed the threshold to generate a warning condition. Warnings are not generated if the parameter is equal to the threshold. By default, all thresholds are disabled by setting to the min or max values. The following table shows the four parameters and range of values: 45 www.national.com DP83849I 5.7.1.3 100MB Cable Length Estimation DP83849I Table 17. Link Quality Monitor Parameter Ranges Parameter Minimum Value Maximum Value Min (2-s comp) Max (2-s comp) -128 +127 0x80 0x7F DAGC 0 +255 0x00 0xFF DBLW -128 +127 0x80 0x7F Freq Offset -128 +127 0x80 0x7F Freq Control -128 +127 0x80 0x7F DEQ C1 5.7.3 TDR Cable Diagnostics The DP83849I implements a Time Domain Reflectometry (TDR) method of cable length measurement and evaluation which can be used to evaluate a connected twisted pair cable. The TDR implementation involves sending a pulse out on either the Transmit or Receive conductor pair and observing the results on either pair. By observing the types and strength of reflections on each pair, software can determine the following: -- -- -- -- -- Cable short Cable open Distance to fault Identify which pair has a fault Pair skew records the time, in 8ns intervals, at which the peak or threshold value first occurs. The TDR monitor implements a timer that starts when the pulse is transmitted. A window may be enabled to qualify incoming data to look for response only in a desired range. This is especially useful for eliminating the transmitted pulse, but also may be used to look for multiple reflections. 5.7.3.3 TDR Control Interface The TDR Control interface is implemented in the Link Diagnostics Registers - Page 2 through TDR Control (TDR_CTRL), address 16h and TDR Window (TDR_WIN), address 17h. The following basic controls are: The TDR cable diagnostics works best in certain conditions. For example, an unterminated cable provides a good reflection for measuring cable length, while a cable with an ideal termination to an unpowered partner may provide no reflection at all. -- TDR Enable: Enable bit 15 of TDR_CTRL (16h) to allow the TDR function. This bypasses normal operation and gives control of the CD10 and CD100 block to the TDR function. -- TDR Send Pulse: Enable bit 11 of TDR_CTRL (16h) to send the TDR pulse and starts the TDR Monitor. The following Transmit mode controls are available: -- Transmit Mode: Enables use of 10Mb Link pulses from the 10Mb Common Driver or data pulses from the 100Mb 5.7.3.1 TDR Pulse Generator Common Driver by enabling TDR 100Mb, bit 14 of TDR_CRTL (16h). The TDR implementation can send two types of TDR pulses. The first option is to send 50ns or 100ns link -- Transmit Pulse Width: Bits [10:8] of TDR_CTRL (16h) pulses from the 10Mb Common Driver. The second option allows sending of 0 to 7 clock width pulses. Actual pulsis to send pulses from the 100Mb Common Driver in 8ns es are dependent on the transmit mode. If Pulse Width increments up to 56ns in width. The 100Mb pulses will is set to 0, then no pulse will be sent. alternate between positive and negative pulses. The -- Transmit Channel Select: The transmitter can send shorter pulses provide better ability to measure short cable pulses down either the transmit pair or the receive pair lengths, especially since they will limit overlap between the by enabling bit 13 of TDR_CTRL (16h). Default value is transmitted pulse and a reflected pulse. The longer pulses to select the transmit pair. may provide better measurements of long cable lengths. In addition, if the pulse width is programmed to 0, no pulse will be sent, but monitor circuit will still be activated. This allows sampling of background data to provide a baseline for analysis. 5.7.3.2 TDR Pulse Monitor The TDR function monitors data from the Analog to Digital Converter (ADC) to detect both peak values and values above a programmable threshold. It can be programmed to detect maximum or minimum values. In addition, it www.national.com The following Receive mode controls are available: -- Min/Max Mode Select: Bit 7 of TDR_CTRL (16h) controls the TDR Monitor operation. In default mode, the monitor will detect maximum (positive) values. In Min mode, the monitor will detect minimum (negative) values. -- Receive Channel Select: The receiver can monitor either the transmit pair or the receive pair by enabling bit 12 of TDR_CTRL (16h). Default value is to select the transmit pair. 46 5.7.3.4 TDR Results The TDR function monitors data from the Analog to Digital Converter (ADC) to detect both peak values and values above a programmable threshold. It can be programmed to detect maximum or minimum values. In addition, it records the time, in 8ns intervals, at which the peak or threshold value first occurs. The results of a TDR peak and threshold measurement are available in the TDR Peak Measurement Register (TDR_PEAK), address 18h and TDR Threshold Measurement Register (TDR_THR), address 19h. The threshold measurement may be a more accurate method of measuring the length for longer cables to provide a better indication of the start of the received pulse, rather than the peak value. Software utilizing the TDR function should implement an algorithm to send TDR pulses and evaluate results. Multiple runs should be used to best qualify any received pulses as multiple reflections could exist. In addition, when monitoring the transmitting pair, the window feature should be used to disqualify the transmitted pulse. Multiple runs may also be used to average the values providing more accurate results. Actual distance measurements are dependent on the velocity of propagation of the cable. The delay value is typically on the order of 4.6 to 4.9 ns/m. 47 www.national.com DP83849I -- Receive Window: The receiver can monitor receive data within a programmable window using the TDR Window Register (TDR_WIN), address 17h. The window is controlled by two register values: TDR Start Window, bits [15:8] of TDR_WIN (17h) and TDR Stop Window, bits [7:0] of TDR_WIN (17h). The TDR Start Window indicates the first clock to start sampling. The TDR Stop Window indicates the last clock to sample. By default, the full window is enabled, with Start set to 0 and Stop set to 255. The window range is in 8ns clock increments, so the maximum window size is 2048ns. DP83849I 6.0 Reset Operation The DP83849I includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal operation, the device can be reset by a hardware or software reset. (BMCR). The period from the point in time when the reset bit is set to the point in time when software reset has concluded is approximately 1 s. The software reset will reset the device such that all registers will be reset to default values and the hardware configuration values will be maintained. Software driver code must wait 3 s following a software reset before allowing further serial MII operations with the DP83849I. 6.1 Hardware Reset A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 s, to the RESET_N pin. This will reset the device such that all registers will be reinitialized to default values and the hardware configuration values will be re-latched into the device (similar to the power-up/reset operation). 6.3 Soft Reset A partial software reset can be initiated by setting the Soft Reset bit (bit 9) in the PHYCR2 Register. Setting this bit will reset all transmit and receive operations, but will not reset the register space. All register configurations will be preserved. Register space will remain available following a Soft Reset. 6.2 Full Software Reset A full-chip software reset is accomplished by setting the reset bit (bit 15) of the Basic Mode Control Register www.national.com 48 DP83849I 7.0 Register Block Table 18. Register Map Offset Access Tag Description Hex Decimal 00h 0 RW BMCR Basic Mode Control Register 01h 1 RO BMSR Basic Mode Status Register 02h 2 RO PHYIDR1 PHY Identifier Register #1 03h 3 RO PHYIDR2 PHY Identifier Register #2 04h 4 RW ANAR Auto-Negotiation Advertisement Register 05h 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page) 05h 5 RW ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page) 06h 6 RW ANER Auto-Negotiation Expansion Register RW ANNPTR Auto-Negotiation Next Page TX RESERVED RESERVED 07h 7 08h-Fh 8-15 10h 16 RO PHYSTS PHY Status Register 11h 17 RW MICR MII Interrupt Control Register 12h 18 RW MISR MII Interrupt Status Register 13h 19 RW PAGESEL Page Select Register 14h 20 RO FCSCR False Carrier Sense Counter Register 15h 21 RO RECR Receive Error Counter Register 16h 22 RW PCSR PCS Sub-Layer Configuration and Status Register 17h 23 RW RBR RMII and Bypass Register 18h 24 RW LEDCR LED Direct Control Register Extended Registers - Page 0 19h 25 RW PHYCR PHY Control Register 1Ah 26 RW 10BTSCR 10Base-T Status/Control Register 1Bh 27 RW CDCTRL1 CD Test Control Register and BIST Extensions Register 1Ch 28 RW PHYCR2 Phy Control Register 2 RW 1Dh 29 EDCR Energy Detect Control Register 1Eh-1Fh 30-31 RESERVED RESERVED 14h-1Fh 30-31 RESERVED 14h 20 RO LEN100_DET 100Mb Length Detect Register 15h 21 RW FREQ100 100Mb Frequency Offset Indication Register 16h 22 RW TDR_CTRL TDR Control Register 17h 23 RW TDR_WIN TDR Window Register 18h 24 RO TDR_PEAK TDR Peak Measurement Register Reserved Registers RESERVED Link Diagnostics Registers - Page 2 19h 25 RO TDR_THR TDR Threshold Measurement Register 1Ah 26 RW VAR_CTRL Variance Control Register RO VAR_DAT Variance Data Register RESERVED RESERVED 1Bh 27 1Ch 28 1Dh 29 RW LQMR Link Quality Monitor Register 1Eh 30 RW LQDR Link Quality Data Register 1Fh 31 RESERVED RESERVED 49 www.national.com www.national.com 50 11h 12h 13h 14h 15h 16h MII Interrupt Control Register MII Interrupt Status and Misc. Control Register Page Select Register False Carrier Sense Counter Register Receive Error Counter Register PCS Sub-Layer Configuration and Status Register 06h Auto-Negotiation Expansion Register 10h 05h Auto-Negotiation Link Partner Ability Register Next Page PHY Status Register 05h Auto-Negotiation Link Partner Ability Register (Base Page) 08-0fh 04h Auto-Negotiation Advertisement Register RESERVED 03h PHY Identifier Register 2 07h 02h PHY Identifier Register 1 Auto-Negotiation Next Page TX Register 01h Basic Mode Status Register Addr 00h Register Name Basic Mode Control Register Tag Next Page Ind OUI LSB Reserved PCSR RECR FCSCR Reserved MISR MICR Reserved Reserved Reserved Reserved LQ_INT Reserved PHYSTS Reserved Reserved ANNPTR Next Page Ind Reserved ANNext LPARNP Page Ind ANER AutoNeg Enable 100Base 100Base 10BaseT -TX FDX -TX HDX FDX Speed Selection 10BaseT HDX Power Down Reserved Isolate Bit 9 Reserved Restart AutoNeg Bit 8 Reserved Duplex Mode Bit 7 Reserved Collision Test MF Preamble Suppress Reserved Bit 6 AutoNeg Complete Reserved Bit 5 Remote Fault Reserved Bit 4 AutoNeg Ability Reserved Bit 3 Link Status Reserved Bit 2 Jabber Detect Reserved Bit 1 Extended Capability Reserved Bit 0 Reserved Reserved Reserved Reserved ED_INT Reserved MDIX mode Reserved Reserved Reserved ACK ACK Reserved Reserved SPD_IN T Reserved Polarity Status Reserved ACK2 Reserved ACK2 Reserved Reserved Reserved DUP_IN T Reserved False Carrier Sense Reserved TOG_TX Reserved Toggle ASM_DI R ASM_DI R Reserved Reserved Reserved Reserved Reserved Reserved FREE_C LK Reserved Reserved Reserved Descrambler Lock Reserved CODE Reserved Code T4 T4 VNDR_ MDL Reserved Page Receive Reserved CODE Reserved Code TX_FD TX_FD VNDR_ MDL Reserved TQ_EN Reserved Reserved Reserved Reserved Reserved Reserved Remote Fault Reserved CODE Reserved Code 10_FD 10_FD VNDR_ MDL Reserved Jabber Detect Reserved CODE Reserved Code 10 10 VNDR_ MDL Reserved Reserved MDL_ REV MDL_ REV MDL_ REV MDL_ REV Reserved SPED_I NT_EN Reserved AutoNeg Complete Reserved CODE PDF Code Reserved DUP_IN T_EN Reserved Loopback Status Reserved CODE LP_NP_ ABLE Code INTEN Speed Status Reserved CODE PAGE_ RX Code INT_OE Link Status Reserved CODE LP_AN_ ABLE Code Reserved Page_Se Page_Se l Bit l Bit ANC_IN FHF_INT RHF_IN T_EN _EN T_EN TINT Duplex Status Reserved CODE NP_ ABLE Code Protocol Protocol Protocol Protocol Protocol Selection Selection Selection Selection Selection Protocol Protocol Protocol Protocol Protocol Selection Selection Selection Selection Selection VNDR_ MDL RXERCNT Reserved RXERCNT FORCE_ 100_OK RXERCNT Reserved RXERCNT Reserved RXERCNT NRZI_ BYPASS RXERCNT Reserved RXERCNT Reserved RXERCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT Reserved LQ_INT_ ED_INT_ LINK_IN EN EN T_EN Reserved MII Interrupt Reserved CODE Reserved Code TX TX VNDR_ MDL SD_FOR SD_ DESC_T CE_PMA OPTION IME Reserved Reserved Reserved ANC_IN FHF_INT RHF_IN T T Reserved Signal Detect Reserved CODE Reserved Code PAUSE PAUSE EXTENDED REGISTERS Reserved LINK_IN T Reserved Rx Err Latch Reserved Message Page Reserved Message Page Remote Fault Remote Fault OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB 100Base -T4 Loopback Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Reset ANLPAR Next Page Ind ANAR PHYIDR 2 PHYIDR 1 BMSR BMCR Table 19. Register Table DP83849I www.national.com 1Eh-1Fh 14h-1Fh 14h 15h 16h 17h 18h 19h RESERVED RESERVED 100Mb Length Detect Register 100Mb Frequency Offset Indication Register TDR Control Register TDR Window Register TDR Peak Register TDR Threshold Register 1Ch 1Dh Energy Detect Control Register RESERVED 1Ch Phy Control Register 2 1Bh 1Bh CD Test Control and BIST Extensions Register Variance Data Register 1Ah 10Base-T Status/Control Register 1Ah 19h PHY Control Register Variance Control Register 18h LED Direct Control Register Addr 17h Register Name RMII and Bypass Register Tag Reserved MDIX_E N Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 8 Reserved Reserved ED_EN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESERVED REGISTERS Reserved TDR_10 0Mb Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TX_CHA RX_CHA SEND_T TDR_WI NNEL NNEL DR DTH Reserved Reserved Bit 5 RMII_M ODE Bit 3 Bit 2 Bit 1 Bit 0 ELAST_ BUF Reserved Reserved Reserved LP_DIS Reserved Reserved FORCE_ LINK_10 Reserved BIST_C ONT_M ODE Reserved Reserved CDPattE N_10 POLARITY PHY ADDR Reserved Reserved Reserved PHY ADDR Reserved 10Meg_ Patt_Ga p Reserved PHY ADDR PHY ADDR Reserved CDPattSel Reserved CDPattSel HEARTB JABBER EAT_DIS _DIS PHY ADDR Reserved Reserved Reserved Reserved TDR_WI DTH Reserved Reserved CABLE_ LEN CABLE_ LEN Reserved Reserved Reserved Reserved CABLE_ CABLE_ LEN LEN Reserved Reserved CABLE_ LEN Reserved Reserved CABLE_ LEN Reserved Reserved Reserved Reserved CABLE_ CABLE_ LEN LEN Reserved Reserved TDR_WI DTH TDR_MI N_MOD E Reserved RX_THR RX_THR RX_THR RX_THR RX_THR RX_THR ESHOLD ESHOLD ESHOLD ESHOLD ESHOLD ESHOLD SEL_FC FREQ_O FREQ_O FREQ_O FREQ_O FREQ_O FREQ_O FREQ_O FREQ_O FFSET FFSET FFSET FFSET FFSET FFSET FFSET FFSET Reserved Reserved Reserved ED_ERR ED_DAT ED_ERR ED_ERR ED_ERR ED_ERR ED_DAT ED_DAT ED_DAT ED_DAT _MET A_MET _COUNT _COUNT _COUNT _COUNT A_COUN A_COUN A_COUN A_COUN T T T T SOFT_R ESET Bit 4 RMII_RE RX_OVF RX_UNF ELAST_ V1_0 _STS _STS BUF LEDACT BLINK_F BLINK_F DRV_SP DRV_LN DRV_AC SPDLED LNKLED ACTLED _RX REQ REQ DLED KLED TLED LINK DIAGNOSTICS REGISTERS - PAGE 2 Reserved Reserved ED_AUT ED_AUT ED_MAN ED_BUR ED_PW O_UP O_DOW ST_DIS R_STAT N E Reserved Bit 6 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TDR_TH R_MET Reserved TDRTHR_TI ME Reserved TDRTHR_TI ME Reserved TDRTHR_TI ME Reserved TDRTHR_TI ME VAR_FR EEZE TDRTHR_TI ME VAR_TI MER TDRTHR_TI ME VAR_TI MER TDRTHR_TI ME VAR_TI MER TDRTHR_TI ME TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE TDR_PE AK AK AK AK AK AK AK_TIM AK_TIM AK_TIM AK_TIM AK_TIM AK_TIM AK_TIM AK_TIM E E E E E E E E Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA VAR_DA TA TA TAT TA TA TA TAT TA TA TA TAT TA TA TA TAT TA TA VAR_CT VAR_RD RL Y TDR_TH ReR served TDR_PE ReAK served TDR_WI TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST TDR_ST N ART ART ART ART ART ART ART ART OP OP OP OP OP OP OP OP TDR_CT TDR_EN RL ABLE FREQ10 SAMPLE 0 _FREQ LEN100_ ReDET served Reserved Reserved EDCR PHYCR2 Reserved Bit 7 BIST_ BIST_ST BP_STR LED_ LED_ STATUS ART ETCH CNFG[1] CNFG[0] Reserved SQUELC SQUELC SQUELC LOOPBA H H H CK_10_ DIS FORCE_ PAUSE_ PAUSE_ BIST_FE PSR_15 MDIX RX TX Reserved Bit 9 DIS_TX_ RX_POR RX_POR TX_SOU TX_SOU PMD_LO SCMII_R SCMII_T OPT T T RCE RCE OP X X Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 SIM_WR ReITE served CDCTRL BIST_ER BIST_ER BIST_ER BIST_ER BIST_ER BIST_ER BIST_ER BIST_ER 1 ROR_C ROR_C ROR_C ROR_C ROR_C ROR_C ROR_C ROR_C OUNT OUNT OUNT OUNT OUNT OUNT OUNT OUNT 10BT_S ERIAL PHYCR LEDCR RBR Table 19. Register Table DP83849I 51 www.national.com 52 1Eh 1Fh Link Quality Data Register RESERVED Addr 1Dh Register Name Link Quality Monitor Register Tag Reserved LQDR LQMR Reserved Reserved LQM_EN ABLE Reserved Reserved Reserved Reserved Reserved Reserved Bit 9 FC_HI_ WARN Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FC_LO_ FREQ_H FREQ_L DBLW_H DBLW_L DAGC_H DAGC_L WARN I_WARN O_WAR I_WARN O_WAR I_WARN O_WAR N N N Bit 1 C1_HI_ WARN Bit 0 C1_LO_ WARN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SAMPLE WRITE_ LQ_PAR LQ_PAR LQ_PAR LQ_THR LQ_THR LQ_THR LQ_THR LQ_THR LQ_THR LQ_THR LQ_THR LQ_THR _PARAM LQ_THR AM_SEL AM_SEL AM_SEL _SEL _DATA _DATA _DATA _DATA _DATA _DATA _DATA _DATA Reserved Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Table 19. Register Table DP83849I DP83849I 7.1 Register Definition In the register definitions under the `Default' heading, the following definitions hold true: -- RW=Read Write access -- -- -- -- -- -- -- -- SC=Register sets on event occurrence and Self-Clears when event ends RW/SC =Read Write access/Self Clearing bit RO=Read Only access COR = Clear on Read RO/COR=Read Only, Clear on Read RO/P=Read Only, Permanently set to a default value LL=Latched Low and held until read, based upon the occurrence of the corresponding event LH=Latched High and held until read, based upon the occurrence of the corresponding event 53 www.national.com DP83849I 7.1.1 Basic Mode Control Register (BMCR) Table 20. Basic Mode Control Register (BMCR), address 00h Bit Bit Name Default 15 RESET 0, RW/SC Description Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is re-strapped. 14 LOOPBACK 0, RW Loopback: 1 = Loopback enabled. 0 = Normal operation. The loopback function enables MII transmit data to be routed to the MII receive data path. Setting this bit may cause the descrambler to lose synchronization and produce a 500 s "dead time" before any valid data will appear at the MII receive outputs. 13 SPEED SELECTION Strap, RW Speed Select: When auto-negotiation is disabled writing to this bit allows the port speed to be selected. 1 = 100 Mb/s. 0 = 10 Mb/s. 12 AUTO-NEGOTIATION ENABLE Strap, RW Auto-Negotiation Enable: Strap controls initial value at reset. 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set. 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. 11 POWER DOWN 0, RW Power Down: 1 = Power down. 0 = Normal operation. Setting this bit powers down the PHY. Only the register block is enabled during a power down condition. This bit is OR'd with the input from the PWRDOWN_INT pin. When the active low PWRDOWN_INT pin is asserted, this bit will be set. 10 ISOLATE 0, RW Isolate: 1 = Isolates the Port from the MII with the exception of the serial management. 0 = Normal operation. 9 RESTART AUTO-NEGOTIATION 0, RW/SC Restart Auto-Negotiation: 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is selfclearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 0 = Normal operation. 8 DUPLEX MODE Strap, RW Duplex Mode: When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected. 1 = Full Duplex operation. 0 = Half Duplex operation. www.national.com 54 DP83849I Table 20. Basic Mode Control Register (BMCR), address 00h (Continued) Bit Bit Name Default 7 COLLISION TEST 0, RW Description Collision Test: 1 = Collision test enabled. 0 = Normal operation. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512-bit times. The COL signal will be de-asserted within 4-bit times in response to the de-assertion of TX_EN. 6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0. 55 www.national.com DP83849I 7.1.2 Basic Mode Status Register (BMSR) Table 21. Basic Mode Status Register (BMSR), address 01h Bit Bit Name Default 15 100BASE-T4 0, RO/P Description 100BASE-T4 Capable: 0 = Device not able to perform 100BASE-T4 mode. 14 100BASE-TX 1, RO/P FULL DUPLEX 13 100BASE-TX 1 = Device able to perform 100BASE-TX in full duplex mode. 1, RO/P HALF DUPLEX 12 10BASE-T 10BASE-T 100BASE-TX Half Duplex Capable: 1 = Device able to perform 100BASE-TX in half duplex mode. 1, RO/P FULL DUPLEX 11 100BASE-TX Full Duplex Capable: 10BASE-T Full Duplex Capable: 1 = Device able to perform 10BASE-T in full duplex mode. 1, RO/P HALF DUPLEX 10BASE-T Half Duplex Capable: 1 = Device able to perform 10BASE-T in half duplex mode. 10:7 RESERVED 0, RO RESERVED: Write as 0, read as 0. 6 MF PREAMBLE 1, RO/P Preamble suppression Capable: SUPPRESSION 1 = Device able to perform management transaction with preamble suppressed, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround. 0 = Normal management operation. 5 AUTO-NEGOTIATION COMPLETE 0, RO Auto-Negotiation Complete: 1 = Auto-Negotiation process complete. 0 = Auto-Negotiation process not complete. 4 REMOTE FAULT 0, RO/LH Remote Fault: 1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End Fault Indication or notification from Link Partner of Remote Fault. 0 = No remote fault condition detected. 3 AUTO-NEGOTIATION ABILITY 1, RO/P Auto Negotiation Ability: 1 = Device is able to perform Auto-Negotiation. 0 = Device is not able to perform Auto-Negotiation. 2 LINK STATUS 0, RO/LL Link Status: 1 = Valid link established (for either 10 or 100 Mb/s operation). 0 = Link not established. The criteria for link validity is implementation specific. The occurrence of a link failure condition will causes the Link Status bit to clear. Once cleared, this bit may only be set by establishing a good link condition and a read via the management interface. 1 JABBER DETECT 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode. 1 = Jabber condition detected. 0 = No Jabber. This bit is implemented with a latching function, such that the occurrence of a jabber condition causes it to set until it is cleared by a read to this register by the management interface or by a reset. 0 EXTENDED CAPABILITY 1, RO/P Extended Capability: 1 = Extended register capabilities. 0 = Basic register set capabilities only. www.national.com 56 7.1.3 PHY Identifier Register #1 (PHYIDR1) Table 22. PHY Identifier Register #1 (PHYIDR1), address 02h Bit Bit Name 15:0 OUI_MSB Default Description <0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are 0000>, RO/P stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). 7.1.4 PHY Identifier Register #2 (PHYIDR2) Table 23. PHY Identifier Register #2 (PHYIDR2), address 03h Bit Bit Name 15:10 OUI_LSB Default Description <0101 11>, RO/P OUI Least Significant Bits: Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register respectively. 9:4 VNDR_MDL <00 1010>, RO/P Vendor Model Number: The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9). 3:0 MDL_REV <0010>, RO/P Model Revision Number: Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant bit to bit 3). This field will be incremented for all major device changes. 7.1.5 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a renegotiation. This will ensure that the new values are properly used in the Auto-Negotiation. Table 24. Negotiation Advertisement Register (ANAR), address 04h Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = Next Page Transfer not desired. 1 = Next Page Transfer desired. 14 RESERVED 0, RO/P 13 RF 0, RW RESERVED by IEEE: Writes ignored, Read as 0. Remote Fault: 1 = Advertises that this device has detected a Remote Fault. 0 = No Remote Fault detected. 12 RESERVED 0, RW RESERVED for Future IEEE use: Write as 0, Read as 0 57 www.national.com DP83849I The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83849I. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National's IEEE assigned OUI is 080017h. DP83849I Table 24. Negotiation Advertisement Register (ANAR), address 04h (Continued) Bit Bit Name Default 11 ASM_DIR 0, RW Description Asymmetric PAUSE Support for Full Duplex Links: The ASM_DIR bit indicates that asymmetric PAUSE is supported. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u. 0= No MAC based full duplex flow control. 10 PAUSE 0, RW PAUSE Support for Full Duplex Links: The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE functions as defined in Annex 31B. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u. 0= No MAC based full duplex flow control. 9 T4 0, RO/P 100BASE-T4 Support: 1= 100BASE-T4 is supported by the local device. 0 = 100BASE-T4 not supported. 8 TX_FD Strap, RW 100BASE-TX Full Duplex Support: 1 = 100BASE-TX Full Duplex is supported by the local device. 0 = 100BASE-TX Full Duplex not supported. 7 TX Strap, RW 100BASE-TX Support: 1 = 100BASE-TX is supported by the local device. 0 = 100BASE-TX not supported. 6 10_FD Strap, RW 10BASE-T Full Duplex Support: 1 = 10BASE-T Full Duplex is supported by the local device. 0 = 10BASE-T Full Duplex not supported. 5 10 Strap, RW 10BASE-T Support: 1 = 10BASE-T is supported by the local device. 0 = 10BASE-T not supported. 4:0 SELECTOR <00001>, RW Protocol Selection Bits: These bits contain the binary encoded protocol selector supported by this port. <00001> indicates that this device supports IEEE 802.3u. www.national.com 58 This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 25. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 05h Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 0 = Link Partner does not desire Next Page Transfer. 1 = Link Partner desires Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged. The Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts. 13 RF 0, RO Remote Fault: 1 = Remote Fault indicated by Link Partner. 0 = No Remote Fault indicated by Link Partner. 12 RESERVED 0, RO RESERVED for Future IEEE use: Write as 0, read as 0. 11 ASM_DIR 0, RO ASYMMETRIC PAUSE: 1 = Asymmetric pause is supported by the Link Partner. 0 = Asymmetric pause is not supported by the Link Partner. 10 PAUSE 0, RO PAUSE: 1 = Pause function is supported by the Link Partner. 0 = Pause function is not supported by the Link Partner. 9 T4 0, RO 100BASE-T4 Support: 1 = 100BASE-T4 is supported by the Link Partner. 0 = 100BASE-T4 not supported by the Link Partner. 8 TX_FD 0, RO 100BASE-TX Full Duplex Support: 1 = 100BASE-TX Full Duplex is supported by the Link Partner. 0 = 100BASE-TX Full Duplex not supported by the Link Partner. 7 TX 0, RO 100BASE-TX Support: 1 = 100BASE-TX is supported by the Link Partner. 0 = 100BASE-TX not supported by the Link Partner. 6 10_FD 0, RO 10BASE-T Full Duplex Support: 1 = 10BASE-T Full Duplex is supported by the Link Partner. 0 = 10BASE-T Full Duplex not supported by the Link Partner. 5 10 0, RO 10BASE-T Support: 1 = 10BASE-T is supported by the Link Partner. 0 = 10BASE-T not supported by the Link Partner. 4:0 SELECTOR <0 0000>, RO Protocol Selection Bits: Link Partner's binary encoded protocol selector. 59 www.national.com DP83849I 7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) DP83849I 7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 26. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 05h Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged. The Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts. Software should not attempt to write to this bit. 13 MP 0, RO Message Page: 1 = Message Page. 0 = Unformatted Page. 12 ACK2 0, RO Acknowledge 2: 1 = Link Partner does have the ability to comply to next page message. 0 = Link Partner does not have the ability to comply to next page message. 11 TOGGLE 0, RO Toggle: 1 = Previous value of the transmitted Link Code word equalled 0. 0 = Previous value of the transmitted Link Code word equalled 1. 10:0 www.national.com CODE <000 0000 0000>, Code: RO This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code shall be interpreted as a "Message Page," as defined in annex 28C of Clause 28. Otherwise, the code shall be interpreted as an "Unformatted Page," and the interpretation is application specific. 60 DP83849I 7.1.8 Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. Table 27. Auto-Negotiate Expansion Register (ANER), address 06h Bit Bit Name Default Description 15:5 RESERVED 0, RO RESERVED: Writes ignored, Read as 0. 4 PDF 0, RO Parallel Detection Fault: 1 = A fault has been detected via the Parallel Detection function. 0 = A fault has not been detected. 3 LP_NP_ABLE 0, RO Link Partner Next Page Able: 1 = Link Partner does support Next Page. 0 = Link Partner does not support Next Page. 2 NP_ABLE 1, RO/P 1 PAGE_RX 0, RO/COR Next Page Able: 1 = Indicates local device is able to send additional "Next Pages". Link Code Word Page Received: 1 = Link Code Word has been received, cleared on a read. 0 = Link Code Word has not been received. 0 LP_AN_ABLE 0, RO Link Partner Auto-Negotiation Able: 1 = indicates that the Link Partner supports Auto-Negotiation. 0 = indicates that the Link Partner does not support Auto-Negotiation. 61 www.national.com DP83849I 7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 28. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 07h Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = No other Next Page Transfer desired. 1 = Another Next Page desired. 14 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 13 MP 1, RW Message Page: 1 = Message Page. 0 = Unformatted Page. 12 ACK2 0, RW Acknowledge2: 1 = Will comply with message. 0 = Cannot comply with message. Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received. 11 TOG_TX 0, RO Toggle: 1 = Value of toggle bit in previously transmitted Link Code Word was 0. 0 = Value of toggle bit in previously transmitted Link Code Word was 1. Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization with the Link Partner during Next Page exchange. This bit shall always take the opposite value of the Toggle bit in the previously exchanged Link Code Word. 10:0 CODE <000 0000 0001>, Code: RW This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code shall be interpreted as a "Message Page", as defined in annex 28C of IEEE 802.3u. Otherwise, the code shall be interpreted as an "Unformatted Page", and the interpretation is application specific. The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u. www.national.com 62 This register provides a single location within the register set for quick access to commonly accessed information. Table 29. PHY Status Register (PHYSTS), address 10h Bit Bit Name Default Description 15 RESERVED 0, RO RESERVED: Write ignored, read as 0. 14 MDIX MODE 0, RO MDIX mode as reported by the Auto-Negotiation logic: This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the PHYCR register. When MDIX is enabled, but not forced, this bit will update dynamically as the Auto-MDIX algorithm swaps between MDI and MDIX configurations. 1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair) 0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair) 13 RECEIVE ERROR LATCH 0, RO/LH Receive Error Latch: This bit will be cleared upon a read of the RECR register. 1 = Receive error event has occurred since last read of RXERCNT (address 15h, Page 0). 0 = No receive error event has occurred. 12 POLARITY STATUS 0, RO Polarity Status: This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared upon a read of the 10BTSCR register, but not upon a read of the PHYSTS register. 1 = Inverted Polarity detected. 0 = Correct Polarity detected. 11 FALSE CARRIER SENSE LATCH 0, RO/LH False Carrier Sense Latch: This bit will be cleared upon a read of the FCSR register. 1 = False Carrier event has occurred since last read of FCSCR (address 14h). 0 = No False Carrier event has occurred. 10 SIGNAL DETECT 0, RO/LL 100Base-TX qualified Signal Detect from PMA: This is the SD that goes into the link monitor. It is the AND of raw SD and descrambler lock, when address 16h, bit 8 (page 0) is set. When this bit is cleared, it will be equivalent to the raw SD from the PMD. 9 DESCRAMBLER LOCK 0, RO/LL 8 PAGE RECEIVED 0, RO 100Base-TX Descrambler Lock from PMD. Link Code Word Page Received: This is a duplicate of the Page Received bit in the ANER register, but this bit will not be cleared upon a read of the PHYSTS register. 1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address 06h, bit 1). 0 = Link Code Word Page has not been received. 7 MII INTERRUPT 0, RO MII Interrupt Pending: 1 = Indicates that an internal interrupt is pending. Interrupt source can be determined by reading the MISR Register (12h). Reading the MISR will clear the Interrupt. 0 = No interrupt pending. 63 www.national.com DP83849I 7.1.10 PHY Status Register (PHYSTS) DP83849I Table 29. PHY Status Register (PHYSTS), address 10h Bit Bit Name Default 6 REMOTE FAULT 0, RO Description Remote Fault: 1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation. 0 = No remote fault condition detected. 5 JABBER DETECT 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not cleared upon a read of the PHYSTS register. 1 = Jabber condition detected. 0 = No Jabber. 4 AUTO-NEG COMPLETE 0, RO Auto-Negotiation Complete: 1 = Auto-Negotiation complete. 0 = Auto-Negotiation not complete. 3 LOOPBACK STATUS 0, RO Loopback: 1 = Loopback enabled. 0 = Normal operation. 2 DUPLEX STATUS 0, RO Duplex: This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. 1 = Full duplex mode. 0 = Half duplex mode. Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link. 1 SPEED STATUS 0, RO Speed10: This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced Modes. 1 = 10 Mb/s mode. 0 = 100 Mb/s mode. Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link. 0 LINK STATUS 0, RO Link Status: This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be cleared upon a read of the PHYSTS register. 1 = Valid link established (for either 10 or 100 Mb/s operation) 0 = Link not established. www.national.com 64 This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII Interrupt Status and Event Control Register (MISR). Table 30. MII Interrupt Control Register (MICR), address 11h Bit Bit Name Default 15:3 RESERVED 0, RO RESERVED: Writes ignored, read as 0. Description 2 TINT 0, RW Test Interrupt: Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be generated as long as this bit remains set. 1 = Generate an interrupt 0 = Do not generate interrupt 1 INTEN 0, RW Interrupt Enable: Enable interrupt dependent on the event enables in the MISR register. 1 = Enable event based interrupts 0 = Disable event based interrupts 0 INT_OE 0, RW Interrupt Output Enable: Enable interrupt events to signal via the PWRDOWN_INT pin by configuring the PWRDOWN_INT pin as an output. 1 = PWRDOWN_INT is an Interrupt Output 0 = PWRDOWN_INT is a Power Down Input 7.1.12 MII Interrupt Status and Misc. Control Register (MISR) This register contains event status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The MICR register controls must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled. Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h 15 LQ_INT 0, RO/COR Link Quality interrupt: 1 = Link Quality interrupt is pending and is cleared by the current read. 0 = No Link Quality interrupt pending. 14 ED_INT 0, RO/COR Energy Detect interrupt: 1 = Energy detect interrupt is pending and is cleared by the current read. 0 = No energy detect interrupt pending. 13 LINK_INT 0, RO/COR Change of Link Status interrupt: 1 = Change of link status interrupt is pending and is cleared by the current read. 0 = No change of link status interrupt pending. 12 SPD_INT 0, RO/COR Change of speed status interrupt: 1 = Speed status change interrupt is pending and is cleared by the current read. 0 = No speed status change interrupt pending. 65 www.national.com DP83849I 7.1.11 MII Interrupt Control Register (MICR) DP83849I Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h 11 DUP_INT 0, RO/COR Change of duplex status interrupt: 1 = Duplex status change interrupt is pending and is cleared by the current read. 0 = No duplex status change interrupt pending. 10 ANC_INT 0, RO/COR Auto-Negotiation Complete interrupt: 1 = Auto-negotiation complete interrupt is pending and is cleared by the current read. 0 = No Auto-negotiation complete interrupt pending. 9 FHF_INT 0, RO/COR False Carrier Counter half-full interrupt: 1 = False carrier counter half-full interrupt is pending and is cleared by the current read. 0 = No false carrier counter half-full interrupt pending. 8 RHF_INT 0, RO/COR Receive Error Counter half-full interrupt: 1 = Receive error counter half-full interrupt is pending and is cleared by the current read. 0 = No receive error carrier counter half-full interrupt pending. 7 LQ_INT_EN 0, RW Enable Interrupt on Link Quality Monitor event 6 ED_INT_EN 0, RW Enable Interrupt on energy detect event 5 LINK_INT_EN 0, RW Enable Interrupt on change of link status 4 SPD_INT_EN 0, RW Enable Interrupt on change of speed status 3 DUP_INT_EN 0, RW Enable Interrupt on change of duplex status 2 ANC_INT_EN 0, RW Enable Interrupt on Auto-negotiation complete event 1 FHF_INT_EN 0, RW Enable Interrupt on False Carrier Counter Register half-full event 0 RHF_INT_EN 0, RW Enable Interrupt on Receive Error Counter Register half-full event 7.1.13 Page Select Register (PAGESEL) This register is used to enable access to the Link Diagnostics Registers. Table 32. Page Select Register (PAGESEL), address 13h Bit Bit Name Default 15:2 RESERVED 0, RO RESERVED: Writes ignored, Read as 0 Description 1:0 PAGE_SEL 0, RW Page_Sel Bit: Selects between paged registers for address 14h to 1Fh. 0 = Extended Registers Page 0 1 = Test Mode Register Page 1 2 = Link Diagnostics Registers Page 2 www.national.com 66 7.2.1 False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the "False Carriers" attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 33. False Carrier Sense Counter Register (FCSCR), address 14h Bit Bit Name Default 15:8 RESERVED 0, RO 7:0 FCSCNT[7:0] 0, RO/COR Description RESERVED: Writes ignored, Read as 0 False Carrier Event Counter: This 8-bit counter increments on every false carrier event. This counter sticks when it reaches its max count (FFh). 7.2.2 Receiver Error Counter Register (RECR) This counter provides information required to implement the "Symbol Error During Carrier" attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification. Table 34. Receiver Error Counter Register (RECR), address 15h Bit Bit Name Default 15:8 RESERVED 0, RO 7:0 RXERCNT[7:0] 0, RO/COR Description RESERVED: Writes ignored, Read as 0 RX_ER Counter: When a valid carrier is present and there is at least one occurrence of an invalid data symbol, this 8-bit counter increments for each receive error detected. This event can increment only once per valid carrier event. If a collision is present, the attribute will not increment. The counter sticks when it reaches its max count. 7.2.3 100 Mb/s PCS Configuration and Status Register (PCSR) This register contains control and status information for the 100BASE Physical Coding Sublayer. Table 35. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h Bit Bit Name Default 15:12 RESERVED <00>, RO 11 FREE_CLK 0, RW Description RESERVED: Writes ignored, Read as 0. Receive Clock: 1 = RX_CLK is free-running 0 = RX_CLK phase adjusted based on alignment 10 TQ_EN 0, RW 100Mbs True Quiet Mode Enable: 1 = Transmit True Quiet Mode. 0 = Normal Transmit Mode. 9 SD FORCE PMA 0, RW Signal Detect Force PMA: 1 = Forces Signal Detection in PMA. 0 = Normal SD operation. 67 www.national.com DP83849I 7.2 Extended Registers - Page 0 DP83849I Table 35. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h (Continued) Bit Bit Name Default 8 SD_OPTION 1, RW Description Signal Detect Option: 1 = Default operation. Link will be asserted following detection of valid signal level and Descrambler Lock. Link will be maintained as long as signal level is valid. A loss of Descrambler Lock will not cause Link Status to drop. 0 = Modified signal detect algorithm. Link will be asserted following detection of valid signal level and Descrambler Lock. Link will be maintained as long as signal level is valid and Descrambler remains locked. 7 DESC_TIME 0, RW Descrambler Timeout: Increase the descrambler timeout. When set this should allow the device to receive larger packets (>9k bytes) without loss of synchronization. 1 = 2ms 0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e) 6 RESERVED 0 RESERVED: Must be zero. 5 FORCE_100_OK 0, RW Force 100Mb/s Good Link: 1 = Forces 100Mb/s Good Link. 0 = Normal 100Mb/s operation. 4:3 RESERVED 0 RESERVED: Must be zero. 2 NRZI_BYPASS 0, RW NRZI Bypass Enable: 1 = NRZI Bypass Enabled. 0 = NRZI Bypass Disabled. 1:0 RESERVED 0 RESERVED: Must be zero. www.national.com 68 This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII, RMII, or Single Clock MII mode for Receive or Transmit. In addition, several additional bits are included to allow datapath selection for Transmit and Receive in multiport applications. Table 36. RMII and Bypass Register (RBR), addresses 17h Bit Bit Name Default 15 SIM_WRITE 0, RW Description Simultaneous Write: Setting this bit in port A register space enables simultaneous write to Phy registers in both ports. Subsequent writes to port A registers will write to registers in both ports A and B. 1 = Simultaneous writes to both ports 0 = Per-port write 14 RESERVED 0, RO RESERVED: Writes ignored, Read as 0 13 DIS_TX_OPT 0, RW Disable RMII TX Latency Optimization: Normally the RMII Transmitter will minimize the transmit latency by realigning the transmit clock with the Reference clock phase at the start of a packet transmission. Setting this bit will disable Phase realignment and ensure that IDLE bits will always be sent in multiples of the symbol size. This will result in a larger uncertainty in RMII transmit latency. 12:11 RX_PORT 00, RW Receive Port: See Section 3.5 for more information on Flexible Port Switching. 10:9 TX_SOURCE Strap, RW Transmit Source: See Section 3.5 for more information on Flexible Port Switching. 00 = Not strapped for Extender Mode 10 = Strapped for Extender Mode 8 PMD_LOOP 0, RW PMD Loopback: 0= Normal Operation 1= Remote (PMD) Loopback Setting this bit will cause the device to Loopback data received from the Physical Layer. The loopback is done prior to the MII or RMII interface. Data received at the internal MII or RMII interface will be applied to the transmitter. This mode should only be used if RMII mode or Single Clock MII mode is enabled. 7 SCMII_RX Strap, RW Single Clock RX MII Mode: 0= Standard MII mode 1= Single Clock RX MII Mode Setting this bit will cause the device to generate receive data (RX_DV, RX_ER, RXD[3:0]) synchronous to the X1 Reference clock. RX_CLK is not used in this mode. This mode uses the RMII elasticity buffer to tolerate variations in clock frequencies. This bit cannot be set if RMII_MODE is set to a 1. This bit is strapped to 1 if EXTENDER_EN is 1 and RMII Mode is not strapped at hard reset. 6 SCMII_TX Strap, RW Single Clock TX MII Mode: 0= Standard MII mode 1= Single Clock TX MII Mode Setting this bit will cause the device to sample transmit data (TX_EN, TXD[3:0]) synchronous to the X1 Reference clock. TX_CLK is not used in this mode. This bit cannot be set if RMII_MODE is set to a 1. This bit is strapped to 1 if EXTENDER_EN is 1 and RMII Mode is not strapped at hard reset. 69 www.national.com DP83849I 7.2.4 RMII and Bypass Register (RBR) DP83849I Table 36. RMII and Bypass Register (RBR), addresses 17h (Continued) Bit Bit Name Default 5 RMII_MODE Strap, RW Description Reduced MII Mode: 0 = Standard MII Mode 1 = Reduced MII Mode 4 RMII_REV1_0 0, RW Reduced MII Revision 1.0: 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of CRS. 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet. 3 RX_OVF_STS 0, RO/COR RX FIFO Over Flow Status: 0 = Normal 1 = Overflow detected 2 RX_UNF_STS 0, RO/COR RX FIFO Under Flow Status: 0 = Normal 1 = Underflow detected 1:0 ELAST_BUF[1:0] 01, RW Receive Elasticity Buffer: This field controls the Receive Elasticity Buffer which allows for frequency variation tolerance between the 50MHz RMII clock and the recovered data. See Section 3.2 for more information on Elasticity Buffer settings in RMII mode. See Section 3.4 for more information on Elasticity Buffer settings in SCMII mode. www.national.com 70 This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs. In addition, it provides control for the Activity source and blinking LED frequency. Table 37. LED Direct Control Register (LEDCR), address 18h Bit Bit Name Default Description 15:9 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 8 LEDACT_RX 0, RW 1 = Activity is only indicated for Receive traffic 0 = Activity is indicated for Transmit or Receive traffic 7:6 BLINK_FREQ 00, RW LED Blink Frequency These bits control the blink frequency of the LED_LINK output when blinking on activity is enabled. 0 = 6Hz 1 = 12Hz 2 = 24Hz 3 = 48Hz 5 DRV_SPDLED 0, RW 1 = Drive value of SPDLED bit onto LED_SPEED output 0 = Normal operation 4 DRV_LNKLED 0, RW 1 = Drive value of LNKLED bit onto LED_LINK output 0 = Normal operation 3 DRV_ACTLED 0, RW 1 = Drive value of ACTLED bit onto LED_ACT/LED_COL output 0 = Normal operation 2 SPDLED 0, RW Value to force on LED_SPEED output 1 LNKLED 0, RW Value to force on LED_LINK output 0 ACTLED 0, RW Value to force on LED_ACT/LED_COL output 71 www.national.com DP83849I 7.2.5 LED Direct Control Register (LEDCR) DP83849I 7.2.6 PHY Control Register (PHYCR) This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause Negotiation status. Table 38. PHY Control Register (PHYCR), address 19h Bit Bit Name Default 15 MDIX_EN Strap, RW Description Auto-MDIX Enable: 1 = Enable Auto-neg Auto-MDIX capability. 0 = Disable Auto-neg Auto-MDIX capability. The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register to be set. If Auto-Negotiation is not enabled, Auto-MDIX should be disabled as well. 14 FORCE_MDIX 0, RW Force MDIX: 1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair) 0 = Normal operation. 13 PAUSE_RX 0, RO Pause Receive Negotiated: Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10] and ANLPAR[11:10] settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, "Pause Resolution", only if the Auto-Negotiated Highest Common Denominator is a full duplex technology. 12 PAUSE_TX 0, RO Pause Transmit Negotiated: Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10] and ANLPAR[11:10] settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, "Pause Resolution", only if the Auto-Negotiated Highest Common Denominator is a full duplex technology. 11 BIST_FE 0, RW/SC BIST Force Error: 1 = Force BIST Error. 0 = Normal operation. This bit forces a single error, and is self clearing. 10 PSR_15 0, RW BIST Sequence select: 1 = PSR15 selected. 0 = PSR9 selected. 9 BIST_STATUS 0, LL/RO BIST Test Status: 1 = BIST pass. 0 = BIST fail. Latched, cleared when BIST is stopped. For a count number of BIST errors, see the BIST Error Count in the CDCTRL1 register. 8 BIST_START 0, RW BIST Start: 1 = BIST start. 0 = BIST stop. 7 BP_STRETCH 0, RW Bypass LED Stretching: This will bypass the LED stretching and the LEDs will reflect the internal value. 1 = Bypass LED stretching. 0 = Normal operation. www.national.com 72 DP83849I Table 38. PHY Control Register (PHYCR), address 19h (Continued) Bit Bit Name Default 6 LED_CNFG[1] 0, RW 5 LED_CNFG[0] Strap, RW Description LED Configuration LED_CNFG[1] Don't care 0 1 LED_ CNFG[0] 1 0 0 Mode Description Mode 1 Mode 2 Mode 3 In Mode 1, LEDs are configured as follows: LED_LINK = ON for Good Link, OFF for No Link LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s LED_ACT/LED_COL = ON for Activity, OFF for No Activity In Mode 2, LEDs are configured as follows: LED_LINK = ON for good Link, BLINK for Activity LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s LED_ACT/LED_COL = ON for Collision, OFF for No Collision Full Duplex, OFF for Half Duplex In Mode 3, LEDs are configured as follows: LED_LINK = ON for Good Link, BLINK for Activity LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s LED_ACT/LED_COL = ON for Full Duplex, OFF for Half Duplex 4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port. 7.2.7 10 Base-T Status/Control Register (10BTSCR) This register is used for control and status for 10BASE-T device operation. Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah Bit Bit Name Default 15 10BT_SERIAL Strap, RW Description 10Base-T Serial Mode (SNI) 1 = Enables 10Base-T Serial Mode 0 = Normal Operation Places 10 Mb/s transmit and receive functions in Serial Network Interface (SNI) Mode of operation. Has no effect on 100 Mb/s operation. 14:12 RESERVED 0, RW RESERVED: Must be zero. 11:9 SQUELCH 100, RW Squelch Configuration: Used to set the Squelch `ON' threshold for the receiver. Default Squelch ON is 330mV peak. 73 www.national.com DP83849I Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah (Continued) Bit Bit Name Default 8 LOOPBACK_10_DIS 0, RW Description 10Base-T Loopback Disable: In half-duplex mode, default 10BASE-T operation loops Transmit data to the Receive data in addition to transmitting the data on the physical medium. This is for consistency with earlier 10BASE2 and 10BASE5 implementations which used a shared medium. Setting this bit disables the loopback function. This bit does not affect loopback due to setting BMCR[14]. 7 LP_DIS 0, RW Normal Link Pulse Disable: 1 = Transmission of NLPs is disabled. 0 = Transmission of NLPs is enabled. 6 FORCE_LINK_10 0, RW Force 10Mb Good Link: 1 = Forced Good 10Mb Link. 0 = Normal Link Status. 5 RESERVED 0, RW 4 POLARITY RO/LH RESERVED: Must be zero. 10Mb Polarity Status: This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS register. 1 = Inverted Polarity detected. 0 = Correct Polarity detected. 3 RESERVED 0, RW RESERVED: Must be zero. 2 RESERVED 1, RW RESERVED: Must be set to one. 1 HEARTBEAT_DIS 0, RW Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode. 1 = Heartbeat function disabled. 0 = Heartbeat function enabled. When the device is operating at 100Mb or configured for full duplex operation, this bit will be ignored - the heartbeat function is disabled. 0 JABBER_DIS 0, RW Jabber Disable: Applicable only in 10BASE-T. 1 = Jabber function disabled. 0 = Jabber function enabled. www.national.com 74 This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the packet BIST function. Table 40. CD Test and BIST Extensions Register (CDCTRL1), address 1Bh Bit Bit Name Default 15:8 BIST_ERROR_COUNT 0, RO Description BIST ERROR Counter: Counts number of errored data nibbles during Packet BIST. This value will reset when Packet BIST is restarted. The counter sticks when it reaches its max count. 7:6 RESERVED 0, RW RESERVED: Must be zero. 5 BIST_CONT_MODE 0, RW Packet BIST Continuous Mode: Allows continuous pseudo random data transmission without any break in transmission. This can be used for transmit VOD testing. This is used in conjunction with the BIST controls in the PHYCR Register (19h). For 10Mb operation, jabber function must be disabled, bit 0 of the 10BTSCR (1Ah), JABBER_DIS = 1. 4 CDPATTEN_10 0, RW CD Pattern Enable for 10Mb: 1 = Enabled. 0 = Disabled. 3 RESERVED 0, RW RESERVED: Must be zero. 2 10MEG_PATT_GAP 0, RW Defines gap between data or NLP test sequences: 1 = 15 s. 0 = 10 s. 1:0 CDPATTSEL[1:0] 00, RW CD Pattern Select[1:0]: If CDPATTEN_10 = 1: 00 = Data, EOP0 sequence 01 = Data, EOP1 sequence 10 = NLPs 11 = Constant Manchester 1s (10MHz sine wave) for harmonic distortion testing. 7.2.9 Phy Control Register 2 (PHYCR2) This register provides additional general control. Table 41. Phy Control Register 2 (PHYCR2), address 1Ch Bit Bit Name Default 15:10 RESERVED 0, RO 9 SOFT_RESET 0, RW/SC Description RESERVED: Writes ignored, read as 0. Soft Reset: Resets the entire device minus the registers - all configuration is preserved. 1= Reset, self-clearing. 8:0 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 75 www.national.com DP83849I 7.2.8 CD Test and BIST Extensions Register (CDCTRL1) DP83849I 7.2.10 Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. Table 42. Energy Detect Control (EDCR), address 1Dh Bit Bit Name Default 15 ED_EN Strap, RW Description Energy Detect Enable: Allow Energy Detect Mode. When Energy Detect is enabled and Auto-Negotiation is disabled via the BMCR register, Auto-MDIX should be disabled via the PHYCR register. 14 ED_AUTO_UP 1, RW Energy Detect Automatic Power Up: Automatically begin power up sequence when Energy Detect Data Threshold value (EDCR[3:0]) is reached. Alternatively, device could be powered up manually using the ED_MAN bit (ECDR[12]). 13 ED_AUTO_DOWN 1, RW Energy Detect Automatic Power Down: Automatically begin power down sequence when no energy is detected. Alternatively, device could be powered down using the ED_MAN bit (EDCR[12]). 12 ED_MAN 0, RW/SC Energy Detect Manual Power Up/Down: Begin power up/down sequence when this bit is asserted. When set, the Energy Detect algorithm will initiate a change of Energy Detect state regardless of threshold (error or data) and timer values. In managed applications, this bit can be set after clearing the Energy Detect interrupt to control the timing of changing the power state. 11 ED_BURST_DIS 0, RW Energy Detect Burst Disable: Disable bursting of energy detect data pulses. By default, Energy Detect (ED) transmits a burst of 4 ED data pulses each time the CD is powered up. When bursting is disabled, only a single ED data pulse will be send each time the CD is powered up. 10 ED_PWR_STATE 0, RO Energy Detect Power State: Indicates current Energy Detect Power state. When set, Energy Detect is in the powered up state. When cleared, Energy Detect is in the powered down state. This bit is invalid when Energy Detect is not enabled. 9 ED_ERR_MET 0, RO/COR Energy Detect Error Threshold Met: No action is automatically taken upon receipt of error events. This bit is informational only and would be cleared on a read. 8 ED_DATA_MET 0, RO/COR Energy Detect Data Threshold Met: The number of data events that occurred met or surpassed the Energy Detect Data Threshold. This bit is cleared on a read. 7:4 ED_ERR_COUNT 0001, RW Energy Detect Error Threshold: Threshold to determine the number of energy detect error events that should cause the device to take action. Intended to allow averaging of noise that may be on the line. Counter will reset after approximately 2 seconds without any energy detect data events. 3:0 ED_DATA_COUNT 0001, RW Energy Detect Data Threshold: Threshold to determine the number of energy detect events that should cause the device to take actions. Intended to allow averaging of noise that may be on the line. Counter will reset after approximately 2 seconds without any energy detect data events. www.national.com 76 DP83849I 7.3 Link Diagnostics Registers - Page 2 Page 2 Link Diagnostics Registers are accessible by setting bits [1:0] = 10 of PAGESEL (13h). 7.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h This register contains linked cable length estimation in 100Mb operation. The cable length is an estimation of the effective cable length based on the characteristics of the recovered signal. The cable length is valid only during 100Mb operation with a valid Link status indication. Table 43. 100Mb Length Detect Register (LEN100_DET), address 14h Bit Bit Name Default Description 15:8 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 7:0 CABLE_LEN 0, RO Cable Length Estimate: Indicates an estimate of effective cable length in meters. A value of FF indicates cable length cannot be determined. 7.3.2 100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h This register returns an indication of clock frequency offset relative to the link partner. Two values can be read, the long term Frequency Offset, or a short term Frequency Control value. The Frequency Control value includes short term phase correction. The variance between the Frequency Control value and the Frequency Offset can be used as an indication of the amount of jitter in the system. Table 44. 100Mb Frequency Offset Indication Register (FREQ100), address 15h Bit Bit Name Default 15 SAMPLE_FREQ 0, RW Description Sample Frequency Offset: If Sel_FC is set to a 0, then setting this bit to a 1 will poll the DSP for the long-term Frequency Offset value. The value will be available in the Freq_Offset bits of this register. If Sel_FC is set to a 1, then setting this bit to a 1 will poll the DSP for the current Frequency Control value. The value will be available in the Freq_Offset bits of this register. This register bit will always read back as 0. 14:9 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 8 SEL_FC 0, RW Select Frequency Control: Setting this bit to a 1 will select the current Frequency Control value instead of the Frequency Offset. This value contains Frequency Offset plus the short term phase correction and can be used to indicate amount of jitter in the system. The value will be available in the Freq_Offset bits of this register. 7:0 FREQ_OFFSET 0, RO Frequency Offset: Frequency offset value loaded from the DSP following assertion of the Sample_Freq control bit. The Frequency Offset or Frequency Control value is a twos-complement signed value in units of approximately 5.1562ppm. The range is as follows: 0x7F = +655ppm 0x00 = 0ppm 0x80 = -660ppm 77 www.national.com DP83849I 7.3.3 TDR Control Register (TDR_CTRL), Page 2, address 16h This register contains control for the Time Domain Reflectometry (TDR) cable diagnostics. The TDR cable diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length and detect certain cabling faults. Table 45. TDR Control Register (TDR_CTRL), address 16h Bit Bit Name Default 15 TDR_ENABLE 0, RW Description TDR Enable: Enable TDR mode. This forces powerup state to correct operating condition for sending and receiving TDR pulses. 14 TDR_100Mb 0, RW TDR 100Mb: Sets TDR controller to use the 100Mb Transmitter. This allows for sending pulse widths in multiples of 8ns. Pulses in 100Mb mode will alternate between positive pulses and negative pulses. Default operation uses the 10Mb Link Pulse generator. Pulses may include just the 50ns preemphasis portion of the pulse or the 100ns full link pulse (as controlled by setting TDR Width). 13 TX_CHANNEL 0, RW Transmit Channel Select: Select transmit channel for sending pulses. Pulse can be sent on the Transmit or Receive pair. 0 : Transmit channel 1 : Receive channel 12 RX_CHANNEL 0, RW Receive Channel Select: Select receive channel for detecting pulses. Pulse can be monitored on the Transmit or Receive pair. 0 : Transmit channel 1 : Receive channel 11 SEND_TDR 0, RW/SC Send TDR Pulse: Setting this bit will send a TDR pulse and enable the monitor circuit to capture the response. This bit will automatically clear when the capture is complete. 10:8 TDR_WIDTH 0, RW TDR Pulse Width: Pulse width in clocks for the transmitted pulse. In 100Mb mode, pulses are in 8ns increments. In 10Mb mode, pulses are in 50ns increments, but only 50ns or 100ns pulses can be sent. Sending a pulse of 0 width will not transmit a pulse, but allows for baseline testing. 7 TDR_MIN_MODE 0, RW Min/Max Mode control: This bit controls direction of the pulse to be detected. Default looks for a positive peak. Threshold and peak values will be interpreted appropriately based on this bit. 0 : Max Mode, detect positive peak 1 : Min Mode, detect negative peak 6 RESERVED 5:0 RX_THRESHOLD 0, RO RESERVED: Writes ignored, read as 0. <10_0000>, RW RX Threshold: This value provides a threshold for measurement to the start of a peak. If Min Mode is set to 0, data must be greater than this value to trigger a capture. If Min Mode is 1, data must be less than this value to trigger a capture. Data ranges from 0x00 to 0x3F, with 0x20 as the midpoint. Positive data is greater than 0x20, negative data is less than 0x20. www.national.com 78 This register contains sample window control for the Time Domain Reflectometry (TDR) cable diagnostics. The two values contained in this register specify the beginning and end times for the window to monitor the response to the transmitted pulse. Time values are in 8ns increments. This provides a method to search for multiple responses and also to screen out the initial outgoing pulse. Table 46. TDR Window Register (TDR_WIN), address 17h Bit Bit Name Default 15:8 TDR_START 0, RW Description TDR Start Window: Specifies start time for monitoring TDR response. 7:0 TDR_STOP 0xFF, RW TDR Stop Window: Specifies stop time for monitoring TDR response. The Stop Window should be set to a value greater than or equal to the Start Window. 7.3.5 TDR Peak Register (TDR_PEAK), Page 2, address 18h This register contains the results of the TDR Peak Detection. Results are valid if the TDR_CTRL[11] is clear following sending the TDR pulse. Table 47. TDR Peak Register (TDR_PEAK), address 18h Bit Bit Name Default Description 15:14 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 13:8 TDR_PEAK 0, RO TDR Peak Value: This register contains the peak value measured during the TDR sample window. If Min Mode control (TDR_CTRL[7]) is 0, this contains the maximum detected value. If Min Mode control is 1, this contains the minimum detected value. 7:0 TDR_PEAK_TIME 0, RO TDR Peak Time: Specifies the time for the first occurrence of the peak value. 7.3.6 TDR Threshold Register (TDR_THR), Page 2, address 19h This register contains the results of the TDR Threshold Detection. Results are valid if the TDR_CTRL[11] is clear following sending the TDR pulse. Table 48. TDR Threshold Register (TDR_THR), address 19h Bit Bit Name Default 15:9 RESERVED 0, RO RESERVED: Writes ignored, read as 0. Description 8 TDR_THR_MET 0, RO TDR Threshold Met: This bit indicates the TDR threshold was met during the sample window. A value of 0 indicates the threshold was not met. 7:0 TDR_THR_TIME 0, RO TDR Threshold Time: Specifies the time for the first data that met the TDR threshold. This field is only valid if the threshold was met. 79 www.national.com DP83849I 7.3.4 TDR Window Register (TDR_WIN), Page 2, address 17h DP83849I 7.3.7 Variance Control Register (VAR_CTRL), Page 2, address 1Ah The Variance Control and Data Registers provide control and status for the Cable Signal Quality Estimation function. The Cable Signal Quality Estimation allows a simple method of determining an approximate Signal-to-Noise Ratio for the 100Mb receiver. This register contains the programmable controls and status bits for the variance computation, which can be used to make a simple Signal-to-Noise Ratio estimation. Table 49. Variance Control Register (VAR_CTRL), address 1Ah Bit 15 Bit Name Default VAR_RDY 0, RO Description Variance Data Ready Status: Indicates new data is available in the Variance data register. This bit will be automatically cleared after two consecutive reads ot VAR_DATA. 14:4 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 3 VAR_FREEZE 0, RW Freeze Variance Registers: Freeze VAR_DATA register. This bit is ensures that VAR_DATA register is frozen for software reads. This bit is automatically cleared after two consecutive reads of VAR_DATA. 2:1 VAR_TIMER 0, RW Variance Computation Timer (in ms): Selects the Variance computation timer period. After a new value is written, computation is automatically restarted. New variance register values are loaded after the timer elapses. Var_Timer = 0 => 2 ms timer (default) Var_Timer = 1 => 4 ms timer Var_Timer = 2 => 6 ms timer Var_Timer = 3 => 8 ms timer Time units are actually 217 cycles of an 8ns clock, or 1.048576ms. 0 VAR_ENABLE 0, RW Variance Enable: Enable Variance computation. Off by default. 7.3.8 Variance Data Register (VAR_DATA), Page 2, address 1Bh This register contains the 32-bit Variance Sum. The contents of the data are valid only when VAR_RDY is asserted in the VAR_CTRL register. Upon detection of VAR_RDY asserted, software should set the VAR_FREEZE bit in the VAR_CTRL register to prevent loading of a new value into the VAR_DATA register. Since the Variance Data value is 32-bits, two reads of this register are required to get the full value. Table 50. Variance Data Register (VAR_DATA), address 1Bh Bit Bit Name Default 15:0 VAR_DATA 0, RO Description Variance Data: Two reads are required to return the full 32-bit Variance Sum value. Following setting the VAR_FREEZE control, the first read of this register will return the low 16 bits of the Variance data. A second read will return the high 16 bits of Variance data. www.national.com 80 This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an interrupt will be asserted if enabled in the MISR. Monitor control and status are available in this register, while the LQDR register controls read/write access to threshold values and current parameter values. Reading of LQMR register clears warning bits and re-arms the interrupt generation. In addition, this register provides a mechanims for allowing automatic reset of the 100Mb link based on the Link Quality Monitor status. Table 51. Link Quality Monitor Register (LQMR), address 1Dh Bit Bit Name Default 15 LQM_ENABLE 0, RW Description Link Quality Monitor Enable: Enables the Link Quality Monitor. The enable is qualified by having a valid 100Mb link. In addition, the individual thresholds can be disabled by setting to the max or min values. 14:10 RESERVED 0, RO 9 FC_HI_WARN 0, RO/COR RESERVED: Writes ignored, read as 0. Frequency Control High Warning: This bit indicates the Frequency Control High Threshold was exceeded. This register bit will be cleared on read. 8 FC_LO_WARN 0, RO/COR Frequency Control Low Warning: This bit indicates the Frequency Control Low Threshold was exceeded. This register bit will be cleared on read. 7 FREQ_HI_WARN 0, RO/COR Frequency Offset High Warning: This bit indicates the Frequency Offset High Threshold was exceeded. This register bit will be cleared on read. 6 FREQ_LO_WARN 0, RO/COR Frequency Offset Low Warning: This bit indicates the Frequency Offset Low Threshold was exceeded. This register bit will be cleared on read. 5 DBLW_HI_WARN 0, RO/COR DBLW High Warning: This bit indicates the DBLW High Threshold was exceeded. This register bit will be cleared on read. 4 DBLW_LO_WARN 0, RO/COR DBLW Low Warning: This bit indicates the DBLW Low Threshold was exceeded. This register bit will be cleared on read. 3 DAGC_HI_WARN 0, RO/COR DAGC High Warning: This bit indicates the DAGC High Threshold was exceeded. This register bit will be cleared on read. 2 DAGC_LO_WARN 0, RO/COR DAGC Low Warning: This bit indicates the DAGC Low Threshold was exceeded. This register bit will be cleared on read. 1 C1_HI_WARN 0, RO/COR C1 High Warning: This bit indicates the DEQ C1 High Threshold was exceeded. This register bit will be cleared on read. 0 C1_LO_WARN 0, RO/COR C1 Low Warning: This bit indicates the DEQ C1 Low Threshold was exceeded. This register bit will be cleared on read. 81 www.national.com DP83849I 7.3.9 Link Quality Monitor Register (LQMR), Page 2, address 1Dh DP83849I 7.3.10 Link Quality Data Register (LQDR), Page 2 This register provides read/write control of thresholds for the 100Mb Link Quality Monitor function. The register also provides a mechanism for reading current adapted parameter values. Threshold values may not be written if the device is powered-down. Table 52. Link Quality Data Register (LQDR), address 1Eh Bit Bit Name Default Description 15:14 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 13 SAMPLE_PARAM 0, RW Sample DSP Parameter: Setting this bit to a 1 enables reading of current parameter values and initiates sampling of the parameter value. The parameter to be read is selected by the LQ_PARAM_SEL bits. 12 WRITE_LQ_THR 0, RW Write Link Quality Threshold: Setting this bit will cause a write to the Threshold register selected by LQ_PARAM_SEL and LQ_THR_SEL. The data written is contained in LQ_THR_DATA. This bit will always read back as 0. 11:9 LQ_PARAM_SEL 0, RW Link Quality Parameter Select: This 3-bit field selects the Link Quality Parameter. This field is used for sampling current parameter values as well as for reads/writes to Threshold values. The following encodings are available: 000: DEQ_C1 001: DAGC 010: DBLW 011: Frequency Offset 100: Frequency Control 8 LQ_THR_SEL 0, RW Link Quality Threshold Select: This bit selects the Link Quality Threshold to be read or written. A 0 selects the Low threshold, while a 1 selects the high threshold. When combined with the LQ_PARAM_SEL field, the following encodings are available {LQ_PARAM_SEL, LQ_THR_SEL}: 000,0: DEQ_C1 Low 000,1: DEQ_C1 High 001,0: DAGC Low 001,1: DAGC High 010,0: DBLW Low 010,1: DBLW High 011,0: Frequency Offset Low 011,1: Frequency Offset High 100,0: Frequency Control Low 100,1: Frequency Control High 7:0 LQ_THR_DATA 0, RW Link Quality Threshold Data: The operation of this field is dependent on the value of the Sample_Param bit. If Sample_Param = 0: On a write, this value contains the data to be written to the selected Link Quality Threshold register. On a read, this value contains the current data in the selected Link Quality Threshold register. If Sample_Param = 1: On a read, this value contains the sampled parameter value. This value will remain unchanged until a new read sequence is started. www.national.com 82 DP83849I 8.0 Electrical Specifications Note: All parameters are guaranteed by test, statistical analysis or design. Recommended Operating Conditions Absolute Maximum Ratings Supply Voltage (VCC) Supply voltage (VCC) -0.5 V to 4.2 V 3.3 Volts + .3V DC Input Voltage (VIN) -0.5V to VCC + 0.5V Industrial - Ambient Temperature (TA) DC Output Voltage (VOUT) -0.5V to VCC + 0.5V Power Dissipation (PD) Storage Temperature (TSTG) 260 C ESD Rating (RZAP = 1.5k, CZAP = 100 pF) 4.0 kV 594 mW Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. -65oC to 150C Lead Temp. (TL) (Soldering, 10 sec.) -40 to 85 C Thermal Characteristic Maximum Case Temperature @ 1.0 W Max 108 Units C Theta Junction to Case (Tjc) @ 1.0 W 17.3 C / W 53 C / W Theta Junction to Ambient (Tja) degrees Celsius/Watt - No Airflow @ 1.0 W 8.1 DC Specs Symbol Pin Types Parameter Conditions Min Typ Max 2.0 Units VIH I I/O Input High Voltage Nominal VCC V VIL I I/O Input Low Voltage 0.8 V IIH I I/O Input High Current VIN = VCC 10 A IIL I I/O Input Low Current VIN = GND 10 A VOL O, I/O Output Low Voltage IOL = 4 mA 0.4 V VOH O, I/O Output High Voltage IOH = -4 mA IOZ I/O, O TRI-STATE Leakage VOUT = VCC Vcc - 0.5 0.95 V A 1.05 V +2 % 2.8 V VTPTD_100 PMD Output Pair 100M Transmit Voltage VTPTDsym PMD Output Pair 100M Transmit Voltage Symmetry VTPTD_10 PMD Output Pair 10M Transmit Voltage CIN1 I CMOS Input Capacitance 8 pF COUT1 O CMOS Output Capacitance 8 pF 2.2 83 1 + 10 2.5 www.national.com DP83849I Symbol Pin Types Parameter SDTHon PMD Input Pair 100BASE-TX Signal detect turnon threshold SDTHoff PMD Input Pair 100BASE-TX Signal detect turnoff threshold VTH1 PMD Input Pair 10BASE-T Receive Threshold Idd100 Supply 100BASE-TX (Full Duplex) 180 mA Idd10 Supply 10BASE-T (Full Duplex) 180 mA Idd Supply Power Down Mode 9.5 mA www.national.com Conditions Min Typ Max Units 1000 mV diff pk-pk 200 mV diff pk-pk 585 CLK2MAC disabled 84 mV DP83849I 8.2 AC Specs 8.2.1 Power Up Timing Vcc X1 clock T2.1.1 Hardware RESET_N 32 clocks MDC T2.1.2 Latch-In of Hardware Configuration Pins T2.1.3 input Dual Function Pins Become Enabled As Outputs Parameter Description output Notes Min Typ Max Units T2.1.1 Post Power Up Stabilization MDIO is pulled high for 32-bit serial mantime prior to MDC preamble for agement initialization register accesses X1 Clock must be stable for a min. of 167ms at power up. 167 ms T2.1.2 Hardware Configuration Latch- Hardware Configuration Pins are described in the Pin Description section in Time from power up 167 ms X1 Clock must be stable for a min. of 167ms at power up. T2.1.3 Hardware Configuration pins transition to output drivers 50 ns Note: In RMII Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84ms. 85 www.national.com DP83849I 8.2.2 Reset Timing Vcc X1 clock T2.2.1 T2.2.4 Hardware RESET_N 32 clocks MDC T2.2.2 Latch-In of Hardware Configuration Pins T2.2.3 input Dual Function Pins Become Enabled As Outputs Parameter Description output Notes Min Typ Max Units T2.2.1 Post RESET Stabilization time MDIO is pulled high for 32-bit serial manprior to MDC preamble for reg- agement initialization ister accesses 3 s T2.2.2 Hardware Configuration Latch- Hardware Configuration Pins are dein Time from the Deassertion scribed in the Pin Description section of RESET (either soft or hard) 3 s T2.2.3 Hardware Configuration pins transition to output drivers 50 ns T2.2.4 RESET pulse width X1 Clock must be stable for at min. of 1us during RESET pulse low time. 1 s Note: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver. www.national.com 86 DP83849I 8.2.3 MII Serial Management Timing MDC T2.3.1 T2.3.4 MDIO (output) MDC T2.3.2 Valid Data MDIO (input) Parameter T2.3.3 Description Notes Min T2.3.1 MDC to MDIO (Output) Delay Time 0 T2.3.2 MDIO (Input) to MDC Setup Time 10 T2.3.3 MDIO (Input) to MDC Hold Time 10 T2.3.4 MDC Frequency Typ Max Units 30 ns ns ns 2.5 25 MHz 8.2.4 100 Mb/s MII Transmit Timing T2.4.1 T2.4.1 TX_CLK T2.4.3 T2.4.2 TXD[3:0] TX_EN Parameter Valid Data Min Typ T2.4.1 TX_CLK High/Low Time Description 100 Mb/s Normal mode Notes 16 20 T2.4.2 TXD[3:0], TX_EN Data Setup to TX_CLK 100 Mb/s Normal mode 10 ns T2.4.3 TXD[3:0], TX_EN Data Hold from TX_CLK 100 Mb/s Normal mode 0 ns 87 Max Units 24 ns www.national.com DP83849I 8.2.5 100 Mb/s MII Receive Timing T2.5.1 T2.5.1 RX_CLK T2.5.2 RXD[3:0] RX_DV RX_ER Valid Data Parameter Description Notes Min Typ Max Units 20 24 ns 30 ns T2.5.1 RX_CLK High/Low Time 100 Mb/s Normal mode 16 T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. 8.2.6 100BASE-TX MII Transmit Packet Latency Timing TX_CLK TX_EN TXD PMD Output Pair Parameter T2.6.1 T2.6.1 IDLE (J/K) Description TX_CLK to PMD Output Pair Latency Notes 100BASE-TX mode DATA Min Typ 5 Max Units bits Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the "J" code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode. www.national.com 88 DP83849I 8.2.7 100BASE-TX MII Transmit Packet Deassertion Timing TX_CLK TX_EN TXD T2.7.1 PMD Output Pair Parameter T2.7.1 DATA DATA (T/R) (T/R) Description TX_CLK to PMD Output Pair Deassertion Notes 100BASE-TX mode IDLE IDLE Min Typ 5 Max Units bits Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the "T" code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode. 89 www.national.com DP83849I 8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) T2.8.1 +1 rise 90% 10% PMD Output Pair 10% +1 fall 90% T2.8.1 -1 fall -1 rise T2.8.1 T2.8.1 T2.8.2 PMD Output Pair eye pattern Parameter T2.8.1 T2.8.2 T2.8.2 Description Notes Min Typ Max Units 3 4 5 ns 100 Mb/s tR and tF Mismatch 500 ps 100 Mb/s PMD Output Pair Transmit Jitter 1.4 ns 100 Mb/s PMD Output Pair tR and tF Note: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times Note: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude www.national.com 90 DP83849I 8.2.9 100BASE-TX MII Receive Packet Latency Timing PMD Input Pair IDLE Data (J/K) T2.9.1 CRS T2.9.2 RXD[3:0] RX_DV RX_ER Parameter Description Notes Min Typ Max Units T2.9.1 Carrier Sense ON Delay 100BASE-TX mode 20 bits T2.9.2 Receive Data Latency 100BASE-TX mode 24 bits Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the "J" code group to the assertion of Carrier Sense. Note: 1 bit time = 10 ns in 100 Mb/s mode Note: PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value. 8.2.10 100BASE-TX MII Receive Packet Deassertion Timing PMD Input Pair DATA IDLE (T/R) T2.10.1 CRS Parameter T2.10.1 Description Carrier Sense OFF Delay Notes 100BASE-TX mode Min Typ 24 Max Units bits Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the "T" code group to the deassertion of Carrier Sense. Note: 1 bit time = 10 ns in 100 Mb/s mode 91 www.national.com DP83849I 8.2.11 10 Mb/s MII Transmit Timing T2.11.1 T2.11.1 TX_CLK T2.11.3 T2.11.2 TXD[3:0] TX_EN Parameter Valid Data Description Notes Min Typ Max Units 200 210 T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 ns T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode 25 ns T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode 0 ns Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge of TX_CLK. 8.2.12 10 Mb/s MII Receive Timing T2.12.1 T2.12.1 RX_CLK T2.12.3 T2.12.2 RXD[3:0] RX_DV Parameter Valid Data Description Notes Min Typ Max Units 160 200 240 ns T2.12.1 RX_CLK High/Low Time T2.12.2 RX_CLK to RXD[3:0], RX_DV Delay 10 Mb/s MII mode 100 ns T2.12.3 RX_CLK rising edge delay from RXD[3:0], RX_DV Valid 10 Mb/s MII mode 100 ns Note: RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. www.national.com 92 DP83849I 8.2.13 10 Mb/s Serial Mode Transmit Timing T2.13.2 T2.13.1 TX_CLK T2.13.4 T2.13.3 TXD[0] TX_EN Parameter Valid Data Min Typ T2.13.1 TX_CLK High Time Description 10 Mb/s Serial mode Notes 20 25 Max Units 30 ns T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode 70 75 80 ns T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise 10 Mb/s Serial mode 25 ns T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 10 Mb/s Serial mode 0 ns 8.2.14 10 Mb/s Serial Mode Receive Timing T2.14.1 T2.14.1 RX_CLK T2.14.2 RXD[0] RX_DV Parameter Valid Data Description T2.14.1 RX_CLK High/Low Time T2.14.2 RX_CLK fall to RXD_0, RX_DV Delay Notes 10 Mb/s Serial mode Min Typ Max Units 35 50 65 ns 10 ns -10 Note: RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. 93 www.national.com DP83849I 8.2.15 10BASE-T Transmit Timing (Start of Packet) TX_CLK TX_EN TXD T2.15.2 PMD Output Pair T2.15.1 Parameter Description T2.15.1 Notes Transmit Output Delay from the Min Typ Max Units 10 Mb/s MII mode 3.5 bits 10 Mb/s Serial mode 3.5 bits Falling Edge of TX_CLK T2.15.2 Transmit Output Delay from the Rising Edge of TX_CLK Note: 1 bit time = 100 ns in 10Mb/s. 8.2.16 10BASE-T Transmit Timing (End of Packet) TX_CLK TX_EN 0 PMD Output Pair T2.16.1 0 T2.16.2 PMD Output Pair Parameter T2.16.1 1 1 Description Notes End of Packet High Time Min Typ 250 300 Max Units ns 250 300 ns (with `0' ending bit) T2.16.2 End of Packet High Time (with `1' ending bit) www.national.com 94 DP83849I 8.2.17 10BASE-T Receive Timing (Start of Packet) 1st SFD bit decoded 1 0 1 0 1 0 1 0 1 0 1 1 TPRD T2.17.1 CRS RX_CLK T2.17.2 RX_DV T2.17.3 0000 RXD[3:0] Parameter Preamble Description SFD Notes Min Data Typ Max Units 1000 ns T2.17.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) 630 T2.17.2 RX_DV Latency 10 bits T2.17.3 Receive Data Latency 8 bits Measurement shown from SFD Note: 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV Note: 1 bit time = 100 ns in 10 Mb/s mode. 8.2.18 10BASE-T Receive Timing (End of Packet) 1 0 1 IDLE PMD Input Pair RX_CLK T2.18.1 CRS Parameter T2.18.1 Description Notes Carrier Sense Turn Off Delay 95 Min Typ Max Units 1.0 s www.national.com DP83849I 8.2.19 10 Mb/s Heartbeat Timing TX_EN TX_CLK T2.19.2 T2.19.1 COL Parameter Description Notes Min Typ Max Units T2.19.1 CD Heartbeat Delay 10 Mb/s half-duplex mode 1200 ns T2.19.2 CD Heartbeat Duration 10 Mb/s half-duplex mode 1000 ns 8.2.20 10 Mb/s Jabber Timing TXE T2.20.1 T2.20.2 PMD Output Pair COL Parameter Description Notes Min Typ Max Units T2.20.1 Jabber Activation Time 85 ms T2.20.2 Jabber Deactivation Time 500 ms www.national.com 96 DP83849I 8.2.21 10BASE-T Normal Link Pulse Timing T2.21.2 T2.21.1 Normal Link Pulse(s) Parameter Description Notes Min Typ Max Units T2.21.1 Pulse Width 100 ns T2.21.2 Pulse Period 16 ms Note: These specifications represent transmit timings. 8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing T2.22.2 T2.22.3 T2.22.1 T2.22.1 Fast Link Pulse(s) clock pulse data pulse clock pulse T2.22.5 T2.22.4 FLP Burst Parameter FLP Burst Description Notes Min Typ Max Units T2.22.1 Clock, Data Pulse Width 100 ns T2.22.2 Clock Pulse to Clock Pulse Period 125 s T2.22.3 Clock Pulse to Data Pulse Period 62 s T2.22.4 Burst Width 2 ms T2.22.5 FLP Burst to FLP Burst Period 16 ms Data = 1 Note: These specifications represent transmit timings. 97 www.national.com DP83849I 8.2.23 100BASE-TX Signal Detect Timing PMD Input Pair T2.23.1 T2.23.2 SD+ internal Parameter Description Notes Min Typ Max Units T2.23.1 SD Internal Turn-on Time 1 ms T2.23.2 SD Internal Turn-off Time 350 s Max Units 240 ns Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. 8.2.24 100 Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS T2.24.1 RX_CLK RX_DV RXD[3:0] Parameter T2.24.1 Description TX_EN to RX_DV Loopback Notes Min 100 Mb/s internal loopback mode Typ Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial "dead-time" of up to 550 s during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the initial 550s "dead-time". Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. www.national.com 98 DP83849I 8.2.25 10 Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS T2.25.1 RX_CLK RX_DV RXD[3:0] Parameter T2.25.1 Description TX_EN to RX_DV Loopback Notes Min 10 Mb/s internal loopback mode Typ Max Units 2 s Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. 99 www.national.com DP83849I 8.2.26 RMII Transmit Timing T2.26.1 X1 T2.26.2 TXD[1:0] TX_EN T2.26.3 Valid Data T2.26.4 PMD Output Pair Parameter Symbol Description Notes Min X1 Clock Period T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising 4 ns T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising 2 ns T2.26.4 X1 Clock to PMD Output Pair 100BASE-TX mode Latency (100Mb) 100 20 Max Units T2.26.1 www.national.com 50 MHz Reference Clock Typ 11 ns bits DP83849I 8.2.27 RMII Receive Timing PMD Input Pair IDLE Data (J/K) Data (TR) T2.27.4 T2.27.5 X1 T2.27.1 T2.27.2 T2.27.3 T2.27.2 T2.27.2 RX_DV CRS_DV T2.27.2 RXD[1:0] RX_ER Parameter Description Notes Min 50 MHz Reference Clock Typ Max 20 Units T2.27.1 X1 Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising T2.27.3 CRS ON delay (100Mb) 100BASE-TX mode 18.5 bits T2.27.4 CRS OFF delay (100Mb) 100BASE-TX mode 27 bits T2.27.5 RXD[1:0] and RX_ER latency (100Mb) 100BASE-TX mode 38 bits 2 ns 14 ns Note: Per the RMII Specification, output delays assume a 25pF load. Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion. Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data. Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to initial assertion of CRS_DV. Note: CRS_OFF delay is measured from the first bit of the TR symbol on the PMD Receive Pair to initial deassertion of CRS_DV. Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with the Elasticity Buffer set to the default value (01). 101 www.national.com DP83849I 8.2.28 Single Clock MII (SCMII) Transmit Timing T2.28.1 X1 T2.28.2 TXD[3:0] TX_EN T2.28.3 Valid Data T2.28.4 PMD Output Pair Parameter Symbol Description Notes Min Typ Units X1 Clock Period 25MHz Reference Clock T2.28.2 TXD[3:0], TX_EN Data Setup To X1 rising 4 ns T2.28.3 TXD[3:0], TX_EN Data Hold From X1 rising 2 ns T2.28.4 X1 Clock to PMD Output Pair Latency (100Mb) 100BASE-TX mode Note: Latency measurement is made from the X1 Rising edge to the first bit of symbol. www.national.com 102 40 Max T2.28.1 13 ns bits DP83849I 8.2.29 Single Clock MII (SCMII) Receive Timing PMD Input Pair IDLE (J/K) Data Data (TR) T2.29.4 T2.29.5 X1 T2.29.1 T2.29.3 CRS T2.29.2 T2.29.2 RX_DV RXD[1:0] RX_ER Parameter Description Notes Min 25MHz Reference Clock Typ Max 40 Units T2.29.1 X1 Clock Period T2.29.2 RXD[3:0], RX_DV and RX_ER From X1 rising output delay T2.29.3 CRS ON delay (100Mb) 100BASE-TX mode 19 bits T2.29.4 CRS OFF delay (100Mb) 100BASE-TX mode 26 bits T2.29.5 RXD[1:0] and RX_ER latency (100Mb) 100BASE-TX mode 56 bits 2 ns 18 ns Note: Output delays assume a 25pF load. Note: CRS is asserted and deasserted asynchronously relative to the reference clock. Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to assertion of CRS_DV. Note: CRS_OFF delay is measured from the first bit of the TR symbol on the PMD Receive Pair to deassertion of CRS_DV. Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with the Elasticity Buffer set to the default value (01). 103 www.national.com DP83849I 8.2.30 Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) T2.30.1 MODE NORMAL ISOLATE Parameter T2.30.1 Description Notes Min Typ From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode Max Units 100 s Max Units 8.2.31 CLK2MAC Timing X1 T2.31.2 T2.31.1 T2.31.1 CLK2MAC Parameter T2.31.1 T2.31.2 Description CLK2MAC High/Low Time CLK2MAC propagation delay Notes Typ MII mode 20 ns RMII mode 10 ns Relative to X1 Note: CLK2MAC characteristics are dependent upon the X1 input characteristics. www.national.com Min 104 8 ns DP83849I 8.2.32 100 Mb/s X1 to TX_CLK Timing X1 T2.32.1 TX_CLK Parameter T2.32.1 Description X1 to TX_CLK delay Notes 100 Mb/s Normal mode Min 0 Typ Max Units 5 ns Note: X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data. 105 www.national.com DP83849I PHYTER(R) DUAL Industrial Temperature with Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver 9.0 Physical Dimensions inches (millimeters) unless otherwise noted Thin Quad Flat Package (TQFP) NS Package Number VHB80A THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PROCUCTS. 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