1. General description
The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V
and 5 V environment.
The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable
(pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented
applications. The 9 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition, provided pin CE
is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all
flip-flops. When pin OE is LOW, the contents of the 9 flip-flops is available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
2. Features
■5 V tolerant inputs/outputs for interfacing with 5 V logic
■Wide supply voltage range from 1.2 V to 3.6 V
■Inputs accept voltages up to 5.5 V
■CMOS low power consumption
■Direct interface with TTL levels
■Flow-through pin-out architecture
■9-bit positive edge-triggered register
■Independent register and 3-state buffer operation
■Complies with JEDEC standard JESD8-B/JESD36
■ESD protection:
◆HBM EIA/JESD22-A114-B exceeds 2000 V
◆MM EIA/JESD22-A115-A exceeds 200 V.
■Specified from 40 °C to +85 °C and −40 °C to +125 °C.
74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive
edge-trigger; 3-state
Rev. 02 — 10 May 2004 Product data sheet
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 2 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
3. Quick reference data
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
∑(CL×VCC2×fo) = sum of outputs.
[2] The condition is VI= GND to VCC.
4. Ordering information
Table 1: Quick reference data
GND = 0 V; T
amb
=25
°
C; t
r
=t
f
≤
2.5 ns.
Symbol Parameter Conditions Min Typ Max Unit
tPHL,
tPLH
propagation delay
CP to Qn CL= 50 pF; VCC = 3.3 V - 3.7 - ns
tPHL propagation delay
MR to Qn CL= 50 pF; VCC = 3.3 V - 4.1 - ns
fmax maximum clock
frequency CL= 50 pF; VCC = 3.3 V - 200 - MHz
CIinput capacitance - 5.0 - pF
CPD power dissipation
capacitance per gate VCC = 3.3 V [1] [2] --
outputs enabled - 17 - pF
outputs disabled - 13 - pF
Table 2: Ordering information
Type number Package
Temperature range Name Description Version
74LVC823AD −40 °C to +125 °C SO24 plastic small outline package; 24 leads;
body width 7.5 mm SOT137-1
74LVC823ADB −40 °C to +125 °C SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm SOT340-1
74LVC823APW −40 °C to +125 °C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm SOT355-1
74LVC823ABQ −40 °C to +125 °C DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5 ×5.5 ×0.85 mm
SOT815-1
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 3 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
5. Functional diagram
Fig 1. Functional diagram.
Fig 2. Logic symbol. Fig 3. IEC logic symbol.
001aaa849
D0
D1
D2
D3
D4
D5
D6
D7
FF0
to
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3-STATE
OUTPUTS
D8 Q8
CP
MR
CE
OE
2
3
4
5
6
7
8
9
10
23
22
21
20
19
18
17
16
15
11
14
1
13
001aaa847
D0
D1
D2
D3
D4
D5
D6
CP
MR Q0
Q1
Q2
Q3
Q4
Q5
Q6
1
14
17
18
19
20
21
22
23
8
7
D7
D8
Q7
Q8 15
16
10
9
6
5
4
3
2
11
OE
13
CE
001aaa848
17
18
19
20
21
22
14 G1
2D 23
8
7
6
5
4
3
2
169
1510
13 1C2
11 R
1EN
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 4 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
Fig 4. Logic diagram.
001aaa850
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
D
FF0
Q
CP
CP
D
FF1
Q
CP
D
FF2
Q
CP
D
FF3
Q
CP
D
FF4
Q
CP
D
FF5
Q
CP
D
FF6
Q
CP
D
FF8
Q
CP
OE
Q5
D5
Q6
D6
Q8
D8
D
FF7
Q
CP
Q7
D7
MR
RRRRR
RR RR
CE
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 5 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO24 and (T)SSOP24. Fig 6. Pin configuration DHVQFN24.
823
OE VCC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D8 Q8
MR CE
GND CP
001aaa845
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
001aaa846
823
Transparent top view
CE
D8
MR
Q8
D7 Q7
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0
GND
CP
OE
VCC
11 14
10 15
9 16
8 17
7 18
6 19
5 20
4 21
3 22
2 23
12
13
1
24
terminal 1
index area
GND(1)
Table 3: Pin description
Symbol Pin Description
1OE output enable input (active LOW)
2 D0 data input
3 D1 data input
4 D2 data input
5 D3 data input
6 D4 data input
7 D5 data input
8 D6 data input
9 D7 data input
10 D8 data input
11 MR master reset input (active LOW)
12 GND ground (0 V)
13 CP clock input (LOW-to-HIGH; edge-triggered)
14 CE clock enable input (active LOW)
15 Q8 3-state flip-flop output
16 Q7 3-state flip-flop output
17 Q6 3-state flip-flop output
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 6 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
7. Functional description
7.1 Function table
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
NC = no change;
↑= LOW-to-HIGH level transition;
X = don’t care.
18 Q5 3-state flip-flop output
19 Q4 3-state flip-flop output
20 Q3 3-state flip-flop output
21 Q2 3-state flip-flop output
22 Q1 3-state flip-flop output
23 Q0 3-state flip-flop output
24 VCC supply voltage
Table 3: Pin description
…continued
Symbol Pin Description
Table 4: Function table [1]
Operating mode Input Internal
flip-flop Output
OE MR CE CP Dn Qn
Clear L L XXXLL
Load and read
register LHL↑lLL
LHL↑hHH
Load register and
disable outputs HHL↑lLZ
HHL↑hHZ
Hold L H H NC X NC NC
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 7 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO24 packages: Ptot derates linearly with 8 mW/K above 70 °C.
For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN24 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground=0V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI<0V - −50 mA
VIinput voltage [1] −0.5 +6.5 V
IOK output diode current VO>V
CC or VO<0V - ±50 mA
VOoutput voltage HIGH or LOW state [1] −0.5 VCC + 0.5 V
3-state [1] −0.5 +6.5 V
IOoutput source or sink
current VO=0VtoV
CC -±50 mA
ICC,
IGND
VCC or GND current - ±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation Tamb =−40 °C to +125 °C[2] - 500 mW
Table 6: Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage for maximum speed
performance 2.7 - 3.6 V
for low-voltage applications 1.2 - 3.6 V
VIinput voltage 0 - 5.5 V
VOoutput voltage HIGH or LOW state 0 - VCC V
3-state 0 - 5.5 V
Tamb operating ambient
temperature in free air −40 - +125 °C
tr, tfinput rise and fall
times VCC = 1.2 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 8 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
10. Static characteristics
Table 7: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =−40 °C to +85 °C[1]
VIH HIGH-level input voltage VCC = 1.2 V VCC --V
VCC = 2.7 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 1.2 V - - GND V
VCC = 2.7 V to 3.6 V - - 0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=−100 µA; VCC = 2.7 V to 3.6 V [2] VCC −0.2 VCC -V
IO=−12 mA; VCC = 2.7 V VCC −0.5 - - V
IO=−18 mA; VCC = 3.0 V VCC −0.6 - - V
IO=−24 mA; VCC = 3.0 V VCC −0.8 - - V
VOL LOW-level output voltage VI=V
IH or VIL
IO= 100 µA; VCC = 2.7 V to 3.6 V [2] - GND 0.2 V
IO= 12 mA; VCC = 2.7 V - - 0.4 V
IO= 24 mA; VCC = 3.0 V - - 0.55 V
ILI input leakage current VI= 5.5 Vor GND; VCC = 3.6 V - ±0.1 ±5µA
IOZ 3-state output OFF-state
current VI=V
IH or VIL; VO= 5.5 Vor GND;
VCC = 3.6 V - 0.1 ±5µA
Ioff power-off leakage supply VIor VO= 5.5 V; VCC = 0 V - 0.1 ±10 µA
ICC quiescent supply current VI=V
CC or GND; IO=0A;
VCC = 3.6 V - 0.1 10 µA
∆ICC additional quiescent
supply current per pin VI=V
CC −0.6 V; IO=0A;
VCC = 2.7 V to 3.6 V [2] - 5 500 µA
CIinput capacitance - 5.0 - pF
Tamb =−40 °C to +125 °C
VIH HIGH-level input voltage VCC =1.2 V VCC --V
VCC = 2.7 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 1.2 V - - GND V
VCC = 2.7 V to 3.6 V - - 0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=−100 µA; VCC = 2.7 V to 3.6 V VCC −0.3 - - V
IO=−12 mA; VCC = 2.7 V VCC −0.65 - - V
IO=−18 mA; VCC = 3.0 V VCC −0.75 - - V
IO=−24 mA; VCC = 3.0 V VCC −1--V
VOL LOW-level output voltage VI=V
IH or VIL
IO= 100 µA; VCC = 2.7 V to 3.6 V - - 0.3 V
IO= 12 mA; VCC = 2.7 V - - 0.6 V
IO= 24 mA; VCC = 3.0 V - - 0.8 V
ILI input leakage current VI= 5.5 Vor GND; VCC = 3.6 V - - ±20 µA
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 9 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
[1] All typical values are measured Tamb =25°C.
[2] These typical values are measured at VCC = 3.3 V.
11. Dynamic characteristics
IOZ 3-state output OFF-state
current VI=V
IH or VIL; VO= 5.5 Vor GND;
VCC = 3.6 V --±20 µA
Ioff power-off leakage supply VIor VO= 5.5 V; VCC =0V - - ±20 µA
ICC quiescent supply current VI=V
CC or GND; IO=0A;
VCC = 3.6 V --40µA
∆ICC additional quiescent
supply current per pin VI=V
CC −0.6 V; IO=0A;
VCC = 2.7 V to 3.6 V - - 5000 µA
Table 7: Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 8: Dynamic characteristics
GND = 0 V; see Figure 11 for test circuit.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =−40 °C to +85 °C[1]
tPHL, tPLH propagation delay CP to Qn see Figure 7
VCC = 1.2 V - 20 - ns
VCC = 2.7 V 1.5 - 8.9 ns
VCC = 3.0 V to 3.6 V [2] 1.5 3.7 8.0 ns
tPHL propagation delay MR to Qn see Figure 9
VCC = 1.2 V - 15 - ns
VCC = 2.7 V 1.5 - 8.8 ns
VCC = 3.0 V to 3.6 V [2] 1.5 4.1 7.9 ns
tPZH, tPZL 3-state output enable time OE to Qn see Figure 10
VCC = 1.2 V - 18 - ns
VCC = 2.7 V 1.5 - 8.3 ns
VCC = 3.0 V to 3.6 V [2] 1.5 3.3 7.2 ns
tPHZ, tPLZ 3-state output disable time OE to Qn see Figure 10
VCC = 1.2 V - 8.0 - ns
VCC = 2.7 V 1.5 - 7.1 ns
VCC = 3.0 V to 3.6 V [2] 1.5 2.9 6.0 ns
tWclock pulse width HIGH or LOW see Figure 7
VCC = 2.7 V 3.3 - - ns
VCC = 3.0 V to 3.6 V [2] 3.3 1.7 - ns
master reset pulse width HIGH or LOW see Figure 9
VCC = 2.7 V 3.3 - - ns
VCC = 3.0 V to 3.6 V [2] 3.3 1.7 - ns
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 10 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
tsu set-up time Dn to CP see Figure 8
VCC = 2.7 V 1.8 - - ns
VCC = 3.0 V to 3.6 V [2] 1.3 0.0 - ns
set-up time CE to CP see Figure 8
VCC = 2.7 V 1.0 - - ns
VCC = 3.0 V to 3.6 V [2] 1.8 −0.8 - ns
trem removal time MR see Figure 9
VCC = 2.7 V 2.0 - - ns
VCC = 3.0 V to 3.6 V [2] 1.0 −0.5 - ns
thhold time Dn to CP see Figure 8
VCC = 2.7 V 2.0 - - ns
VCC = 3.0 V to 3.6 V [2] 2.0 0.8 - ns
hold time CE to CP see Figure 8
VCC = 2.7 V 1.3 - - ns
VCC = 3.0 V to 3.6 V [2] 1.3 0.0 - ns
fmax maximum clock frequency see Figure 7
VCC = 2.7 V 150 - - MHz
VCC = 3.0 V to 3.6 V [2] 150 200 - MHz
tsk(0) skew VCC = 3.0 V to 3.6 V [3] - - 1.0 ns
CPD power dissipation capacitance per gate VCC = 3.3 V [4] [5] --
outputs enabled - 17 - pF
outputs disabled - 13 - pF
Tamb =−40 °C to +125 °C
tPHL, tPLH propagation delay CP to Qn see Figure 7
VCC = 2.7 V 1.5 - 11.5 ns
VCC = 3.0 V to 3.6 V 1.5 - 10.0 ns
tPHL propagation delay MR to Qn see Figure 9
VCC = 2.7 V 1.5 - 11.0 ns
VCC = 3.0 V to 3.6 V 1.5 - 10.0 ns
tPZH, tPZL 3-state output enable time OE to Qn see Figure 10
VCC = 2.7 V 1.5 - 10.5 ns
VCC = 3.0 V to 3.6 V 1.5 - 9.0 ns
tPHZ, tPLZ 3-state output disable time OE to Qn see Figure 10
VCC = 2.7 V 1.5 - 9.0 ns
VCC = 3.0 V to 3.6 V 1.5 - 7.5 ns
Table 8: Dynamic characteristics
…continued
GND = 0 V; see Figure 11 for test circuit.
Symbol Parameter Conditions Min Typ Max Unit
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 11 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
[1] All typical values are measured Tamb =25°C.
[2] These typical values are measured at VCC = 3.3 V.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
∑(CL×VCC2×fo) = sum of outputs.
[5] The condition is VI= GND to VCC.
tWclock pulse width HIGH or LOW see Figure 7
VCC = 2.7 V 3.3 - - ns
VCC = 3.0 V to 3.6 V 3.3 - - ns
master reset pulse width HIGH or LOW see Figure 9
VCC = 2.7 V 3.3 - - ns
VCC = 3.0 V to 3.6 V 3.3 - - ns
tsu set-up time Dn to CP see Figure 8
VCC = 2.7 V 1.8 - - ns
VCC = 3.0 V to 3.6 V 1.3 - - ns
set-up time CE to CP see Figure 8
VCC = 2.7 V 1.0 - - ns
VCC = 3.0 V to 3.6 V 1.8 - - ns
trem removal time MR see Figure 9
VCC = 2.7 V 2.0 - - ns
VCC = 3.0 V to 3.6 V 1.0 - - ns
thhold time Dn to CP see Figure 8
VCC = 2.7 V 2.0 - - ns
VCC = 3.0 V to 3.6 V 2.0 - - ns
hold time CE to CP see Figure 8
VCC = 2.7 V 1.3 - - ns
VCC = 3.0 V to 3.6 V 1.3 - - ns
fmax maximum clock frequency see Figure 7
VCC = 2.7 V 150 - - MHz
VCC = 3.0 V to 3.6 V 150 - - MHz
tsk(0) skew VCC = 3.0 V to 3.6 V [3] - - 1.5 ns
Table 8: Dynamic characteristics
…continued
GND = 0 V; see Figure 11 for test circuit.
Symbol Parameter Conditions Min Typ Max Unit
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 12 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
12. Waveforms
Measurement points are given in Table 9.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig 7. Clock to output propagation delays, clock pulse width and maximum clock pulse
frequency.
Measurement points are given in Table 9.
VOL and VOH are the typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output
performance.
Fig 8. Data set-up and hold times for data and clock enable inputs to clock input.
mna894
CP input
Qn output
tPHL tPLH
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
001aaa851
GND
GND
th
tsu th
tsu
VM
VM
VM
VI
VOH
VOL
VI
Qn output
CP input
Dn, CE input
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 13 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
Measurement points are given in Table 9.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig 9. Master reset pulse width, master reset to clock removal time and master reset to
output propagation delay.
Table 9: Measurement points
Supply voltage Input Output
VCC VMVM
1.2 V 0.5 × VCC 0.5 × VCC
2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 1.5 V 1.5 V
001aaa852
GND
GND
tW
trem
VM
VM
VI
VOH
VOL
VI
Qn output
CP input
MR input VMVM
tPHL
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 14 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
Measurement points are given in Table 10.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig 10. 3-state outputs enable and disable times.
Table 10: Measurement points
Supply voltage Input Output
VCC VMVMVXVY
1.2 V 0.5 × VCC 0.5 × VCC VOL + 0.1 V VOH − 0.1 V
2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V
3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V
mgu775
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VMVM
GND
GND
tPZL
tPZH
VM
VM
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 15 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
[1] The circuit performs better when RL= 1000 Ω.
Test data is given in Table 11.
Definitions for test circuits:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to output impedance ZO of the pulse generator.
Fig 11. Load circuitry for switching times.
Table 11: Test data
Supply voltage Input Load VEXT
VCC VICLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
1.2 V VCC 50 pF 500 Ω[1] open GND 2 × VCC
2.7 V 2.7 V 50 pF 500 Ωopen GND 2 × VCC
3.0 V to 3.6 V 2.7 V 50 pF 500 Ωopen GND 2 × VCC
VEXT
VCC
VIVO
mna616
D.U.T.
CL
RT
RL
RL
PULSE
GENERATOR
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 16 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
13. Package outline
Fig 12. Package outline SO24.
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 15.6
15.2 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT137-1
X
12
24
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
c
L
vMA
13
(A )
3
A
y
0.25
075E05 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.61
0.60 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
e
1
0 5 10 mm
scale
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
99-12-27
03-02-19
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 17 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
Fig 13. Package outline SSOP24.
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 8.4
8.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 0.8
0.4 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT340-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
112
24 13
0.25
y
pin 1 index
0 2.5 5 mm
scale
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
A
max.
2
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 18 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
Fig 14. Package outline TSSOP24.
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 7.9
7.7 4.5
4.3 0.65 6.6
6.2 0.4
0.3 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT355-1 MO-153 99-12-27
03-02-19
0.25 0.5
0.2
wM
bp
Z
e
112
24 13
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
D
y
0 2.5 5 mm
scale
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
A
max.
1.1
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 19 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
Fig 15. Package outline DHVQFN24.
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
SOT815-1 - - - - - - - - - 03-04-29
SOT815-1
0 2.5 5 mm
scale
by
y1C
C
AC
CB
vM
wM
e1
e2
terminal 1
index area
terminal 1
index area
X
UNIT A(1)
max. A1bc eEhLe1ywv
mm 10.05
0.00 0.30
0.18 0.5 4.5
e2
1.50.2 2.25
1.95
Dh
4.25
3.95 0.05 0.05
y1
0.10.1
DIMENSIONS (mm are the original dimensions)
0.5
0.3
D(1)
5.6
5.4
E(1)
3.6
3.4
D
E
BA
e
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
AA1c
detail X
Eh
L
Dh
2
23
11
14
13
12
1
24
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 20 of 22
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
14. Revision history
Table 12: Revision history
Document ID Release date Data sheet status Change notice Order number Supersedes
74LVC823A_2 20040510 Product data - 9397 750 13128 74LVC823A_1
Modifications: •The format of this data sheet has been redesigned to comply with the current presentation and
information standard of Philips Semiconductors.
•Table 2: added type number of DHVQFN24 package
•Figure 6: added pin configuration DHVQFN24
•Table 7: added values for Tamb =−40 °C to +125 °C
•Table 8: added values for Tamb =−40 °C to +125 °C.
74LVC823A_1 19980924 Product specification - 9397 750 04583 -
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
9397 750 13128 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 10 May 2004 21 of 22
15. Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
17. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
Level Data sheet status[1] Product status[2] [3] Definition
I Objective data Development This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights. Date of release: 10 May 2004
Document order number: 9397 750 13128
Published in The Netherlands
Philips Semiconductors 74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Recommended operating conditions. . . . . . . . 7
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
15 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 21
16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
17 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
18 Contact information . . . . . . . . . . . . . . . . . . . . 21
