74LVC823A 9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Rev. 02 -- 10 May 2004 Product data sheet 1. General description The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. 2. Features 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Flow-through pin-out architecture 9-bit positive edge-triggered register Independent register and 3-state buffer operation Complies with JEDEC standard JESD8-B/JESD36 ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Specified from 40 C to +85 C and -40 C to +125 C. 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. Symbol Parameter Conditions Min Typ Max Unit tPHL, tPLH propagation delay CP to Qn CL = 50 pF; VCC = 3.3 V - 3.7 - ns tPHL propagation delay MR to Qn CL = 50 pF; VCC = 3.3 V - 4.1 - ns fmax maximum clock frequency CL = 50 pF; VCC = 3.3 V - 200 - MHz CI input capacitance - 5.0 - pF power dissipation capacitance per gate CPD VCC = 3.3 V [1] [2] - - outputs enabled - 17 - pF outputs disabled - 13 - pF [1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total load switching outputs; (CL x VCC2 x fo) = sum of outputs. [2] The condition is VI = GND to VCC. 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74LVC823AD -40 C to +125 C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 74LVC823ADB -40 C to +125 C SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 74LVC823APW -40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 74LVC823ABQ -40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1 thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 2 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 5. Functional diagram 2 D0 Q0 23 3 D1 Q1 22 4 D2 Q2 21 5 D3 Q3 20 Q4 19 Q5 18 FF0 to FF8 6 D4 7 D5 8 D6 Q6 17 9 D7 Q7 16 10 D8 Q8 15 13 CP 11 MR 14 CE 1 OE 3-STATE OUTPUTS 001aaa849 Fig 1. Functional diagram. 1 11 2 3 4 5 6 7 8 9 10 MR D0 OE Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 CP 13 Q8 CE 23 G1 2 22 1C2 23 2D 21 3 22 20 4 21 19 5 20 6 19 7 18 8 17 9 16 10 15 18 17 16 15 14 001aaa847 Fig 2. Logic symbol. 001aaa848 Fig 3. IEC logic symbol. 9397 750 13128 Product data sheet R 14 13 1 EN 11 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 3 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs D0 D1 D2 D3 D4 MR CE D R Q R D CP Q CP FF0 R D Q CP FF1 R D Q D CP FF2 R Q CP FF3 FF4 CP OE Q0 D5 Q1 D6 D R Q D7 D CP Q2 R Q FF5 Q5 R Q D CP FF6 R Q CP FF7 Q6 Q4 D8 D CP Q3 FF8 Q7 Q8 001aaa850 Fig 4. Logic diagram. 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 4 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 6. Pinning information 1 24 VCC D0 2 23 Q0 D3 D4 D5 D6 D7 21 Q2 4 5 20 Q3 6 19 Q4 823 7 18 Q5 17 Q6 8 9 16 Q7 D8 10 OE 23 Q0 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 D5 7 D6 8 D7 9 D8 10 15 Q8 13 CP GND 12 19 Q4 823 18 Q5 17 Q6 16 Q7 GND(1) 15 Q8 MR 11 14 CE MR 11 2 D1 14 CE 001aaa845 CP 13 D2 22 Q1 3 D0 GND 12 D1 1 terminal 1 index area OE 24 VCC 6.1 Pinning 001aaa846 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO24 and (T)SSOP24. Fig 6. Pin configuration DHVQFN24. 6.2 Pin description Table 3: Pin description Symbol Pin Description 1 OE output enable input (active LOW) 2 D0 data input 3 D1 data input 4 D2 data input 5 D3 data input 6 D4 data input 7 D5 data input 8 D6 data input 9 D7 data input 10 D8 data input 11 MR master reset input (active LOW) 12 GND ground (0 V) 13 CP clock input (LOW-to-HIGH; edge-triggered) 14 CE clock enable input (active LOW) 15 Q8 3-state flip-flop output 16 Q7 3-state flip-flop output 17 Q6 3-state flip-flop output 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 5 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 3: Pin description ...continued Symbol Pin Description 18 Q5 3-state flip-flop output 19 Q4 3-state flip-flop output 20 Q3 3-state flip-flop output 21 Q2 3-state flip-flop output 22 Q1 3-state flip-flop output 23 Q0 3-state flip-flop output 24 VCC supply voltage 7. Functional description 7.1 Function table Table 4: Function table Operating mode [1] OE MR CE CP Dn Internal flip-flop Clear L L X X X L Load and read register L H L l L L L H L h H H Load register and disable outputs H H L l L Z H H L h H Z Hold L H H NC X NC NC [1] Input L Qn H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high-impedance OFF-state; NC = no change; = LOW-to-HIGH level transition; X = don't care. 9397 750 13128 Product data sheet Output (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 6 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input diode current VI < 0 V [1] VI input voltage IOK output diode current output voltage VO IO output source or sink current ICC, IGND VCC or GND current Tstg storage temperature Max Unit -0.5 +6.5 V - -50 mA -0.5 +6.5 V mA - 50 HIGH or LOW state [1] -0.5 VCC + 0.5 V 3-state [1] -0.5 +6.5 V - 50 mA - 100 mA -65 +150 C - 500 mW VO > VCC or VO < 0 V VO = 0 V to VCC Tamb = -40 C to +125 C power dissipation Ptot Min [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO24 packages: Ptot derates linearly with 8 mW/K above 70 C. For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN24 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Typ Max Unit for maximum speed performance 2.7 - 3.6 V for low-voltage applications 1.2 - 3.6 V 0 - 5.5 V HIGH or LOW state 0 - VCC V 3-state 0 - 5.5 V Tamb operating ambient in free air temperature -40 - +125 C tr, tf input rise and fall times VCC = 1.2 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 7 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +85 VIH VIL VOH Conditions Min Typ Max Unit VCC = 1.2 V VCC - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 1.2 V - - GND V VCC = 2.7 V to 3.6 V - - 0.8 V VCC - 0.2 VCC - V IO = -12 mA; VCC = 2.7 V VCC - 0.5 - - V IO = -18 mA; VCC = 3.0 V VCC - 0.6 - - V IO = -24 mA; VCC = 3.0 V VCC - 0.8 - - V - GND 0.2 V - - 0.4 V C [1] HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 2.7 V to 3.6 V VOL LOW-level output voltage [2] VI = VIH or VIL IO = 100 A; VCC = 2.7 V to 3.6 V [2] IO = 12 mA; VCC = 2.7 V - - 0.55 V ILI input leakage current VI = 5.5 V or GND; VCC = 3.6 V IO = 24 mA; VCC = 3.0 V - 0.1 5 A IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - 0.1 5 A Ioff power-off leakage supply VI or VO = 5.5 V; VCC = 0 V - 0.1 10 A ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - 0.1 10 A ICC additional quiescent supply current per pin VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V - 5 500 A CI input capacitance - 5.0 - pF VCC - - V [2] Tamb = -40 C to +125 C VIH HIGH-level input voltage VCC =1.2 V VCC = 2.7 V to 3.6 V 2.0 - - V VIL LOW-level input voltage VCC = 1.2 V - - GND V VCC = 2.7 V to 3.6 V - - 0.8 V VOH VOL ILI HIGH-level output voltage VI = VIH or VIL LOW-level output voltage input leakage current IO = -100 A; VCC = 2.7 V to 3.6 V VCC - 0.3 - - V IO = -12 mA; VCC = 2.7 V VCC - 0.65 - - V IO = -18 mA; VCC = 3.0 V VCC - 0.75 - - V IO = -24 mA; VCC = 3.0 V VCC - 1 - - V IO = 100 A; VCC = 2.7 V to 3.6 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.8 V - - 20 A VI = VIH or VIL VI = 5.5 V or GND; VCC = 3.6 V 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 8 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 7: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - - 20 A Ioff power-off leakage supply VI or VO = 5.5 V; VCC = 0 V - - 20 A ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - - 40 A ICC additional quiescent supply current per pin VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V - - 5000 A Min Typ Max Unit - 20 - ns 1.5 - 8.9 ns 1.5 3.7 8.0 ns - 15 - ns 1.5 - 8.8 ns 1.5 4.1 7.9 ns - 18 - ns 1.5 - 8.3 ns 1.5 3.3 7.2 ns - 8.0 - ns 1.5 - 7.1 ns 1.5 2.9 6.0 ns 3.3 - - ns 3.3 1.7 - ns 3.3 - - ns 3.3 1.7 - ns [1] All typical values are measured Tamb = 25 C. [2] These typical values are measured at VCC = 3.3 V. 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; see Figure 11 for test circuit. Symbol Parameter Tamb = -40 C to +85 Conditions C [1] tPHL, tPLH propagation delay CP to Qn see Figure 7 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHL propagation delay MR to Qn [2] see Figure 9 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tPZH, tPZL 3-state output enable time OE to Qn [2] see Figure 10 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHZ, tPLZ 3-state output disable time OE to Qn [2] see Figure 10 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tW clock pulse width HIGH or LOW [2] see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V master reset pulse width HIGH or LOW [2] see Figure 9 VCC = 2.7 V VCC = 3.0 V to 3.6 V 9397 750 13128 Product data sheet [2] (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 9 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 8: Dynamic characteristics ...continued GND = 0 V; see Figure 11 for test circuit. Symbol Parameter Conditions tsu set-up time Dn to CP see Figure 8 VCC = 2.7 V VCC = 3.0 V to 3.6 V set-up time CE to CP [2] VCC = 3.0 V to 3.6 V removal time MR [2] VCC = 3.0 V to 3.6 V hold time Dn to CP [2] VCC = 2.7 V [2] VCC = 3.0 V to 3.6 V maximum clock frequency 1.8 - - ns 1.3 0.0 - ns 1.0 - - ns 1.8 -0.8 - ns 2.0 - - ns 1.0 -0.5 - ns 2.0 - - ns 2.0 0.8 - ns 1.3 - - ns 1.3 0.0 - ns see Figure 8 VCC = 2.7 V fmax Unit see Figure 8 VCC = 3.0 V to 3.6 V hold time CE to CP Max see Figure 9 VCC = 2.7 V th Typ see Figure 8 VCC = 2.7 V trem Min [2] see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(0) skew VCC = 3.0 V to 3.6 V CPD power dissipation capacitance per gate VCC = 3.3 V 150 - - MHz [2] 150 200 - MHz [3] - - 1.0 ns [4] [5] - - outputs enabled - 17 - pF outputs disabled - 13 - pF VCC = 2.7 V 1.5 - 11.5 ns VCC = 3.0 V to 3.6 V 1.5 - 10.0 ns VCC = 2.7 V 1.5 - 11.0 ns VCC = 3.0 V to 3.6 V 1.5 - 10.0 ns VCC = 2.7 V 1.5 - 10.5 ns VCC = 3.0 V to 3.6 V 1.5 - 9.0 ns VCC = 2.7 V 1.5 - 9.0 ns VCC = 3.0 V to 3.6 V 1.5 - 7.5 ns Tamb = -40 C to +125 C tPHL, tPLH propagation delay CP to Qn tPHL tPZH, tPZL tPHZ, tPLZ propagation delay MR to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn see Figure 7 see Figure 9 see Figure 10 see Figure 10 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 10 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 8: Dynamic characteristics ...continued GND = 0 V; see Figure 11 for test circuit. Symbol Parameter Conditions tW clock pulse width HIGH or LOW see Figure 7 master reset pulse width HIGH or LOW set-up time Dn to CP tsu set-up time CE to CP removal time MR trem hold time Dn to CP th hold time CE to CP maximum clock frequency fmax tsk(0) skew Min Typ Max Unit VCC = 2.7 V 3.3 - - ns VCC = 3.0 V to 3.6 V 3.3 - - ns VCC = 2.7 V 3.3 - - ns VCC = 3.0 V to 3.6 V 3.3 - - ns VCC = 2.7 V 1.8 - - ns VCC = 3.0 V to 3.6 V 1.3 - - ns VCC = 2.7 V 1.0 - - ns VCC = 3.0 V to 3.6 V 1.8 - - ns VCC = 2.7 V 2.0 - - ns VCC = 3.0 V to 3.6 V 1.0 - - ns VCC = 2.7 V 2.0 - - ns VCC = 3.0 V to 3.6 V 2.0 - - ns VCC = 2.7 V 1.3 - - ns VCC = 3.0 V to 3.6 V 1.3 - - ns VCC = 2.7 V 150 - - MHz VCC = 3.0 V to 3.6 V 150 - - MHz - - 1.5 ns see Figure 9 see Figure 8 see Figure 8 see Figure 9 see Figure 8 see Figure 8 see Figure 7 VCC = 3.0 V to 3.6 V [3] [1] All typical values are measured Tamb = 25 C. [2] These typical values are measured at VCC = 3.3 V. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total load switching outputs; (CL x VCC2 x fo) = sum of outputs. [5] The condition is VI = GND to VCC. 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 11 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 12. Waveforms 1/f max VI CP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna894 Measurement points are given in Table 9. VOL and VOH are the typical output voltage drop that occur with the output load. Fig 7. Clock to output propagation delays, clock pulse width and maximum clock pulse frequency. VI VM CP input GND t su t su th th VI VM Dn, CE input GND VOH VM Qn output VOL 001aaa851 Measurement points are given in Table 9. VOL and VOH are the typical output voltage drop that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 8. Data set-up and hold times for data and clock enable inputs to clock input. 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 12 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs VI VM CP input GND t rem tW VI VM MR input VM GND t PHL VOH VM Qn output VOL 001aaa852 Measurement points are given in Table 9. VOL and VOH are the typical output voltage drop that occur with the output load. Fig 9. Master reset pulse width, master reset to clock removal time and master reset to output propagation delay. Table 9: Measurement points Supply voltage Input Output VCC VM VM 1.2 V 0.5 x VCC 0.5 x VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 13 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs VI OE input VM VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled mgu775 Measurement points are given in Table 10. VOL and VOH are the typical output voltage drop that occur with the output load. Fig 10. 3-state outputs enable and disable times. Table 10: Measurement points Supply voltage Input Output VCC VM VM VX 1.2 V 0.5 x VCC 0.5 x VCC VOL + 0.1 V VOH - 0.1 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 9397 750 13128 Product data sheet VY (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 14 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs VEXT VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL mna616 Test data is given in Table 11. Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance ZO of the pulse generator. Fig 11. Load circuitry for switching times. Table 11: Test data Supply voltage Input Load VCC VI CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.2 V VCC 50 pF 500 [1] open GND 2 x VCC 2.7 V 2.7 V 50 pF 500 open GND 2 x VCC 3.0 V to 3.6 V 2.7 V 50 pF 500 open GND 2 x VCC [1] VEXT The circuit performs better when RL = 1000 . 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 15 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 13. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SO24. 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 16 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index Lp L 1 12 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT340-1 JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 13. Package outline SSOP24. 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 17 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT355-1 JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 14. Package outline TSSOP24. 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 18 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm B D SOT815-1 A A E A1 c detail X terminal 1 index area C e1 terminal 1 index area e y1 C v M C A B w M C b 2 y 11 L 12 1 e2 Eh 24 13 23 14 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 5.6 5.4 4.25 3.95 3.6 3.4 2.25 1.95 0.5 4.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT815-1 --- --- --- EUROPEAN PROJECTION ISSUE DATE 03-04-29 Fig 15. Package outline DHVQFN24. 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 19 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 14. Revision history Table 12: Revision history Document ID Release date Data sheet status Change notice Order number Supersedes 74LVC823A_2 20040510 Product data - 9397 750 13128 74LVC823A_1 Modifications: 74LVC823A_1 * The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. * * * * Table 2: added type number of DHVQFN24 package Figure 6: added pin configuration DHVQFN24 Table 7: added values for Tamb = -40 C to +125 C Table 8: added values for Tamb = -40 C to +125 C. 19980924 Product specification - 9397 750 13128 Product data sheet 9397 750 04583 - (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 20 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 9397 750 13128 Product data sheet (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 -- 10 May 2004 21 of 22 74LVC823A Philips Semiconductors 9-bit D-type flip-flop with 5 V tolerant inputs/outputs 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information . . . . . . . . . . . . . . . . . . . . 21 (c) Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 10 May 2004 Document order number: 9397 750 13128 Published in The Netherlands