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89
10
11
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16
-
+
-
+
-
+
-IN A
+IN A
-IN B
+IN B
DIS B
DIS C
-IN C
+IN C -VS
OUT C
+VS
OUT B
-VS
OUT A
+VS
DIS A
LMH6738
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SNOSAC1E –APRIL 2004–REVISED MARCH 2013
LMH6738 Very Wideband, Low Distortion Triple Op Amp
Check for Samples: LMH6738
1FEATURES DESCRIPTION
2• 750 MHz −3 dB small signal bandwidth The LMH6738 is a very wideband, DC coupled
(AV= +1) monolithic operational amplifier designed specifically
•−85 dBc 3rd harmonic distortion (20 MHz) for ultra high resolution video systems as well as wide
• 2.3 nV/Hz input noise voltage dynamic range systems requiring exceptional signal
fidelity. Benefiting from TI’s current feedback
• 3300 V/μs slew rate architecture, the LMH6738 offers a gain range of ±1
• 33 mA supply current (11.3 mA per op amp) to ±10 while providing stable, operation without
• 90 mA linear output current external compensation, even at unity gain. At a gain
of +2 the LMH6738 supports ultra high resolution
• 0.02/0.01 Diff. Gain / Diff. Phase (RL= 150Ω)video systems with a 400 MHz 2 VPP –3 dB
Bandwidth. With 12-bit distortion levels through 30
APPLICATIONS MHz (RL= 100Ω), 2.3 nV/Hz input referred noise, the
• RGB video driver LMH6738 is the ideal driver or buffer for high speed
flash A/D and D/A converters. Wide dynamic range
• High resolution projectors systems such as radar and communication receivers
• Flash A/D driver requiring a wideband amplifier offering exceptional
• D/A transimpedance buffer signal purity will find the LMH6738 low input referred
• Wide dynamic range IF amp noise and low harmonic distortion make it an
attractive solution.
• Radar/communication receivers
• DDS post-amps
• Wideband inverting summer
• Line driver
CONNECTION DIAGRAM
16-Pin SSOP
Top View
See Package Number DBQ0016A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMH6738
SNOSAC1E –APRIL 2004–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
Supply Voltage (V+- V–) 13.2V
IOUT See Note (2)
Common Mode Input Voltage ±VCC
Maximum Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Soldering Information
Infrared or Convection (20 sec.) 235°C
Wave Soldering (10 sec.) 260°C
ESD Tolerance (3)
Human Body Model 2000V
Machine Model 200V
Storage Temperature Range −65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Application Section for more details.
(3) Human Body Model is 1.5 kΩin series with 100 pF. Machine Model is 0Ωin series with 200 pF.
Operating Ratings (1)
Thermal Resistance
Package (θJC) (θJA)
16-Pin SSOP 36°C/W 120°C/W
Operating Temperature Range −40°C to +85°C
Supply Voltage (V+- V–) 8V to 12V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
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Electrical Characteristics (1)
AV= +2, VCC = ±5V, RL= 100Ω, RF= 549Ω; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
Frequency Domain Performance
UGBW -3 dB Bandwidth Unity Gain, VOUT = 200 mVPP 750 MHz
SSBW -3 dB Bandwidth VOUT = 200 mVPP 480 MHz
LSBW VOUT = 2 VPP 400
0.1 dB Bandwidth VOUT = 2 VPP 150 MHz
GFPL Peaking DC to 75 MHz 0 dB
GFR1 Rolloff DC to 150 MHz, VOUT = 2 VPP 0.1 dB
GFR2 Rolloff @ 300 MHz, VOUT = 2 VPP 1.0 dB
Time Domain Response
TRS Rise and Fall Time 2V Step 0.9 ns
(10% to 90%)
TRL 5V Step 1.7
SR Slew Rate 5V Step 3300 V/µs
tsSettling Time to 0.1% 2V Step 10 ns
teEnable Time From Disable = rising edge. 7.3 ns
tdDisable Time From Disable = falling edge. 4.5 ns
Distortion
HD2L 2nd Harmonic Distortion 2 VPP, 5 MHz −80
HD2 2 VPP, 20 MHz −71 dBc
HD2H 2 VPP, 50 MHz −55
HD3L 3rd Harmonic Distortion 2 VPP, 5 MHz −90
HD3 2 VPP, 20 MHz −85 dBc
HD3H 2 VPP, 50 MHz −65
Equivalent Input Noise
VNNon-Inverting Voltage >1 MHz 2.3 nV/√Hz
ICN Inverting Current >1 MHz 12 pA/√Hz
NCN Non-Inverting Current >1 MHz 3 pA/√Hz
Video Performance
DG Differential Gain 4.43 MHz, RL= 150Ω.02 %
DP Differential Phase 4.43 MHz, RL= 150Ω.01 °
Static, DC Performance
VIO Input Offset Voltage (2) 0.5 ±2.5 mV
±4.5
IBN Input Bias Current (2) Non-Inverting −15 −7 0 µA
−20 +5
IBI Input Bias Current (2) Inverting −2 ±25 μA
±35
PSRR Power Supply Rejection Ratio (2) 50 53 dB
48.5
CMRR Common Mode Rejection Ratio (2) 46 50 dB
44
XTLK Crosstalk Input Referred, f=10MHz, Drive −80 dB
channels A,C measure channel B
ICC Supply Current (2) All three amps Enabled, No Load 32 35 mA
40
Supply Current Disabled V+RL=∞1.9 2.2 mA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. Performance is indicated in the electrical tables under conditions of internal self
heating where TJ> TA. See Applications Section for information on temperature de-rating of this device." Min/Max ratings are based on
product characterization and simulation. Individual parameters are tested as noted.
(2) Parameter 100% production tested at 25°C.
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Electrical Characteristics (1) (continued)
AV= +2, VCC = ±5V, RL= 100Ω, RF= 549Ω; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
Supply Current Disabled V−RL=∞1.1 1.3 mA
Miscellaneous Performance
RIN+ Non-Inverting Input Resistance 1000 kΩ
CIN+ Non-Inverting Input Capacitance .8 pF
RIN−Inverting Input Impedance Output impedance of input buffer. 30 Ω
ROOutput Impedance DC 0.05 Ω
VOOutput Voltage Range (2) RL= 100Ω±3.25 ±3.5
±3.1 V
RL=∞±3.65 ±3.8
±3.5
CMIR Common Mode Input Range CMRR > 40 dB ±1.9 ±2.0 V
(2) ±1.7
IOLinear Output Current VIN = 0V, VOUT < ±30 mV 80 90 mA
(3) (2) 60
ISC Short Circuit Current (4) VIN = 2V Output Shorted to Ground 160 mA
IIH Disable Pin Bias Current High Disable Pin = V+10 μA
IIL Disable Pin Bias Current Low Disable Pin = 0V −350 μA
VDMAX Voltage for Disable Disable Pin ≤VDMAX 0.8 V
VDMIM Voltage for Enable Disable Pin ≥VDMIN 2.0 V
(3) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Application Section for more details.
(4) Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application
Section for more details.
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10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
VS = 7V
VOUT = 2 VPP
VS = 9V
VS = 12.5V
10 100 1000
FREQUENCY (MHz)
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
NORMALIZED GAIN (dB)
AV = 1
AV = 2
AV = 5
VOUT = 1 VPP
10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
AV = 1, RF = 749:
AV = 2, RF = 549:
AV = 5, RF = 459:
VOUT = 0.25 VPP
10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
GAIN (dB)
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 4 VPP
AV = 2 V/V
RF = 549:
10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
AV = 1, RF = 749:
AV = 2, RF = 549:
AV = 5, RF = 459:
VOUT = 2 VPP
AV = 10, RF = 332:
10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
AV = -1, RF = 475:
AV = -2, RF = 450:
AV = -5, RF = 400:
AV = -10, RF = 500:
VOUT = 2 VPP
LMH6738
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SNOSAC1E –APRIL 2004–REVISED MARCH 2013
Typical Performance Characteristics
AV= +2, VCC = ±5V, RL= 100Ω, RF= 549Ω; unless otherwise specified).
Large Signal Frequency Response Large Signal Frequency Response
Figure 1. Figure 2.
Frequency Response
vs.
Small Signal Frequency Response VOUT
Figure 3. Figure 4.
Frequency Response
vs.
Supply Voltage Gain Flatness
Figure 5. Figure 6.
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01 2 3 4 5 67 8
VOUT (VPP)
-110
-100
-90
-80
-70
-60
-50
-40
DISTORTION (dBc)
RL = 100:
f = 10 MHz
HD3
HD2
1100
FREQUENCY (MHz)
-100
-80
-60
-40
DISTORTION (dBc)
10
-50
-70
-90
-45
-55
-65
-75
-85
-95
HD2
HD3
VOUT = 2 VPP
020 40 60 80 100 120
CAPACITIVE LOAD (pF)
0
10
20
30
40
50
60
70
80
RECOMMENDED RS (:)
LOAD = 1 k: || CL
120
0.01 11000
FREQUENCY (MHz)
MAGNITUDE, |Z| (dB:)
100
10
0.1
100
90
110
MAGNITUDE
PHASE
40
70
60
50
80
-180
-45
-90
-135
0
PHASE (°)
LMH6738
SNOSAC1E –APRIL 2004–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
AV= +2, VCC = ±5V, RL= 100Ω, RF= 549Ω; unless otherwise specified). Frequency Response
vs.
Pulse Response Capacitive Load
Figure 7. Figure 8.
Series Output Resistance
vs.
Capacitive Load Open Loop Gain and Phase
Figure 9. Figure 10.
Distortion Distortion
vs. vs.
Frequency Output Voltage
Figure 11. Figure 12.
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0.001 0.1 10 1000
0.01
0.1
10
100
100
1
0.01
1
FREQUENCY (MHz)
|Z| (:)
AV = 2 V/V
VIN = 0V
0 70 -1
1
-0.4
-0.2
0.0
0.2
0.4
0.6
OUTPUT (V)
TIME (ns)
3
10 20 30 40 50 60
-0.6
VOUT
DISABLE
DISABLE (V)
110 100 1000
FREQUENCY (MHz)
-90
-80
-70
-60
-50
-40
-30
CROSSTALK (dBc)
CH A & C VOUT = 2 VPP
MEASURE CH B
6.8 7.6 8.4 9.2 11.6 12.4
-100
-95
-85
-80
-75
-70
-65
DISTORTION (dBc)
TOTAL SUPPLY VOLTAGE (V)
-90
10 10.8
VOUT = 2VPP
f = 10 MHz
HD2
HD3
0.01 11000
FREQUENCY (MHz)
0
20
50
CMRR (dB)
100
10
0.1
40
30
10
45
35
25
15
5
LMH6738
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SNOSAC1E –APRIL 2004–REVISED MARCH 2013
Typical Performance Characteristics (continued)
AV= +2, VCC = ±5V, RL= 100Ω, RF= 549Ω; unless otherwise specified).
Distortion CMRR
vs. vs.
Supply Voltage Frequency
Figure 13. Figure 14.
PSRR Crosstalk
vs. vs.
Frequency Frequency
Figure 15. Figure 16.
Closed Loop Output Impedance |Z| Disable Timing
Figure 17. Figure 18.
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0.1 1 10 100 1000
FREQUENCY (MHz)
-100
-90
-80
-70
-60
-50
-40
-30
CROSSTALK (dBc)
VIN = 2 VPP
VS = ±5V
-40 -20 0 20 80 100
OFFSET VOLTAGE (mV)
TEMPERATURE (°C)
40 60
-0.6
-0.4
0
0.2
0.4
0.6
0.8
1
-0.2
-10
-8
-4
-2
0
2
4
6
-6
BIAS CURRENT (PA)
IBI
VOS
IBN
0.1 1 10 100 10k
kHz
1
10
100
1000
1
10
100
1000
1k
VOLTAGE NOISE (nV/
Hz)
CURRENT NOISE (pA/
Hz)
INVERTING CURRENT
NON-INVERTING CURRENT
NON-INVERTING VOLTAGE
LMH6738
SNOSAC1E –APRIL 2004–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
AV= +2, VCC = ±5V, RL= 100Ω, RF= 549Ω; unless otherwise specified).
DC Errors Input Noise
vs. vs.
Temperature Frequency
Figure 19. Figure 20.
Figure 21.
Disabled Channel Isolation
vs.
Frequency
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VOUT
+
-
VIN
+5V
-5V
CPOS
6.8 µF
RG
RF
0.01 µF
6.8 µF
CNEG
0.01 µF
RIN 0.1 µF
CSS
AV = 1 +RF/RG = VOUT/VIN
VOUT
+
-
VIN
+5V
-5V
CPOS
6.8 µF
RGRF
0.01 µF
6.8 µF
CNEG
0.01 µF
RT
25:0.1 µF
CSS
SELECT RT TO
YIELD DESIRED
RIN = RT||RG
AV = VOUT
VIN
RF
RG=
LMH6738
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SNOSAC1E –APRIL 2004–REVISED MARCH 2013
APPLICATION INFORMATION
Figure 22. Recommended Non-Inverting Gain Figure 23. Recommended Inverting Gain Circuit
Circuit
GENERAL INFORMATION
The LMH6738 is a high speed current feedback amplifier, optimized for very high speed and low distortion. The
LMH6738 has no internal ground reference so single or split supply configurations are both equally useful.
EVALUATION BOARDS
Texas Instruments provides the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the data sheet plots were measured with these boards.
Device Package Evaluation Board
Part Number
LMH6738MQA SSOP LMH730275
FEEDBACK RESISTOR SELECTION
One of the key benefits of a current feedback operational amplifier is the ability to maintain optimum frequency
response independent of gain by using appropriate values for the feedback resistor (RF). The Electrical
Characteristics and Typical Performance plots specify an RFof 550Ω, a gain of +2 V/V and ±5V power supplies
(unless otherwise specified). Generally, lowering RFfrom it’s recommended value will peak the frequency
response and extend the bandwidth while increasing the value of RFwill cause the frequency response to roll off
faster. Reducing the value of RFtoo far below it’s recommended value will cause overshoot, ringing and,
eventually, oscillation.
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1 2 3 4 5 6 7 8 9 10
0
100
200
300
400
500
600
700
800
RECOMMENDED RF (:)
|GAIN| (V/V)
NON-INVERTING (AV > 0)
INVERTING (AV < 0)
LMH6738
SNOSAC1E –APRIL 2004–REVISED MARCH 2013
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Figure 24. Recommended RFvs. Gain
See Figure 24, Recommended RF. vs Gain for selecting a feedback resistor value for gains of ±1 to ±10. Since
each application is slightly different it is worth some experimentation to find the optimal RFfor a given circuit. In
general a value of RFthat produces ~.1 dB of peaking is the best compromise between stability and maximal
bandwidth. Note that it is not possible to use a current feedback amplifier with the output shorted directly to the
inverting input. The buffer configuration of the LMH6738 requires a 750Ωfeedback resistor for stable operation.
The LMH6738 was optimized for high speed operation. As shown in Figure 24 the suggested value for RF
decreases for higher gains. Due to the impedance of the input buffer there is a practical limit for how small RFcan
go, based on the lowest practical value of RG. This limitation applies to both inverting and non inverting
configurations. For the LMH6738 the input resistance of the inverting input is approximately 30Ωand 20Ωis a
practical (but not hard and fast) lower limit for RG. The LMH6738 begins to operate in a gain bandwidth limited
fashion in the region where RGis nearly equal to the input buffer impedance. Note that the amplifier will operate
with RGvalues well below 20Ω, however results may be substantially different than predicted from ideal models.
In particular the voltage potential between the Inverting and Non Inverting inputs cannot be expected to remain
small.
Inverting gain applications that require impedance matched inputs may limit gain flexibility somewhat (especially
if maximum bandwidth is required). The impedance seen by the source is RG|| RT(RTis optional). The value of
RGis RF/Gain. Thus for an inverting gain of −7 V/V and an optimal value for RFthe input impedance is equal to
50Ω. Using a termination resistor this can be brought down to match a 25Ωsource, however, a 150Ωsource
cannot be matched. To match a 150Ωsource would require using a 1050Ωfeedback resistor and would result in
reduced bandwidth.
For more information see Application Note OA-13 (SNOA366) which describes the relationship between RFand
closed-loop frequency response for current feedback operational amplifiers. The value for the inverting input
impedance for the LMH6738 is approximately 30Ω. The LMH6738 is designed for optimum performance at gains
of +1 to +10 V/V and −1to−9 V/V. Higher gain configurations are still useful, however, the bandwidth will fall as
gain is increased, much like a typical voltage feedback amplifier.
ACTIVE FILTER
When using any current feedback Operational Amplifier as an active filter it is necessary to be careful using
reactive components in the feedback loop. Reducing the feedback impedance, especially at higher frequencies,
will almost certainly cause stability problems. Likewise capacitance on the inverting input should be avoided. See
Application Notes OA-07 (SNOA365) and OA-26 (SNOA387) for more information on Active Filter applications for
Current Feedback Op Amps.
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+
-
RIN
51:
RF
550:
X1
-
+ROUT
51:
RG
550:
CL
10 pF RL
1 k:
+
-
6.8 PF
C2
0.01 PF
RIN
75:
RG
550:
RF
550:
C3
6.8 PF
C4
X1
-
+
ROUT
75:
C1
0.01 PF
VOUT
VIN
+
-
RIN
51:
RF
550:
X1
-
+ROUT
51:
RG
550:
CL
10 pF RL
1 k:
LMH6738
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SNOSAC1E –APRIL 2004–REVISED MARCH 2013
When using the LMH6738 as a low pass filter the value of RFcan be substantially reduced from the value
recommended in the RFvs. Gain charts. The benefit of reducing RFis increased gain at higher frequencies,
which improves attenuation in the stop band. Stability problems are avoided because in the stop band additional
device bandwidth is used to cancel the input signal rather than amplify it. The benefit of this change depends on
the particulars of the circuit design. With a high pass filter configuration reducing RFwill likely result in device
instability and is not recommended.
Figure 25. Typical Video Application Figure 26. Decoupling Capacitive Loads
DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the use of a series output resistor ROUT.Figure 26 shows
the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive
loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
The charts “Suggested ROUT vs. Cap Load” give a recommended value for selecting a series output resistor for
mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the
frequency response. This gives a good compromise between settling time and bandwidth. For applications where
maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced
slightly from the recommended values.
An alternative approach is to place Rout inside the feedback loop as shown in Figure 27. This will preserve gain
accuracy, but will still limit maximum output voltage swing.
Figure 27. Series Output Resistor Inside
Feedback Loop
INVERTING INPUT PARASITIC CAPACITANCE
Parasitic capacitance is any capacitance in a circuit that was not intentionally added. It comes about from
electrical interaction between conductors. Parasitic capacitance can be reduced but never entirely eliminated.
Most parasitic capacitances that cause problems are related to board layout or lack of termination on
transmission lines. Please see the section on Layout Considerations for hints on reducing problems due to
parasitic capacitances on board traces. Transmission lines should be terminated in their characteristic
impedance at both ends.
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-40 -20 0 20 40 60 80 100
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
MAXIMUM POWER DISSIPATION (W)
TEMPERATURE (°C)
225 LFPM FORCED AIR
STILL AIR
LMH6738
SNOSAC1E –APRIL 2004–REVISED MARCH 2013
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High speed amplifiers are sensitive to capacitance between the inverting input and ground or power supplies.
This shows up as gain peaking at high frequency. The capacitor raises device gain at high frequencies by
making RGappear smaller. Capacitive output loading will exaggerate this effect. In general, avoid introducing
unnecessary parasitic capacitance at both the inverting input and the output.
One possible remedy for this effect is to slightly increase the value of the feedback (and gain set) resistor. This
will tend to offset the high frequency gain peaking while leaving other parameters relatively unchanged. If the
device has a capacitive load as well as inverting input capacitance using a series output resistor as described in
DRIVING CAPACITIVE LOADS will help.
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation board as a guide. The LMH730275 is the evaluation
board for the LMH6738.
To reduce parasitic capacitances ground and power planes should be removed near the input and output pins.
Components in the feedback loop should be placed as close to the device as possible. For long signal paths
controlled impedance lines should be used, along with impedance matching elements at both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to
ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the
smaller ceramic capacitors should be placed as close to the device as possible. The LMH6738 has multiple
power and ground pins for enhanced supply bypassing. Every pin should ideally have a separate bypass
capacitor. Sharing bypass capacitors may slightly degrade second order harmonic performance, especially if the
supply traces are thin and /or long. In Figure 22 and Figure 23 CSS is optional, but is recommended for best
second harmonic distortion. Another option to using CSS is to use pairs of .01 μF and 0.1 μF ceramic capacitors
for each supply bypass.
VIDEO PERFORMANCE
The LMH6738 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless.
Best performance will be obtained with back terminated loads. The back termination reduces reflections from the
transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier
output stage. Figure 25 shows a typical configuration for driving a 75ΩCable. The amplifier is configured for a
gain of two to make up for the 6 dB of loss in ROUT.
Figure 28. Maximum Power Dissipation
POWER DISSIPATION
The LMH6738 is optimized for maximum speed and performance in the small form factor of the standard SSOP-
16 package. To achieve its high level of performance, the LMH6738 consumes an appreciable amount of
quiescent current which cannot be neglected when considering the total package power dissipation limit. The
quiescent current contributes to about 40° C rise in junction temperature when no additional heat sink is used (VS
= ±5V, all 3 channels on). Therefore, it is easy to see the need for proper precautions to be taken in order to
make sure the junction temperature’s absolute maximum rating of 150°C is not violated.
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To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of
utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation (all 3
channels).
With the LMH6738 used in a back-terminated 75ΩRGB analog video system (with 2 VPP output voltage), the
total power dissipation is around 435 mW of which 340 mW is due to the quiescent device dissipation (output
black level at 0V). With no additional heat sink used, that puts the junction temperature to about 140° C when
operated at 85°C ambient.
To reduce the junction temperature many options are available. Forced air cooling is the easiest option. An
external add-on heat-sink can be added to the SSOP-16 package, or alternatively, additional board metal
(copper) area can be utilized as heat-sink.
An effective way to reduce the junction temperature for the SSOP-16 package (and other plastic packages) is to
use the copper board area to conduct heat. With no enhancement the major heat flow path in this package is
from the die through the metal lead frame (inside the package) and onto the surrounding copper through the
interconnecting leads. Since high frequency performance requires limited metal near the device pins the best
way to use board copper to remove heat is through the bottom of the package. A gap filler with high thermal
conductivity can be used to conduct heat from the bottom of the package to copper on the circuit board. Vias to a
ground or power plane on the back side of the circuit board will provide additional heat dissipation. A combination
of front side copper and vias to the back side can be combined as well.
Follow these steps to determine the Maximum power dissipation for the LMH6738:
1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS) VS= V+-V−
2. Calculate the RMS power dissipated in the output stage:
– PD(rms) = rms ((VS- VOUT)*IOUT) where VOUT and IOUT are the voltage and current across the external
load and VSis the total supply current
3. Calculate the total RMS power: PT= PAMP+PD
The maximum power that the LMH6738, package can dissipate at a given temperature can be derived with the
following equation (See Figure 28):
PMAX = (150º – TAMB)/ θJA, where TAMB = Ambient temperature (°C) and θJA = Thermal resistance, from junction
to ambient, for a given package (°C/W). For the SSOP package θJA is 120°C/W.
ESD PROTECTION
The LMH6738 is protected against electrostatic discharge (ESD) on all pins. The LMH6738 will survive 2000V
Human Body model and 200V Machine model events.
Under closed loop operation the ESD diodes have no effect on circuit performance. There are occasions,
however, when the ESD diodes will be evident. If the LMH6738 is driven by a large signal while the device is
powered down the ESD diodes will conduct.
The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through
the device, hence it is possible to power up a chip with a large signal applied to the input pins. Shorting the
power pins to each other will prevent the chip from being powered up through the input.
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH6738
LMH6738
SNOSAC1E –APRIL 2004–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 13
14 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6738
PACKAGE OPTION ADDENDUM
www.ti.com 13-Dec-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6738MQ/NOPB ACTIVE SSOP DBQ 16 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH67
38MQ
LMH6738MQX/NOPB ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH67
38MQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Dec-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6738MQX/NOPB SSOP DBQ 16 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Jul-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6738MQX/NOPB SSOP DBQ 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Jul-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP-.244.228
-6.195.80[ ]
.069 MAX
[1.75]
14X .0250
[0.635]
16X -.012.008
-0.300.21[ ]
2X
.175
[4.45]
TYP-.010.005
-0.250.13[ ]
0- 8 -.010.004
-0.250.11[ ]
(.041 )
[1.04]
.010
[0.25]
GAGE PLANE
-.035.016
-0.880.41[ ]
A
NOTE 3
-.197.189
-5.004.81[ ]
B
NOTE 4
-.157.150
-3.983.81[ ]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
116
.007 [0.17] C A B
9
8
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
(.213)
[5.4]
14X (.0250 )
[0.635]
16X (.063)
[1.6]
16X (.016 )
[0.41]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:8X
SYMM
1
89
16
SEE
DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
16X (.063)
[1.6]
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
(.213)
[5.4]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
89
16
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