LMH6738 www.ti.com SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 LMH6738 Very Wideband, Low Distortion Triple Op Amp Check for Samples: LMH6738 FEATURES 1 * 2 * * * * * * DESCRIPTION 750 MHz -3 dB small signal bandwidth (AV = +1) -85 dBc 3rd harmonic distortion (20 MHz) 2.3 nV/Hz input noise voltage 3300 V/s slew rate 33 mA supply current (11.3 mA per op amp) 90 mA linear output current 0.02/0.01 Diff. Gain / Diff. Phase (RL = 150) The LMH6738 is a very wideband, DC coupled monolithic operational amplifier designed specifically for ultra high resolution video systems as well as wide dynamic range systems requiring exceptional signal fidelity. Benefiting from TI's current feedback architecture, the LMH6738 offers a gain range of 1 to 10 while providing stable, operation without external compensation, even at unity gain. At a gain of +2 the LMH6738 supports ultra high resolution video systems with a 400 MHz 2 VPP -3 dB Bandwidth. With 12-bit distortion levels through 30 MHz (RL = 100), 2.3 nV/Hz input referred noise, the LMH6738 is the ideal driver or buffer for high speed flash A/D and D/A converters. Wide dynamic range systems such as radar and communication receivers requiring a wideband amplifier offering exceptional signal purity will find the LMH6738 low input referred noise and low harmonic distortion make it an attractive solution. APPLICATIONS * * * * * * * * * RGB video driver High resolution projectors Flash A/D driver D/A transimpedance buffer Wide dynamic range IF amp Radar/communication receivers DDS post-amps Wideband inverting summer Line driver CONNECTION DIAGRAM 16-Pin SSOP Top View -IN A 1 +IN A 2 DIS B 3 -IN B 4 +IN B 5 DIS C 6 -IN C 7 +IN C 8 16 + DIS A 15 +VS 14 OUT A + 13 -VS 12 OUT B 11 +VS + 10 OUT C 9 -VS See Package Number DBQ0016A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2013, Texas Instruments Incorporated LMH6738 SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) Supply Voltage (V+ - V-) 13.2V IOUT See Note Common Mode Input Voltage (2) VCC Maximum Junction Temperature +150C -65C to +150C Storage Temperature Range Soldering Information Infrared or Convection (20 sec.) 235C Wave Soldering (10 sec.) 260C ESD Tolerance (3) Human Body Model 2000V Machine Model 200V -65C to +150C Storage Temperature Range (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical Characteristics tables. The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Application Section for more details. Human Body Model is 1.5 k in series with 100 pF. Machine Model is 0 in series with 200 pF. Operating Ratings (1) Thermal Resistance Package 16-Pin SSOP - Supply Voltage (V - V ) (1) 2 (JA) 120C/W -40C to +85C Operating Temperature Range + (JC) 36C/W 8V to 12V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical Characteristics tables. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 LMH6738 www.ti.com SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 Electrical Characteristics (1) AV = +2, VCC = 5V, RL = 100, RF = 549; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Performance UGBW -3 dB Bandwidth Unity Gain, VOUT = 200 mVPP 750 SSBW -3 dB Bandwidth VOUT = 200 mVPP 480 VOUT = 2 VPP 400 LSBW MHz MHz 0.1 dB Bandwidth VOUT = 2 VPP 150 MHz GFPL Peaking DC to 75 MHz 0 dB GFR1 Rolloff DC to 150 MHz, VOUT = 2 VPP 0.1 dB GFR2 Rolloff @ 300 MHz, VOUT = 2 VPP 1.0 dB Rise and Fall Time (10% to 90%) 2V Step 0.9 5V Step 1.7 SR Slew Rate 5V Step 3300 V/s ts Settling Time to 0.1% 2V Step 10 ns te Enable Time From Disable = rising edge. 7.3 ns td Disable Time From Disable = falling edge. 4.5 ns 2nd Harmonic Distortion 2 VPP, 5 MHz -80 HD2 2 VPP, 20 MHz -71 HD2H 2 VPP, 50 MHz -55 2 VPP, 5 MHz -90 HD3 2 VPP, 20 MHz -85 HD3H 2 VPP, 50 MHz -65 Time Domain Response TRS TRL ns Distortion HD2L HD3L 3rd Harmonic Distortion dBc dBc Equivalent Input Noise VN Non-Inverting Voltage >1 MHz 2.3 nV/Hz ICN Inverting Current >1 MHz 12 pA/Hz NCN Non-Inverting Current >1 MHz 3 pA/Hz Video Performance DG Differential Gain 4.43 MHz, RL = 150 .02 % DP Differential Phase 4.43 MHz, RL = 150 .01 Static, DC Performance (2) VIO Input Offset Voltage IBN Input Bias Current (2) Non-Inverting IBI Input Bias Current (2) Inverting PSRR Power Supply Rejection Ratio CMRR Common Mode Rejection Ratio XTLK Crosstalk ICC Supply Current (2) Supply Current Disabled V+ (1) (2) 2.5 4.5 mV -7 0 +5 A -2 25 35 A 50 48.5 53 dB 46 44 50 dB Input Referred, f=10MHz, Drive channels A,C measure channel B -80 dB All three amps Enabled, No Load 32 35 40 mA RL = 1.9 2.2 mA (2) (2) -15 -20 0.5 Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. Performance is indicated in the electrical tables under conditions of internal self heating where TJ> TA. See Applications Section for information on temperature de-rating of this device." Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Parameter 100% production tested at 25C. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 3 LMH6738 SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) (continued) AV = +2, VCC = 5V, RL = 100, RF = 549; unless otherwise specified. Symbol Parameter Conditions - Supply Current Disabled V Min RL = Typ Max Units 1.1 1.3 mA Miscellaneous Performance RIN+ Non-Inverting Input Resistance CIN+ Non-Inverting Input Capacitance RIN- Inverting Input Impedance Output impedance of input buffer. RO Output Impedance DC VO Output Voltage Range (2) 1000 k .8 pF 30 0.05 RL = 100 3.25 3.1 3.5 RL = 3.65 3.5 3.8 1.9 1.7 2.0 V 80 60 90 mA V CMIR Common Mode Input Range CMRR > 40 dB IO Linear Output Current VIN = 0V, VOUT < 30 mV ISC Short Circuit Current VIN = 2V Output Shorted to Ground 160 mA IIH Disable Pin Bias Current High Disable Pin = V+ 10 A IIL Disable Pin Bias Current Low Disable Pin = 0V -350 VDMAX Voltage for Disable Disable Pin VDMAX VDMIM Voltage for Enable Disable Pin VDMIN (3) (4) 4 (2) (3) (2) (4) A 0.8 2.0 V V The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Application Section for more details. Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application Section for more details. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 LMH6738 www.ti.com SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 Typical Performance Characteristics AV = +2, VCC = 5V, RL = 100, RF = 549; unless otherwise specified). Large Signal Frequency Response 1 0 0 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) Large Signal Frequency Response 1 AV = 1, RF = 749: -2 AV = 2, RF = 549: -3 -4 AV = 5, RF = 459: -5 AV = 10, RF = 332: -6 -7 -8 -1 AV = -1, RF = 475: -2 -3 AV = -2, RF = 450: -4 AV = -5, RF = 400: -5 AV = -10, RF = 500: -6 -7 -8 VOUT = 2 VPP VOUT = 2 VPP -9 -9 10 100 10 1000 100 FREQUENCY (MHz) Figure 2. Small Signal Frequency Response Frequency Response vs. VOUT 1 1 0 0 -1 -1 AV = 1, RF = 749: -2 AV = 2, RF = 549: -4 -5 AV = 5, RF = 459: -6 VOUT = 4 VPP -2 -3 -3 VOUT = 2 VPP -4 -5 VOUT = 1 VPP -6 -7 -7 -8 -8 VOUT = 0.25 VPP 10 100 1000 FREQUENCY (MHz) VOUT = 0.5 VPP AV = 2 V/V RF = 549: -9 10 -9 100 FREQUENCY (MHz) Figure 3. 0.5 0 0.4 -1 0.3 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) Gain Flatness 1 VS = 7V -2 -3 VS = 9V -4 -5 VS = 12.5V -6 -7 VOUT = 2 VPP -9 10 100 1000 Figure 4. Frequency Response vs. Supply Voltage -8 1000 Figure 1. GAIN (dB) NORMALIZED GAIN (dB) FREQUENCY (MHz) 1000 AV = 1 0.2 AV = 2 0.1 0 -0.1 -0.2 AV = 5 -0.3 -0.4 VOUT = 1 VPP -0.5 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Figure 6. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 5 LMH6738 SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) AV = +2, VCC = 5V, RL = 100, RF = 549; unless otherwise specified). Frequency Response vs. Capacitive Load Pulse Response 1.5 2 1 0 0.5 -2 CL = 4.7 pF, RS = 70: GAIN (dB) VOUT (V) CL = 15 pF, RS = 44: 0 CL = 47 pF, RS = 24: -4 CL = 100 pF, RS = 17: -0.5 -6 -1 -8 VOUT = 1 VPP, CL || 1 k: -1.5 -10 0 4 8 12 16 20 1 10 100 1000 FREQUENCY (MHz) TIME (ns) Figure 7. Figure 8. Series Output Resistance vs. Capacitive Load Open Loop Gain and Phase 80 120 LOAD = 1 k: || CL 110 MAGNITUDE 60 50 40 30 20 100 90 80 0 70 -45 -90 60 PHASE 10 -135 50 0 0 20 40 60 80 100 120 40 0.01 -180 1000 100 FREQUENCY (MHz) Figure 9. Figure 10. Distortion vs. Frequency Distortion vs. Output Voltage -40 -40 RL = 100: f = 10 MHz VOUT = 2 VPP -45 -50 -50 -55 DISTORTION (dBc) DISTORTION (dBc) 10 1 0.1 CAPACITIVE LOAD (pF) -60 -65 HD2 -70 -75 -80 -85 -90 -60 HD3 -70 -80 HD2 -90 -100 -95 -100 HD3 -110 1 10 100 FREQUENCY (MHz) 0 1 2 3 4 5 6 7 8 VOUT (VPP) Figure 11. 6 PHASE () MAGNITUDE, |Z| (dB:) RECOMMENDED RS (:) 70 Figure 12. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 LMH6738 www.ti.com SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 Typical Performance Characteristics (continued) AV = +2, VCC = 5V, RL = 100, RF = 549; unless otherwise specified). Distortion vs. Supply Voltage CMRR vs. Frequency 50 -65 VOUT = 2VPP f = 10 MHz HD2 -70 45 35 CMRR (dB) DISTORTION (dBc) 40 -75 -80 HD3 -85 30 25 20 15 -90 10 -95 5 -100 0 6.8 7.6 8.4 9.2 0.01 10.8 11.6 12.4 10 Figure 13. Figure 14. PSRR vs. Frequency Crosstalk vs. Frequency 1000 -30 60 CH A & C VOUT = 2 VPP PSRR + 50 MEASURE CH B -40 CROSSTALK (dBc) PSRR 40 PSRR (dB) 100 FREQUENCY (MHz) TOTAL SUPPLY VOLTAGE (V) 30 20 10 -50 -60 -70 -80 0 -90 0.1 1 10 100 1 1000 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Figure 16. Closed Loop Output Impedance |Z| Disable Timing 0.6 100 AV = 2 V/V 0.4 VIN = 0V VOUT OUTPUT (V) 1 DISABLE (V) 0.2 10 |Z| (:) 10 1 0.1 0.0 -0.2 -0.4 -0.6 0.1 3 1 DISABLE 0.01 0.001 0.01 -1 0.1 1 10 100 1000 0 10 20 30 40 50 60 70 TIME (ns) FREQUENCY (MHz) Figure 17. Figure 18. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 7 LMH6738 SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) AV = +2, VCC = 5V, RL = 100, RF = 549; unless otherwise specified). DC Errors vs. Temperature Input Noise vs. Frequency 1 6 1000 1000 0.6 2 0.4 0 VOS 0.2 -2 0 -4 -0.2 -6 -0.4 100 INVERTING CURRENT NO N CU RR EN T 10 10 -8 IBN -0.6 -40 -IN VER TIN G 100 CURRENT NOISE (pA/ Hz) 4 VOLTAGE NOISE (nV/ Hz) 0.8 BIAS CURRENT (PA) OFFSET VOLTAGE (mV) IBI -10 -20 0 20 40 60 80 NON-INVERTING VOLTAGE 1 100 0.1 1 10 100 1 1k 10k kHz TEMPERATURE (C) Figure 19. Figure 20. Figure 21. Disabled Channel Isolation vs. Frequency -30 CROSSTALK (dBc) -40 VIN = 2 VPP VS = 5V -50 -60 -70 -80 -90 -100 0.1 1 10 100 1000 FREQUENCY (MHz) 8 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 LMH6738 www.ti.com SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 APPLICATION INFORMATION +5V 0.01 F VIN RIN +5V 6.8 F 6.8 F AV = 1 +RF/RG = VOUT/VIN 0.01 F CPOS VOUT 25: - + CSS 0.1 F - CNEG 0.01 F RG = VOUT VIN CPOS + CSS 0.1 F RF AV = RF VIN RG RG -5V CNEG 0.01 F RT 6.8 F VOUT 6.8 F -5V Figure 22. Recommended Non-Inverting Gain Circuit RF SELECT RT TO YIELD DESIRED RIN = RT||RG Figure 23. Recommended Inverting Gain Circuit GENERAL INFORMATION The LMH6738 is a high speed current feedback amplifier, optimized for very high speed and low distortion. The LMH6738 has no internal ground reference so single or split supply configurations are both equally useful. EVALUATION BOARDS Texas Instruments provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. Many of the data sheet plots were measured with these boards. Device Package Evaluation Board Part Number LMH6738MQA SSOP LMH730275 FEEDBACK RESISTOR SELECTION One of the key benefits of a current feedback operational amplifier is the ability to maintain optimum frequency response independent of gain by using appropriate values for the feedback resistor (RF). The Electrical Characteristics and Typical Performance plots specify an RF of 550, a gain of +2 V/V and 5V power supplies (unless otherwise specified). Generally, lowering RF from it's recommended value will peak the frequency response and extend the bandwidth while increasing the value of RF will cause the frequency response to roll off faster. Reducing the value of RF too far below it's recommended value will cause overshoot, ringing and, eventually, oscillation. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 9 LMH6738 SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 www.ti.com 800 RECOMMENDED RF (:) 700 600 NON-INVERTING (AV > 0) 500 400 300 INVERTING (AV < 0) 200 100 0 1 2 3 4 5 6 7 8 9 10 |GAIN| (V/V) Figure 24. Recommended RF vs. Gain See Figure 24, Recommended RF. vs Gain for selecting a feedback resistor value for gains of 1 to 10. Since each application is slightly different it is worth some experimentation to find the optimal RF for a given circuit. In general a value of RF that produces ~.1 dB of peaking is the best compromise between stability and maximal bandwidth. Note that it is not possible to use a current feedback amplifier with the output shorted directly to the inverting input. The buffer configuration of the LMH6738 requires a 750 feedback resistor for stable operation. The LMH6738 was optimized for high speed operation. As shown in Figure 24 the suggested value for RF decreases for higher gains. Due to the impedance of the input buffer there is a practical limit for how small RFcan go, based on the lowest practical value of RG. This limitation applies to both inverting and non inverting configurations. For the LMH6738 the input resistance of the inverting input is approximately 30 and 20 is a practical (but not hard and fast) lower limit for RG. The LMH6738 begins to operate in a gain bandwidth limited fashion in the region where RG is nearly equal to the input buffer impedance. Note that the amplifier will operate with RG values well below 20, however results may be substantially different than predicted from ideal models. In particular the voltage potential between the Inverting and Non Inverting inputs cannot be expected to remain small. Inverting gain applications that require impedance matched inputs may limit gain flexibility somewhat (especially if maximum bandwidth is required). The impedance seen by the source is RG || RT (RT is optional). The value of RG is RF /Gain. Thus for an inverting gain of -7 V/V and an optimal value for RF the input impedance is equal to 50. Using a termination resistor this can be brought down to match a 25 source, however, a 150 source cannot be matched. To match a 150 source would require using a 1050 feedback resistor and would result in reduced bandwidth. For more information see Application Note OA-13 (SNOA366) which describes the relationship between RF and closed-loop frequency response for current feedback operational amplifiers. The value for the inverting input impedance for the LMH6738 is approximately 30. The LMH6738 is designed for optimum performance at gains of +1 to +10 V/V and -1 to -9 V/V. Higher gain configurations are still useful, however, the bandwidth will fall as gain is increased, much like a typical voltage feedback amplifier. ACTIVE FILTER When using any current feedback Operational Amplifier as an active filter it is necessary to be careful using reactive components in the feedback loop. Reducing the feedback impedance, especially at higher frequencies, will almost certainly cause stability problems. Likewise capacitance on the inverting input should be avoided. See Application Notes OA-07 (SNOA365) and OA-26 (SNOA387) for more information on Active Filter applications for Current Feedback Op Amps. 10 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 LMH6738 www.ti.com SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 When using the LMH6738 as a low pass filter the value of RF can be substantially reduced from the value recommended in the RF vs. Gain charts. The benefit of reducing RF is increased gain at higher frequencies, which improves attenuation in the stop band. Stability problems are avoided because in the stop band additional device bandwidth is used to cancel the input signal rather than amplify it. The benefit of this change depends on the particulars of the circuit design. With a high pass filter configuration reducing RF will likely result in device instability and is not recommended. X1 6.8 PF + C2 0.01 PF RIN 51: RG 550: - + - ROUT 51: CL 10 pF RL 1 k: C1 RIN 75: RF 550: X1 VIN + RG 550: - + VOUT ROUT 75: - RF 550: 0.01 PF C3 6.8 PF C4 Figure 25. Typical Video Application Figure 26. Decoupling Capacitive Loads DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 26 shows the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. The charts "Suggested ROUT vs. Cap Load" give a recommended value for selecting a series output resistor for mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the frequency response. This gives a good compromise between settling time and bandwidth. For applications where maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values. An alternative approach is to place Rout inside the feedback loop as shown in Figure 27. This will preserve gain accuracy, but will still limit maximum output voltage swing. X1 + + RIN 51: RG 550: - - ROUT 51: CL 10 pF RL 1 k: RF 550: Figure 27. Series Output Resistor Inside Feedback Loop INVERTING INPUT PARASITIC CAPACITANCE Parasitic capacitance is any capacitance in a circuit that was not intentionally added. It comes about from electrical interaction between conductors. Parasitic capacitance can be reduced but never entirely eliminated. Most parasitic capacitances that cause problems are related to board layout or lack of termination on transmission lines. Please see the section on Layout Considerations for hints on reducing problems due to parasitic capacitances on board traces. Transmission lines should be terminated in their characteristic impedance at both ends. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 11 LMH6738 SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 www.ti.com High speed amplifiers are sensitive to capacitance between the inverting input and ground or power supplies. This shows up as gain peaking at high frequency. The capacitor raises device gain at high frequencies by making RG appear smaller. Capacitive output loading will exaggerate this effect. In general, avoid introducing unnecessary parasitic capacitance at both the inverting input and the output. One possible remedy for this effect is to slightly increase the value of the feedback (and gain set) resistor. This will tend to offset the high frequency gain peaking while leaving other parameters relatively unchanged. If the device has a capacitive load as well as inverting input capacitance using a series output resistor as described in DRIVING CAPACITIVE LOADS will help. LAYOUT CONSIDERATIONS Whenever questions about layout arise, use the evaluation board as a guide. The LMH730275 is the evaluation board for the LMH6738. To reduce parasitic capacitances ground and power planes should be removed near the input and output pins. Components in the feedback loop should be placed as close to the device as possible. For long signal paths controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller ceramic capacitors should be placed as close to the device as possible. The LMH6738 has multiple power and ground pins for enhanced supply bypassing. Every pin should ideally have a separate bypass capacitor. Sharing bypass capacitors may slightly degrade second order harmonic performance, especially if the supply traces are thin and /or long. In Figure 22 and Figure 23 CSS is optional, but is recommended for best second harmonic distortion. Another option to using CSS is to use pairs of .01 F and 0.1 F ceramic capacitors for each supply bypass. VIDEO PERFORMANCE The LMH6738 has been designed to provide excellent performance with production quality video signals in a wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless. Best performance will be obtained with back terminated loads. The back termination reduces reflections from the transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier output stage. Figure 25 shows a typical configuration for driving a 75 Cable. The amplifier is configured for a gain of two to make up for the 6 dB of loss in ROUT. MAXIMUM POWER DISSIPATION (W) 2 1.8 225 LFPM FORCED AIR 1.6 1.4 1.2 1 STILL AIR 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 28. Maximum Power Dissipation POWER DISSIPATION The LMH6738 is optimized for maximum speed and performance in the small form factor of the standard SSOP16 package. To achieve its high level of performance, the LMH6738 consumes an appreciable amount of quiescent current which cannot be neglected when considering the total package power dissipation limit. The quiescent current contributes to about 40 C rise in junction temperature when no additional heat sink is used (VS = 5V, all 3 channels on). Therefore, it is easy to see the need for proper precautions to be taken in order to make sure the junction temperature's absolute maximum rating of 150C is not violated. 12 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 LMH6738 www.ti.com SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation (all 3 channels). With the LMH6738 used in a back-terminated 75 RGB analog video system (with 2 VPP output voltage), the total power dissipation is around 435 mW of which 340 mW is due to the quiescent device dissipation (output black level at 0V). With no additional heat sink used, that puts the junction temperature to about 140 C when operated at 85C ambient. To reduce the junction temperature many options are available. Forced air cooling is the easiest option. An external add-on heat-sink can be added to the SSOP-16 package, or alternatively, additional board metal (copper) area can be utilized as heat-sink. An effective way to reduce the junction temperature for the SSOP-16 package (and other plastic packages) is to use the copper board area to conduct heat. With no enhancement the major heat flow path in this package is from the die through the metal lead frame (inside the package) and onto the surrounding copper through the interconnecting leads. Since high frequency performance requires limited metal near the device pins the best way to use board copper to remove heat is through the bottom of the package. A gap filler with high thermal conductivity can be used to conduct heat from the bottom of the package to copper on the circuit board. Vias to a ground or power plane on the back side of the circuit board will provide additional heat dissipation. A combination of front side copper and vias to the back side can be combined as well. Follow these steps to determine the Maximum power dissipation for the LMH6738: 1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS) VS = V+-V- 2. Calculate the RMS power dissipated in the output stage: - PD (rms) = rms ((VS - VOUT)*IOUT) where VOUT and IOUT are the voltage and current across the external load and VS is the total supply current 3. Calculate the total RMS power: PT = PAMP+PD The maximum power that the LMH6738, package can dissipate at a given temperature can be derived with the following equation (See Figure 28): PMAX = (150 - TAMB)/ JA, where TAMB = Ambient temperature (C) and JA = Thermal resistance, from junction to ambient, for a given package (C/W). For the SSOP package JA is 120C/W. ESD PROTECTION The LMH6738 is protected against electrostatic discharge (ESD) on all pins. The LMH6738 will survive 2000V Human Body model and 200V Machine model events. Under closed loop operation the ESD diodes have no effect on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6738 is driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to power up a chip with a large signal applied to the input pins. Shorting the power pins to each other will prevent the chip from being powered up through the input. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 13 LMH6738 SNOSAC1E - APRIL 2004 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E * 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6738 PACKAGE OPTION ADDENDUM www.ti.com 13-Dec-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMH6738MQ/NOPB ACTIVE SSOP DBQ 16 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH67 38MQ LMH6738MQX/NOPB ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH67 38MQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Jul-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMH6738MQX/NOPB Package Package Pins Type Drawing SSOP DBQ 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 5.4 2.0 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Jul-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6738MQX/NOPB SSOP DBQ 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBQ0016A SSOP - 1.75 mm max height SCALE 2.800 SHRINK SMALL-OUTLINE PACKAGE C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 16 1 14X .0250 [0.635] 2X .175 [4.45] .189-.197 [4.81-5.00] NOTE 3 8 9 B .150-.157 [3.81-3.98] NOTE 4 16X .008-.012 [0.21-0.30] .007 [0.17] C A B .069 MAX [1.75] .005-.010 TYP [0.13-0.25] SEE DETAIL A .010 [0.25] GAGE PLANE .004-.010 [0.11-0.25] 0 -8 .016-.035 [0.41-0.88] (.041 ) [1.04] DETAIL A TYPICAL 4214846/A 03/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MO-137, variation AB. www.ti.com EXAMPLE BOARD LAYOUT DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SEE DETAILS SYMM 1 16 16X (.016 ) [0.41] 14X (.0250 ) [0.635] 9 8 (.213) [5.4] LAND PATTERN EXAMPLE SCALE:8X METAL SOLDER MASK OPENING SOLDER MASK OPENING .002 MAX [0.05] ALL AROUND METAL .002 MIN [0.05] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214846/A 03/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM 1 16 16X (.016 ) [0.41] SYMM 14X (.0250 ) [0.635] 9 8 (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X 4214846/A 03/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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